<?xml version="1.0" encoding="UTF-8"?><rss xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:atom="http://www.w3.org/2005/Atom" version="2.0"><channel><title><![CDATA[T113S3 主线内核 如何使能EMAC 25MHz时钟]]></title><description><![CDATA[<p dir="auto">内核版本是6.12.35<br />
内核日志如下:<br />
[    0.264623] dwmac-sun8i 4500000.ethernet: IRQ eth_wake_irq not found<br />
[    0.268356] ehci-platform 4200000.usb: irq 36, io mem 0x04200000<br />
[    0.272992] dwmac-sun8i 4500000.ethernet: IRQ eth_lpi not found<br />
[    0.273002] dwmac-sun8i 4500000.ethernet: IRQ sfty not found<br />
[    0.273382] dwmac-sun8i 4500000.ethernet: PTP uses main clock<br />
[    0.275620] hub 2-0:1.0: 1 port detected<br />
[    0.281819] dwmac-sun8i 4500000.ethernet: Current syscon value is not the default 58000 (expect 0)<br />
[    0.303961] ehci-platform 4200000.usb: USB 2.0 started, EHCI 1.00<br />
[    0.314219] dwmac-sun8i 4500000.ethernet: No HW DMA feature register supported<br />
[    0.319352] hub 1-0:1.0: USB hub found<br />
[    0.323451] dwmac-sun8i 4500000.ethernet: RX Checksum Offload Engine supported<br />
[    0.329956] hub 1-0:1.0: 1 port detected<br />
[    0.339431] dwmac-sun8i 4500000.ethernet: COE Type 2<br />
[    0.623933] usb 1-1: new high-speed USB device number 2 using ehci-platform<br />
[    0.629268] dwmac-sun8i 4500000.ethernet: TX Checksum insertion supported<br />
[    0.815287] hub 1-1:1.0: USB hub found<br />
[    0.819142] dwmac-sun8i 4500000.ethernet: Normal descriptors<br />
[    0.827001] hub 1-1:1.0: 4 ports detected<br />
[    0.835403] dwmac-sun8i 4500000.ethernet: Chain mode enabled<br />
[    1.263936] usb 1-1.3: new high-speed USB device number 3 using ehci-platform<br />
[    1.537277] dwmac-sun8i 4500000.ethernet: EMAC reset timeout<br />
[    1.542964] dwmac-sun8i 4500000.ethernet eth0: stmmac_dvr_remove: removing driver<br />
[    1.584892] dwmac-sun8i 4500000.ethernet: probe with driver dwmac-sun8i failed with error -110<br />
设备树配置如下:<br />
&amp;emac {<br />
pinctrl-0 = &lt;&amp;rmii_pg_clk25m_pins&gt;;<br />
pinctrl-names = "default";<br />
phy-mode = "rmii";<br />
phy-handle = &lt;&amp;ip101gr&gt;;<br />
phy-supply = &lt;&amp;reg_3v3&gt;;<br />
clocks = &lt;&amp;ccu CLK_BUS_EMAC&gt;,&lt;&amp;ccu CLK_EMAC_25M&gt;;<br />
clock-names = "stmmaceth","ephy25m";<br />
use_ephy25m = &lt;1&gt;;<br />
status = "okay";<br />
};</p>
<p dir="auto">&amp;mdio{<br />
status = "okay";<br />
reset-assert-us = &lt;10000&gt;;<br />
reset-post-delay-us = &lt;150000&gt;;<br />
reset-deassert-us = &lt;150000&gt;;<br />
reset-gpios = &lt;&amp;pio 6 6 GPIO_ACTIVE_LOW&gt;; /* PG6 */<br />
ip101gr: ethernet-phy@0 {<br />
// compatible = "ethernet-phy-ieee802.3-c22";<br />
// compatible = "ethernet-phy-id001c.c816";<br />
compatible = "ethernet-phy-id0243.0c54","ethernet-phy-ieee802.3-c22";<br />
reg = &lt;0&gt;;<br />
};<br />
};</p>
<p dir="auto">现在的问题是我没办法识别出PHY，而且用示波器去看EPHY-25M引脚也没有时钟输出，问一下主线内核该怎么开启内部时钟输出？</p>
]]></description><link>https://bbs.aw-ol.com/topic/6540/t113s3-主线内核-如何使能emac-25mhz时钟</link><generator>RSS for Node</generator><lastBuildDate>Sat, 16 May 2026 20:34:40 GMT</lastBuildDate><atom:link href="https://bbs.aw-ol.com/topic/6540.rss" rel="self" type="application/rss+xml"/><pubDate>Mon, 04 Aug 2025 16:08:39 GMT</pubDate><ttl>60</ttl><item><title><![CDATA[Reply to T113S3 主线内核 如何使能EMAC 25MHz时钟 on Fri, 03 Oct 2025 09:30:38 GMT]]></title><description><![CDATA[<p dir="auto">我对icplus的修改（内核版本6.12.0）：</p>
<pre><code>diff --git a/drivers/net/phy/icplus.c b/drivers/net/phy/icplus.c
index a00a667454a9..411ca8fbb30e 100644
--- a/drivers/net/phy/icplus.c
+++ b/drivers/net/phy/icplus.c
@@ -21,6 +21,7 @@
 #include &lt;linux/ethtool.h&gt;
 #include &lt;linux/phy.h&gt;
 #include &lt;linux/property.h&gt;
+#include &lt;linux/clk.h&gt;
 
 #include &lt;asm/io.h&gt;
 #include &lt;asm/irq.h&gt;
@@ -89,6 +90,7 @@ static struct ip101g_hw_stat ip101g_hw_stats[] = {
 struct ip101a_g_phy_priv {
 	enum ip101gr_sel_intr32 sel_intr32;
 	u64 stats[ARRAY_SIZE(ip101g_hw_stats)];
+	struct clk *clk;
 };
 
 static int ip175c_config_init(struct phy_device *phydev)
@@ -210,6 +212,11 @@ static int ip101a_g_probe(struct phy_device *phydev)
 	if (!priv)
 		return -ENOMEM;
 
+	priv-&gt;clk = devm_clk_get_optional_enabled(dev, NULL);
+	if (IS_ERR(priv-&gt;clk))
+		return dev_err_probe(dev, PTR_ERR(priv-&gt;clk),
+				     "failed to get phy clock\n");
+
 	/* Both functions (RX error and interrupt status) are sharing the same
 	 * pin on the 32-pin IP101GR, so this is an exclusive choice.
 	 */
@@ -571,6 +578,33 @@ static void ip101g_get_stats(struct phy_device *phydev,
 		data[i] = ip101g_get_stat(phydev, i);
 }
 
+static int ip101a_g_suspend(struct phy_device *phydev)
+{
+	struct ip101a_g_phy_priv *priv = phydev-&gt;priv;
+	int ret = 0;
+
+	if (!phydev-&gt;wol_enabled) {
+		ret = genphy_suspend(phydev);
+
+		if (ret)
+			return ret;
+
+		clk_disable_unprepare(priv-&gt;clk);
+	}
+
+	return ret;
+}
+
+static int ip101a_g_resume(struct phy_device *phydev)
+{
+	struct ip101a_g_phy_priv *priv = phydev-&gt;priv;
+
+	if (!phydev-&gt;wol_enabled)
++		clk_prepare_enable(priv-&gt;clk);
+
+	return genphy_resume(phydev);
+}
+
 static struct phy_driver icplus_driver[] = {
 {
 	PHY_ID_MATCH_MODEL(IP175C_PHY_ID),
@@ -601,8 +635,9 @@ static struct phy_driver icplus_driver[] = {
 	.config_aneg	= ip101a_g_config_aneg,
 	.read_status	= ip101a_g_read_status,
 	.soft_reset	= genphy_soft_reset,
-	.suspend	= genphy_suspend,
-	.resume		= genphy_resume,
+	.suspend	= ip101a_g_suspend,
+	.resume		= ip101a_g_resume,
+	.flags		= PHY_ALWAYS_CALL_SUSPEND,
 }, {
 	.name		= "ICPlus IP101G",
 	.match_phy_device = ip101g_match_phy_device,
@@ -618,8 +653,9 @@ static struct phy_driver icplus_driver[] = {
 	.get_sset_count = ip101g_get_sset_count,
 	.get_strings	= ip101g_get_strings,
 	.get_stats	= ip101g_get_stats,
-	.suspend	= genphy_suspend,
-	.resume		= genphy_resume,
+	.suspend	= ip101a_g_suspend,
+	.resume		= ip101a_g_resume,
+	.flags		= PHY_ALWAYS_CALL_SUSPEND,
 } };
 
 module_phy_driver(icplus_driver);
</code></pre>
<pre><code>&amp;emac {
	pinctrl-names = "default";
	pinctrl-0 = &lt;&amp;rmii_pg_pins&gt;;
	phy-mode = "rmii";
	phy-handle = &lt;&amp;phy1&gt;;
	phy-supply = &lt;&amp;reg_vcc3v3&gt;;
	status = "okay";
};

&amp;mdio {
	status = "okay";

	phy1: ethernet-phy@1 {
		compatible = "ethernet-phy-ieee802.3-c22";
		reg = &lt;1&gt;;
		reset-gpios = &lt;&amp;pio 6 6 GPIO_ACTIVE_LOW&gt;; /* PG6 */
		reset-assert-us = &lt;5000&gt;;
		reset-deassert-us = &lt;5000&gt;;
		clocks = &lt;&amp;ccu CLK_EMAC_25M&gt;;
	};
};
</code></pre>
]]></description><link>https://bbs.aw-ol.com/post/27267</link><guid isPermaLink="true">https://bbs.aw-ol.com/post/27267</guid><dc:creator><![CDATA[asf66]]></dc:creator><pubDate>Fri, 03 Oct 2025 09:30:38 GMT</pubDate></item><item><title><![CDATA[Reply to T113S3 主线内核 如何使能EMAC 25MHz时钟 on Tue, 30 Sep 2025 16:21:36 GMT]]></title><description><![CDATA[<p dir="auto">参照这个补丁修改对应的phy驱动：<br />
<a href="https://lore.kernel.org/netdev/20230605154010.49611-2-detlev.casanova@collabora.com/T/#u" target="_blank" rel="noopener noreferrer nofollow ugc">https://lore.kernel.org/netdev/20230605154010.49611-2-detlev.casanova@collabora.com/T/#u</a><br />
然后在设备树phy节点添加 clocks = &lt;&amp;ccu CLK_EMAC_25M&gt;;</p>
]]></description><link>https://bbs.aw-ol.com/post/27266</link><guid isPermaLink="true">https://bbs.aw-ol.com/post/27266</guid><dc:creator><![CDATA[asf66]]></dc:creator><pubDate>Tue, 30 Sep 2025 16:21:36 GMT</pubDate></item><item><title><![CDATA[Reply to T113S3 主线内核 如何使能EMAC 25MHz时钟 on Tue, 05 Aug 2025 02:48:26 GMT]]></title><description><![CDATA[<p dir="auto">主线内核需要IRC去问一下主线的实现，<a href="https://linux-sunxi.org/IRC" target="_blank" rel="noopener noreferrer nofollow ugc">https://linux-sunxi.org/IRC</a></p>
]]></description><link>https://bbs.aw-ol.com/post/26845</link><guid isPermaLink="true">https://bbs.aw-ol.com/post/26845</guid><dc:creator><![CDATA[awwwwa]]></dc:creator><pubDate>Tue, 05 Aug 2025 02:48:26 GMT</pubDate></item></channel></rss>