T113 longan uboot无输出

[wxgd2017]

修改了uart0 到PF2/PF4 ，但是uboot阶段无输出，请问下还需要修改哪里？sys_config.fex 已经注释了sd0的配置信息

HELLO! BOOT0 is starting!
[32]BOOT0 commit : 5224261
[35]set pll start
[40]periph0 has been enabled
[43]set pll end
[45][pmu]: bus read error
[47]board init ok
[49]enable_jtag
[51]ZQ value = 0x31
[53]get_pmu_exist() = -1
[55]DRAM BOOT DRIVE INFO: V0.32
[58]DRAM CLK = 792 MHz
[60]DRAM Type = 3 (2:DDR2,3:DDR3)
[64]DRAMC read ODT  off.
[66]DRAM ODT value: 0x42.
[69]ddr_efuse_type: 0xa
[71]mark_id: 0x60
[73]DRAM SIZE =128 M
[75]PLL_DDR_CTRL_REG:0xf8004100
[78]DRAM_CLK_REG:0xc0000000
[81][TIMING DEBUG] MR2= 0x18
[88]DRAM simple test OK.
[91]rtc standby flag is 0x0, super standby flag is 0x0
[96]dram size =128
[98]spinand UBOOT_START_BLK_NUM 8 UBOOT_LAST_BLK_NUM 32
[104]block from 8 to 32
[243]Check is correct.
[245]dma 0x29c4c int is not used yet
[248]dma 0x29c4c int is free, you do not need to free it again
[254]Entry_name        = u-boot
[261]Entry_name        = optee
[265]Entry_name        = dtb
[268]Jump to second Boot.
M/TC: OP-TEE version: 6aef7bb2-dirty (gcc version 5.3.1 20160412 (Linaro GCC 5.3-2016.05)) #1 Fri Jul 23 09:25:11 UTC 2021 arm

[whycan]

u-boot 的 board.dts 也需要修改。

[wxgd2017]

@whycan uboot的dts没找到，后来在sunxi-commed.h中修改为串口0就有输出了

[kevin_allwinner]

@wxgd2017 在哪个路径了？