第一次用F133，驱动I80接口失败，求助大佬
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这是第一次弄全志soc和linux，一路跟着tina的文档走，前面调试rgb屏测试ok，不过后面想用i80接口，结果这几天折腾，没折腾明白，网上没找到对应的（有其他的，但没看明白，实力限制……），发个帖求助下大佬们，因为初次搞这个，操作步骤粗鄙不堪入目之处，请多多见谅，后面可以多给小弟批评指正下，多谢！
先说问题
进入系统后，启动日志：
[34]HELLO! BOOT0 is starting! [37]BOOT0 commit : 88480af [40]set pll start [42]periph0 has been enabled [44]set pll end [46][pmu]: bus read error [48]board init ok [50]ZQ value = 0x30 [52]get_pmu_exist() = -1 [54]DRAM BOOT DRIVE INFO: V0.33 [57]DRAM CLK = 528 MHz [59]DRAM Type = 2 (2:DDR2,3:DDR3) [62]DRAMC read ODT off. [65]DRAM ODT off. [67]ddr_efuse_type: 0xa [69]DRAM SIZE =64 M [71]dram_tpr4:0x0 [73]PLL_DDR_CTRL_REG:0xf8002b00 [76]DRAM_CLK_REG:0xc0000000 [78][TIMING DEBUG] MR2= 0x0 [83]DRAM simple test OK. [85]dram size =64 [87]spinor id is: ef 40 19, read cmd: 0b [90]Succeed in reading toc file head. [94]The size of toc is 10c000. [273]Entry_name = opensbi [276]Entry_name = u-boot [280]Entry_name = dtb [282]Jump to second Boot. OpenSBI auto-t113-linux-V0.8-1-g771d82e ____ _____ ____ _____ / __ \ / ____| _ \_ _| | | | |_ __ ___ _ __ | (___ | |_) || | | | | | '_ \ / _ \ '_ \ \___ \| _ < | | | |__| | |_) | __/ | | |____) | |_) || |_ \____/| .__/ \___|_| |_|_____/|____/_____| | | |_| Platform Name : T-HEAD Xuantie Platform Platform HART Features : RV64ACDFIMSUVX Platform Max HARTs : 1 Current Hart : 0 Firmware Base : 0x41fc0400 Firmware Size : 75 KB Runtime SBI Version : 0.2 MIDELEG : 0x0000000000000222 MEDELEG : 0x000000000000b1ff PMP0 : 0x0000000041fc0000-0x0000000041fdffff (A) PMP1 : 0x0000000040000000-0x000000007fffffff (A,R,W,X) PMP2 : 0x0000000080000000-0x00000000bfffffff (A,R,W,X) PMP3 : 0x0000000000020000-0x0000000000027fff (A,▒ U-Boot 2018.05-g2a1965a (Jul 10 2022 - 02:50:57 +0000) Allwinner Technology [00.367]DRAM: 64 MiB [00.369]Relocation Offset is: 01ed9000 [00.374]secure enable bit: 0 [00.377]CPU=1008 MHz,PLL6=600 Mhz,AHB=200 Mhz, APB1=100Mhz MBus=300Mhz [00.383]flash init start [00.385]workmode = 0,storage type = 3 [00.392]spi sunxi_slave->max_hz:100000000 SF: write offset not multiple of erase size [01.109]spi sample_mode:1 sample_delay:1d [01.114]spi sunxi_slave->max_hz:100000000 SF: Detected w25q256 with page size 256 Bytes, erase size 64 KiB, total 32 MiB [01.126]sunxi flash init ok [01.128]line:703 init_clocks [01.131]drv_disp_init request pwm success, pwm7:pwm7:0x2000c00. fdt get node offset faill: hdmi [01.149]unable to map hdmi registers [01.152]drv_disp_init finish [01.156]Loading Environment from SUNXI_FLASH... OK [01.170]boot_gui_init:start [01.173]set disp.dev2_output_type fail. using defval=0 [01.180]boot_gui_init:finish partno erro : can't find partition bootloader ** Unrecognized filesystem type ** [01.190]sunxi bmp info error : unable to open logo file bootlogo.bmp [01.196]out of usb burn from boot: not need burn key [01.201]get secure storage map err partno erro : can't find partition private root_partition is rootfs set root to /dev/mtdblock5 [01.212]update part info [01.215]update bootcmd [01.217]change working_fdt 0x42a98da0 to 0x42a78da0 disable nand error: FDT_ERR_NOTFOUND No reserved memory region found in source FDT [01.247]update dts noncached_alloc(): addr = 0x42ae8480 noncached_alloc(): addr = 0x42ae84c0 noncached_alloc(): addr = 0x42ae8500 noncached_alloc(): addr = 0x42ac27c0 geth_sys_init:639: get node 'gmac0' error geth_sys_init fail! [01.267]Board Net Initialization Failed [01.271]No ethernet found. Hit any key to stop autoboot: 1 FDT ERROR:get muxsel err returned FDT_ERR_INTERNAL sunxi_pwm_pin_set_state, fdt_set_all_pin, ret=-1 [01.370]LCD open finish 0 [02.417]no vendor_boot partition is found Android's image name: f133-mq_r Detect comp none [02.433] Starting kernel ... [ 0.000000] Linux version 5.4.61 (test@test-virtual-machine) (riscv64-unknown-linux-gnu-gcc (C-SKY RISCV Tools V1.8.4 B20200702) 8.1.0, GNU ld (GNU Binutils) 2.32) #102 PREEMPT Wed Jul 17 03:01:59 UTC 2024 [ 0.000000] Zone ranges: [ 0.000000] DMA32 [mem 0x0000000040000000-0x0000000043ffffff] [ 0.000000] Normal empty [ 0.000000] Movable zone start for each node [ 0.000000] Early memory node ranges [ 0.000000] node 0: [mem 0x0000000040000000-0x0000000043ffffff] [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x0000000043ffffff] [ 0.000000] On node 0 totalpages: 16384 [ 0.000000] DMA32 zone: 224 pages used for memmap [ 0.000000] DMA32 zone: 0 pages reserved [ 0.000000] DMA32 zone: 16384 pages, LIFO batch:3 [ 0.000000] elf_hwcap is 0x20112d [ 0.000000] pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768 [ 0.000000] pcpu-alloc: [0] 0 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 16160 [ 0.000000] Kernel command line: ubi.mtd=sys ubi.block=0,rootfs earlyprintk=sunxi-uart,0x02500000 clk_ignore_unused initcall_debug=0 console=ttyS0,115200 loglevel=8 root=/dev/mtdblock5 rootfstype=squashfs init=/pseudo_init partitions=boot-resource@mtdblock1:env@mtdblock2:env-redund@mtdblock3:boot@mtdblock4:rootfs@mtdblock5:UDISK@mtdblock6 cma=0M snum= mac_addr= wifi_mac= bt_mac= specialstr= gpt=1 androidboot.hardware=sun20iw1p1 boot_type=3 androidboot.boot_type=3 gpt=1 uboot_message=2018.05-g2a1965a(07/10/2022-02:50:57) mbr_offset=1556480 [ 0.000000] Dentry cache hash table entries: 8192 (order: 4, 65536 bytes, linear) [ 0.000000] Inode-cache hash table entries: 4096 (order: 3, 32768 bytes, linear) [ 0.000000] Sorting __ex_table... [ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off [ 0.000000] Memory: 56072K/65536K available (3963K kernel code, 419K rwdata, 1676K rodata, 136K init, 222K bss, 9464K reserved, 0K cma-reserved) [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 [ 0.000000] rcu: Preemptible hierarchical RCU implementation. [ 0.000000] Tasks RCU enabled. [ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies. [ 0.000000] NR_IRQS: 0, nr_irqs: 0, preallocated irqs: 0 [ 0.000000] plic: mapped 200 interrupts with 1 handlers for 2 contexts. [ 0.000000] riscv_timer_init_dt: Registering clocksource cpuid [0] hartid [0] [ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x588fe9dc0, max_idle_ns: 440795202592 ns [ 0.000006] sched_clock: 64 bits at 24MHz, resolution 41ns, wraps every 4398046511097ns [ 0.000027] riscv_timer_clockevent depends on broadcast, but no broadcast function available [ 0.000363] clocksource: timer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns [ 0.000925] Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=240000) [ 0.000945] pid_max: default: 32768 minimum: 301 [ 0.001116] Mount-cache hash table entries: 512 (order: 0, 4096 bytes, linear) [ 0.001139] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes, linear) [ 0.003003] ASID allocator initialised with 65536 entries [ 0.003180] rcu: Hierarchical SRCU implementation. [ 0.003869] devtmpfs: initialized [ 0.022074] random: get_random_u32 called from bucket_table_alloc.isra.27+0xfa/0x11c with crng_init=0 [ 0.022946] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns [ 0.022978] futex hash table entries: 256 (order: 0, 6144 bytes, linear) [ 0.023140] pinctrl core: initialized pinctrl subsystem [ 0.024565] NET: Registered protocol family 16 [ 0.025315] DMA: preallocated 256 KiB pool for atomic allocations [ 0.025902] cpuidle: using governor menu [ 0.064749] rtc_ccu: sunxi ccu init OK [ 0.073056] clock: sunxi ccu init OK [ 0.074810] clock: sunxi ccu init OK [ 0.103572] iommu: Default domain type: Translated [ 0.103766] sunxi iommu: irq = 4 [ 0.104930] SCSI subsystem initialized [ 0.105150] usbcore: registered new interface driver usbfs [ 0.105234] usbcore: registered new interface driver hub [ 0.105340] usbcore: registered new device driver usb [ 0.106322] Advanced Linux Sound Architecture Driver Initialized. [ 0.107207] pwm module init! [ 0.108815] g2d 5410000.g2d: Adding to iommu group 0 [ 0.109329] G2D: rcq version initialized.major:252 [ 0.109940] clocksource: Switched to clocksource riscv_clocksource [ 0.121725] sun8iw20-pinctrl 2000000.pinctrl: initialized sunXi PIO driver [ 0.124830] sunxi_usb_udc 4100000.udc-controller: 4100000.udc-controller supply udc not found, using dummy regulator [ 0.125661] NET: Registered protocol family 2 [ 0.126536] tcp_listen_portaddr_hash hash table entries: 256 (order: 0, 4096 bytes, linear) [ 0.126591] TCP established hash table entries: 512 (order: 0, 4096 bytes, linear) [ 0.126609] TCP bind hash table entries: 512 (order: 0, 4096 bytes, linear) [ 0.126624] TCP: Hash tables configured (established 512 bind 512) [ 0.126791] UDP hash table entries: 256 (order: 1, 8192 bytes, linear) [ 0.126837] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear) [ 0.127072] NET: Registered protocol family 1 [ 0.128254] sun8iw20-pinctrl 2000000.pinctrl: 2000000.pinctrl supply vcc-pc not found, using dummy regulator [ 0.128875] spi spi0: spi0 supply spi not found, using dummy regulator [ 0.129124] sunxi_spi_resource_get()2116 - [spi0] SPI MASTER MODE [ 0.129193] sunxi_spi_resource_get()2163 - sample_mode:1 sample_delay:29 [ 0.129250] sunxi_spi_clk_init()2205 - [spi0] mclk 100000000 [ 0.130225] sunxi_spi_probe()2623 - [spi0]: driver probe succeed, base ffffffd00405a000, irq 31 [ 0.132323] workingset: timestamp_bits=62 max_order=14 bucket_order=0 [ 0.137849] squashfs: version 4.0 (2009/01/31) Phillip Lougher [ 0.138093] ntfs: driver 2.1.32 [Flags: R/W]. [ 0.138379] jffs2: version 2.2. (NAND) (SUMMARY) © 2001-2006 Red Hat, Inc. [ 0.138752] fuse: init (API version 7.31) [ 0.159206] io scheduler mq-deadline registered [ 0.159222] io scheduler kyber registered // disp初始化 [ 0.160168] [DISP]disp_module_init [ 0.160764] disp 5000000.disp: Adding to iommu group 0 [ 0.161372] [DISP] disp_init,line:2386: [ 0.161379] smooth display screen:0 type:1 mode:4 // lcd初始化 [ 0.161519] lcd_init [ 0.162442] display_fb_request,fb_id:0 [ 0.164044] [DISP] Fb_copy_boot_fb,line:1505: [ 0.164052] src_height(480) > dst_height(240),please cut the height [ 0.164566] disp_al_manager_apply ouput_type:1 [ 0.164686] lcd_clk_config [ 0.164714] [DISP] lcd_clk_config,line:895: [ 0.164724] disp 0, clk: pll(0),clk(0),dclk(0) dsi_rate(0) [ 0.164724] clk real:pll(297000000),clk(288000000),dclk(0) dsi_rate(0) [ 0.165384] [DISP]disp_module_init finish // 初始化完成 [ 0.166269] sunxi_sid_init()551 - insmod ok [ 0.166844] pwm-regulator: supplied by regulator-dummy [ 0.168566] sun8iw20-pinctrl 2000000.pinctrl: 2000000.pinctrl supply vcc-pe not found, using dummy regulator [ 0.169052] uart uart0: uart0 supply uart not found, using dummy regulator [ 0.169458] uart0: ttyS0 at MMIO 0x2500000 (irq = 18, base_baud = 1500000) is a SUNXI [ 0.169485] sw_console_setup()1808 - console setup baud 115200 parity n bits 8, flow n [ 0.901824] printk: console [ttyS0] enabled [ 0.907650] misc dump reg init [ 0.912094] sun8iw20-pinctrl 2000000.pinctrl: 2000000.pinctrl supply vcc-pg not found, using dummy regulator [ 0.923384] sunxi-rfkill soc@3000000:rfkill@0: module version: v1.0.9 [ 0.930643] sunxi-rfkill soc@3000000:rfkill@0: get gpio chip_en failed [ 0.937997] sunxi-rfkill soc@3000000:rfkill@0: get gpio power_en failed [ 0.945427] sunxi-rfkill soc@3000000:rfkill@0: wlan_busnum (1) [ 0.951966] sunxi-rfkill soc@3000000:rfkill@0: Missing wlan_power. [ 0.958911] sunxi-rfkill soc@3000000:rfkill@0: wlan clock[0] (32k-fanout1) [ 0.966651] sunxi-rfkill soc@3000000:rfkill@0: wlan_regon gpio=204 assert=1 [ 0.974595] sunxi-rfkill soc@3000000:rfkill@0: wlan_hostwake gpio=202 assert=1 [ 0.982747] sunxi-rfkill soc@3000000:rfkill@0: wakeup source is enabled [ 0.990495] sunxi-rfkill soc@3000000:rfkill@0: Missing bt_power. [ 0.997223] sunxi-rfkill soc@3000000:rfkill@0: bt clock[0] (32k-fanout1) [ 1.004867] sunxi-rfkill soc@3000000:rfkill@0: bt_rst gpio=210 assert=0 [ 1.013067] [ADDR_MGT] addr_mgt_probe: module version: v1.0.11 [ 1.020810] [ADDR_MGT] addr_mgt_probe: success. [ 1.027372] spi-nor spi0.0: w25q256 (32768 Kbytes) [ 1.037933] 7 sunxipart partitions found on MTD device spi0.0 [ 1.044469] Creating 7 MTD partitions on "spi0.0": [ 1.049818] 0x000000000000-0x000000180000 : "uboot" [ 1.060809] 0x000000180000-0x000000190000 : "boot-resource" [ 1.080774] 0x000000190000-0x0000001d0000 : "env" [ 1.090766] 0x0000001d0000-0x000000210000 : "env-redund" [ 1.110713] 0x000000210000-0x000000990000 : "boot" [ 1.120792] 0x000000990000-0x000001110000 : "rootfs" [ 1.140711] 0x000001110000-0x000002000000 : "UDISK" [ 1.151730] sunxi-rtc 7090000.rtc: Warning: Using internal RC 16M clock source. Time may be inaccurate! [ 1.162746] sunxi-rtc 7090000.rtc: Warning: Using internal RC 16M clock source. Time may be inaccurate! [ 1.173538] sunxi-rtc 7090000.rtc: Warning: Using internal RC 16M clock source. Time may be inaccurate! [ 1.184770] sunxi-rtc 7090000.rtc: registered as rtc0 [ 1.190542] sunxi-rtc 7090000.rtc: Warning: Using internal RC 16M clock source. Time may be inaccurate! [ 1.201147] sunxi-rtc 7090000.rtc: setting system clock to 1970-01-01T01:48:07 UTC (6487) [ 1.210372] sunxi-rtc 7090000.rtc: sunxi rtc probed [ 1.216333] sunxi cedar version 1.1 [ 1.220563] sunxi-cedar 1c0e000.ve: Adding to iommu group 0 [ 1.226850] VE: install start!!! [ 1.226850] [ 1.232424] VE: cedar-ve the get irq is 6 [ 1.232424] [ 1.238767] VE: ve_debug_proc_info:(____ptrval____), data:(____ptrval____), lock:(____ptrval____) [ 1.238767] [ 1.250410] VE: install end!!! [ 1.250410] [ 1.255457] VE: sunxi_cedar_probe [ 1.260173] sunxi-wdt 6011000.watchdog: Watchdog enabled (timeout=16 sec, nowayout=0) [ 1.270510] sunxi-mmc 4021000.sdmmc: SD/MMC/SDIO Host Controller Driver(v4.22 2021-12-20 15:40) [ 1.280594] sunxi-mmc 4021000.sdmmc: ***ctl-spec-caps*** 8 [ 1.286778] sunxi-mmc 4021000.sdmmc: No vmmc regulator found [ 1.293187] sunxi-mmc 4021000.sdmmc: No vqmmc regulator found [ 1.299594] sunxi-mmc 4021000.sdmmc: No vdmmc regulator found [ 1.306032] sunxi-mmc 4021000.sdmmc: No vd33sw regulator found [ 1.312599] sunxi-mmc 4021000.sdmmc: No vd18sw regulator found [ 1.319103] sunxi-mmc 4021000.sdmmc: No vq33sw regulator found [ 1.325677] sunxi-mmc 4021000.sdmmc: No vq18sw regulator found [ 1.332240] sunxi-mmc 4021000.sdmmc: Cann't get pin bias hs pinstate,check if needed [ 1.341805] sunxi-mmc 4021000.sdmmc: sdc set ios:clk 0Hz bm PP pm UP vdd 21 width 1 timing LEGACY(SDR12) dt B [ 1.352957] sunxi-mmc 4021000.sdmmc: no vqmmc,Check if there is regulator [ 1.373154] sunxi-mmc 4021000.sdmmc: sdc set ios:clk 400000Hz bm PP pm ON vdd 21 width 1 timing LEGACY(SDR12) dt B [ 1.397401] sunxi-mmc 4021000.sdmmc: detmode:manually by software [ 1.405082] sunxi-mmc 4021000.sdmmc: smc 0 p1 err, cmd 52, RTO !! [ 1.412215] ashmem: initialized [ 1.415741] sunxi-mmc 4021000.sdmmc: smc 0 p1 err, cmd 52, RTO !! [ 1.422620] sunxi-mmc 4021000.sdmmc: sdc set ios:clk 400000Hz bm PP pm ON vdd 21 width 1 timing LEGACY(SDR12) dt B [ 1.434591] exFAT: Version 1.3.0 [ 1.443037] sunxi-mmc 4021000.sdmmc: sdc set ios:clk 400000Hz bm PP pm ON vdd 21 width 1 timing LEGACY(SDR12) dt B [ 1.454731] [AUDIOCODEC][sunxi_codec_parse_params][2412]:digital_vol:0, lineout_vol:26, mic1gain:31, mic2gain:31 pa_msleep:120, pa_level:1, pa_pwr_level:1 [ 1.454731] [ 1.472032] [AUDIOCODEC][sunxi_codec_parse_params][2448]:adcdrc_cfg:0, adchpf_cfg:1, dacdrc_cfg:0, dachpf:0 [ 1.483505] [AUDIOCODEC][sunxi_internal_codec_probe][2609]:codec probe finished [ 1.491683] sunxi-mmc 4021000.sdmmc: smc 0 p1 err, cmd 5, RTO !! [ 1.499335] sunxi-mmc 4021000.sdmmc: smc 0 p1 err, cmd 5, RTO !! [ 1.506756] debugfs: Directory '203034c.dummy_cpudai' with parent 'audiocodec' already present! [ 1.516485] sunxi-mmc 4021000.sdmmc: smc 0 p1 err, cmd 5, RTO !! [ 1.523390] [SNDCODEC][sunxi_card_init][583]:card init finished [ 1.530012] sunxi-mmc 4021000.sdmmc: smc 0 p1 err, cmd 5, RTO !! [ 1.536801] sunxi-mmc 4021000.sdmmc: sdc set ios:clk 0Hz bm PP pm OFF vdd 0 width 1 timing LEGACY(SDR12) dt B [ 1.550507] sunxi-codec-machine 2030340.sound: 2030000.codec <-> 203034c.dummy_cpudai mapping ok [ 1.561940] input: audiocodec sunxi Audio Jack as /devices/platform/soc@3000000/2030340.sound/sound/card0/input0 [ 1.574246] [SNDCODEC][sunxi_card_dev_probe][836]:register card finished [ 1.583699] NET: Registered protocol family 10 [ 1.590012] [SNDCODEC][sunxi_hs_init_work][259]:resume-->report switch [ 1.597568] Segment Routing with IPv6 [ 1.601987] NET: Registered protocol family 17 [ 1.608786] HDMI 2.0 driver init start! [ 1.613210] boot_hdmi=false [ 1.616379] ERROR: can not get hdmi_cts_compatibility [ 1.622072] ERROR: pinctrl_get for HDMI2.0 DDC fail [ 1.627539] ERROR: can not get ddc_en_io_ctrl [ 1.632453] ERROR: can not get hdmi_power_cnt [ 1.638751] HDMI2.0 module init end [ 1.669910] UBI error: cannot open mtd sys, error -2 [ 1.675558] UBI: block: can't open volume on ubi0_-1, err=-19 [ 1.683395] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2 [ 1.693150] clk: Not disabling unused clocks [ 1.697919] ALSA device list: [ 1.701304] cfg80211: failed to load regulatory.db [ 1.706688] #0: audiocodec [ 1.710043] alloc_fd: slot 0 not NULL! [ 1.718663] VFS: Mounted root (squashfs filesystem) readonly on device 31:5. [ 1.731227] devtmpfs: mounted [ 1.734722] Freeing unused kernel memory: 136K [ 1.739673] This architecture does not have kernel memory protection. [ 1.746982] Run /pseudo_init as init process [ 1.764008] random: fast init done mount: mounting none on /dev failed: Device or resource busy [ 3.071008] MTD: Couldn't look up '/dev/by-name/rootfs_data': -2 mount: mounting /dev/by-name/rootfs_data on /overlay failed: No such file or directory Mount Failed: formating /dev/by-name/rootfs_data to jffs2 ... mkfs.jffs2: error!: Unrecognisable erase size ------run rc.preboot file----- [ 3.610097] jffs2: notice: (99) jffs2_build_xattr_subsystem: complete building xattr subsystem, 0 of xdatum (0 unchecked, 0 orphan) and 0 of xref (0 dead, 0 orphan) found. ------run rc.modules file----- [ 3.707454] random: crng init done [ 5.239976] hdmi_hpd_sys_config_release [ 20.156128] sunxi-rfkill soc@3000000:rfkill@0: wlan power on success [ 20.267209] sunxi-rfkill soc@3000000:rfkill@0: bus_index: 1 [ 20.273730] sunxi-mmc 4021000.sdmmc: sdc set ios:clk 0Hz bm PP pm UP vdd 21 width 1 timing LEGACY(SDR12) dt B [ 20.294444] sunxi-mmc 4021000.sdmmc: no vqmmc,Check if there is regulator [ 20.314953] sunxi-mmc 4021000.sdmmc: sdc set ios:clk 400000Hz bm PP pm ON vdd 21 width 1 timing LEGACY(SDR12) dt B [ 20.340686] sunxi-mmc 4021000.sdmmc: sdc set ios:clk 400000Hz bm PP pm ON vdd 21 width 1 timing LEGACY(SDR12) dt B [ 20.356451] sunxi-mmc 4021000.sdmmc: sdc set ios:clk 400000Hz bm PP pm ON vdd 21 width 1 timing LEGACY(SDR12) dt B [ 20.370895] sunxi-mmc 4021000.sdmmc: card claims to support voltages below defined range [ 20.390608] sunxi-mmc 4021000.sdmmc: sdc set ios:clk 400000Hz bm PP pm ON vdd 21 width 1 timing SD-HS(SDR25) dt B [ 20.403338] sunxi-mmc 4021000.sdmmc: sdc set ios:clk 50000000Hz bm PP pm ON vdd 21 width 1 timing SD-HS(SDR25) dt B [ 20.416776] sunxi-mmc 4021000.sdmmc: sdc set ios:clk 50000000Hz bm PP pm ON vdd 21 width 4 timing SD-HS(SDR25) dt B [ 20.431008] mmc0: new high speed SDIO card at address 0001 [ 31.849997] pio-18: disabling [ 31.853340] pio-33: disabling [ 31.856647] usb1-vbus: disabling Successfully initialized wpa_supplicant ------run rc.final file----- BusyBox v1.27.2 () built-in shell (ash) ------run profile file----- _____ _ __ _ |_ _||_| ___ _ _ | | |_| ___ _ _ _ _ | | _ | || | | |__ | || || | ||_'_| | | | || | || _ | |_____||_||_|_||___||_,_| |_| |_||_|_||_|_| Tina is Based on OpenWrt! ---------------------------------------------- Tina Linux (Neptune, 5C1C9C53) ---------------------------------------------- nodev debugfs root@TinaLinux:/# [ 34.165790] file system registered [ 34.207543] configfs-gadget 4100000.udc-controller: failed to start g1: -19 sh: write error: No such device [ 34.268250] read descriptors [ 34.272099] read strings [ 34.437927] sunxi_set_cur_vol_work()485 WARN: get power supply failed [ 34.509331] configfs-gadget gadget: high-speed config #1: c root@TinaLinux:/#lcd初始化部分，设备树设置的320*240，不知道这里fb的800哪里来的
然后查看disp的sys信息
root@TinaLinux:/# cat /sys/class/disp/disp/attr/sys screen 0: de_rate 300000000 hz, ref_fps:-1 mgr0: 0x0 fmt[rgb] cs[0x204] range[full] eotf[0x4] bits[8bits] err[1] force_sync[0] unblank direct_show[false] iommu[1] dmabuf: cache[0] cache max[0] umap skip[0] umap skip max[32] lcd output backlight( 0) fps:60.2 0x 0 err:12387 skip:86 irq:12389 vsync:0 vsync_skip:0 BUF enable ch[1] lyr[0] z[16] prem[N] a[pixel 255] fmt[ 0] fb[ 320, 240; 320, 240; 320, 240] crop[ 0, 0, 320, 240] frame[ 0, 0, 800, 480] addr[fff80000, 0, 0] flags[0x 0] trd[0,0] depth[ 0] root@TinaLinux:/# root@TinaLinux:/#可以看到mgr0是0x0，后面frame又是800x480，有问题，但不知出在哪儿……前面rgb屏frame也是这样，不过我用测试代码修改了fb_var_screeninfo才行
切换到dispdbg，用suspend命令root@TinaLinux:/# cd /sys/kernel/debug/dispdbg/ root@TinaLinux:/sys/kernel/debug/dispdbg# echo disp0 > name root@TinaLinux:/sys/kernel/debug/dispdbg# echo suspend >command root@TinaLinux:/sys/kernel/debug/dispdbg# echo 1 >start [ 1170.840215] disp_suspend [ 1170.843048] [DISP] disp_lcd_disable,line:2369: [ 1170.843053] lcd_panel_fun[0](--).cfg_close_flow is NULL [ 1170.870085] disp_suspend finish root@TinaLinux:/sys/kernel/debug/dispdbg#lcd_panel_fun0.cfg_close_flow is NULL这个搞的有点蒙，在lcdpanel里，这里cfg_close_flow是有的，不知道这里为啥是个NULL，另外lcd_panel_fun0这里括号，是我在源码
lichee/linux-5.4/drivers/video/fbdev/sunxi/disp2/disp/de/disp_lcd.c----->disp_lcd_disable中改的DE_WRN("lcd_panel_fun[%d](%s--%s).cfg_close_flow is NULL\n", lcd->disp,lcdp->panel_info.lcd_model_name,lcdp->panel_info.lcd_driver_name);但似乎，都是空值，所以是不是驱动挂的不是指定的panel呢？
下面是我添加驱动到配置的具体步骤，新手操作，粗鄙难入眼之处，请多担待……
再说步骤
根据手头的Tina的开发文档，及自己的理解，我分为以下几个步骤：
- 在lichee/brandy-2.0/u-boot-2018/drivers/video/sunxi/disp2/disp/lcd/路径添加ili9341_80.c和ili9341_80.h
如下，c文件
/* * drivers/video/fbdev/sunxi/disp2/disp/lcd/ili9341/ili9341.c * * Copyright (c) 2007-2018 Allwinnertech Co., Ltd. * Author: zhengxiaobin <zhengxiaobin@allwinnertech.com> * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. [lcd0] lcd_used = 1 lcd_driver_name = "ili9341" lcd_x = 240 lcd_y = 320 lcd_width = 108 lcd_height = 64 lcd_dclk_freq = 60 lcd_pwm_used = 0 lcd_pwm_ch = 0 lcd_pwm_freq = 50000 lcd_pwm_pol = 1 lcd_pwm_max_limit = 255 lcd_hbp = 20 ;10 + 20 + 10 + 240*3 = 760 real set 1000 lcd_ht = 1000 lcd_hspw = 10 lcd_vbp = 5 lcd_vt = 340 lcd_vspw = 2 lcd_frm = 0 lcd_if = 0 lcd_hv_if = 8 lcd_hv_clk_phase = 0 lcd_hv_sync_polarity = 0 lcd_hv_srgb_seq = 0 lcd_io_phase = 0x0000 lcd_gamma_en = 0 lcd_bright_curve_en = 1 lcd_cmap_en = 0 lcd_rb_swap = 0 deu_mode = 0 lcdgamma4iep = 22 smart_color = 90 ;reset lcd_gpio_0 = port:PD16<1><0><default><1> lcdd2 = port:PD00<2><0><2><default> lcdd3 = port:PD01<2><0><2><default> lcdd4 = port:PD02<2><0><2><default> lcdd5 = port:PD03<2><0><2><default> lcdd6 = port:PD04<2><0><2><default> lcdd7 = port:PD05<2><0><2><default> lcdd10 = port:PD06<2><0><2><default> lcdd11 = port:PD07<2><0><2><default> lcdd12 = port:PD08<2><0><2><default> lcdd13 = port:PD09<2><0><2><default> lcdd14 = port:PD10<2><0><2><default> lcdd15 = port:PD11<2><0><2><default> lcdd18 = port:PD12<2><0><2><default> lcdd19 = port:PD13<2><0><2><default> lcdd20 = port:PD14<2><0><2><default> lcdd21 = port:PD15<2><0><2><default> lcdclk = port:PD18<7><0><3><default> lcdde = port:PD19<7><0><3><default> lcdhsync = port:PD20<7><0><3><default> lcdvsync = port:PD21<7><0><3><default> * */ #include "ili9341_80.h" #define CPU_TRI_MODE #define ili9341c_spi_reset_1 sunxi_lcd_gpio_set_value(0, 0, 1) #define ili9341c_spi_reset_0 sunxi_lcd_gpio_set_value(0, 0, 0) static void lcd_panel_ili9341_init(struct disp_panel_para *info); static void LCD_power_on(u32 sel); static void LCD_power_off(u32 sel); static void LCD_bl_open(u32 sel); static void LCD_bl_close(u32 sel); static void LCD_panel_init(u32 sel); static void LCD_panel_exit(u32 sel); extern s32 tcon0_cpu_set_tri_mode(u32 sel); void write_tcon_register(int offset, int value) { volatile int *tcon_reg = (int *)(0xf1c0c000 + offset); int reg = 0; reg = *((volatile int *)tcon_reg); reg |= value; *((volatile int *)tcon_reg) = reg; } static void lcd_cfg_panel_info(struct panel_extend_para *info) { u32 i = 0, j = 0; u32 items; u8 lcd_gamma_tbl[][2] = { //{input value, corrected value} {0, 0}, {15, 15}, {30, 30}, {45, 45}, {60, 60}, {75, 75}, {90, 90}, {105, 105}, {120, 120}, {135, 135}, {150, 150}, {165, 165}, {180, 180}, {195, 195}, {210, 210}, {225, 225}, {240, 240}, {255, 255}, }; u32 lcd_cmap_tbl[2][3][4] = { { {LCD_CMAP_G0, LCD_CMAP_B1, LCD_CMAP_G2, LCD_CMAP_B3}, {LCD_CMAP_B0, LCD_CMAP_R1, LCD_CMAP_B2, LCD_CMAP_R3}, {LCD_CMAP_R0, LCD_CMAP_G1, LCD_CMAP_R2, LCD_CMAP_G3}, }, { {LCD_CMAP_B3, LCD_CMAP_G2, LCD_CMAP_B1, LCD_CMAP_G0}, {LCD_CMAP_R3, LCD_CMAP_B2, LCD_CMAP_R1, LCD_CMAP_B0}, {LCD_CMAP_G3, LCD_CMAP_R2, LCD_CMAP_G1, LCD_CMAP_R0}, }, }; items = sizeof(lcd_gamma_tbl) / 2; for (i = 0; i < items - 1; i++) { u32 num = lcd_gamma_tbl[i + 1][0] - lcd_gamma_tbl[i][0]; for (j = 0; j < num; j++) { u32 value = 0; value = lcd_gamma_tbl[i][1] + ((lcd_gamma_tbl[i + 1][1] - lcd_gamma_tbl[i][1]) * j) / num; info->lcd_gamma_tbl[lcd_gamma_tbl[i][0] + j] = (value << 16) + (value << 8) + value; } } info->lcd_gamma_tbl[255] = (lcd_gamma_tbl[items - 1][1] << 16) + (lcd_gamma_tbl[items - 1][1] << 8) + lcd_gamma_tbl[items - 1][1]; memcpy(info->lcd_cmap_tbl, lcd_cmap_tbl, sizeof(lcd_cmap_tbl)); } static s32 lcd_open_flow(u32 sel) { LCD_OPEN_FUNC(sel, LCD_power_on, 40); #ifdef CPU_TRI_MODE LCD_OPEN_FUNC(sel, LCD_panel_init, 50); LCD_OPEN_FUNC(sel, sunxi_lcd_tcon_enable, 50); #else LCD_OPEN_FUNC(sel, sunxi_lcd_tcon_enable, 50); LCD_OPEN_FUNC(sel, LCD_panel_init, 50); #endif LCD_OPEN_FUNC(sel, LCD_bl_open, 0); return 0; } static s32 lcd_close_flow(u32 sel) { LCD_CLOSE_FUNC(sel, LCD_bl_close, 50); #ifdef CPU_TRI_MODE LCD_CLOSE_FUNC(sel, sunxi_lcd_tcon_disable, 10); LCD_CLOSE_FUNC(sel, LCD_panel_exit, 10); #else LCD_CLOSE_FUNC(sel, LCD_panel_exit, 10); LCD_CLOSE_FUNC(sel, sunxi_lcd_tcon_disable, 10); #endif LCD_CLOSE_FUNC(sel, LCD_power_off, 10); return 0; } static void LCD_power_on(u32 sel) { sunxi_lcd_power_enable(sel, 0); sunxi_lcd_pin_cfg(sel, 1); } static void LCD_power_off(u32 sel) { sunxi_lcd_pin_cfg(sel, 0); sunxi_lcd_power_disable(sel, 0); } static void LCD_bl_open(u32 sel) { sunxi_lcd_pwm_enable(sel); /*config lcd_bl_en pin to open lcd backlight*/ sunxi_lcd_backlight_enable(sel); } static void LCD_bl_close(u32 sel) { /*config lcd_bl_en pin to close lcd backlight*/ sunxi_lcd_backlight_disable(sel); sunxi_lcd_pwm_disable(sel); } static void LCD_WRITE_DATA(u32 value) { sunxi_lcd_cpu_write_data(0,value&0xFFFF); } static void LCD_WRITE_COMMAND(u32 value) { sunxi_lcd_cpu_write_index(0,value&0xFFFF); } static void LCD_panel_init(u32 sel) { struct disp_panel_para *info = kmalloc(sizeof(struct disp_panel_para), GFP_KERNEL | __GFP_ZERO); bsp_disp_get_panel_info(sel, info); lcd_panel_ili9341_init(info); kfree(info); return; } static void LCD_panel_exit(u32 sel) { struct disp_panel_para *info = kmalloc(sizeof(struct disp_panel_para), GFP_KERNEL | __GFP_ZERO); LCD_WRITE_COMMAND(0x28); LCD_WRITE_COMMAND(0x10); sunxi_lcd_delay_ms(300); bsp_disp_get_panel_info(sel, info); kfree(info); return; } static void lcd_panel_ili9341_init(struct disp_panel_para *info) { //************* Start Initial Sequence **********// //************* Reset LCD Driver ****************// ili9341c_spi_reset_1; sunxi_lcd_delay_ms(1); ili9341c_spi_reset_0; /*Delay 10ms This delay time is necessary*/ sunxi_lcd_delay_ms(10); ili9341c_spi_reset_1; /*Delay 120 ms*/ sunxi_lcd_delay_ms(120); /************** Start Initial Sequence ***********/ /*Pixel Format Set*/ LCD_WRITE_COMMAND(0x3A); LCD_WRITE_DATA(0x55); LCD_WRITE_COMMAND(0xF6); LCD_WRITE_DATA(0x01); LCD_WRITE_DATA(0x33); LCD_WRITE_COMMAND(0xB5); LCD_WRITE_DATA(0x04); LCD_WRITE_DATA(0x04); LCD_WRITE_DATA(0x0A); LCD_WRITE_DATA(0x14); LCD_WRITE_COMMAND(0x35); LCD_WRITE_DATA(0x00); LCD_WRITE_COMMAND(0xCF); LCD_WRITE_DATA(0x00); LCD_WRITE_DATA(0xEA); LCD_WRITE_DATA(0xF0); LCD_WRITE_COMMAND(0xED); LCD_WRITE_DATA(0x64); LCD_WRITE_DATA(0x03); LCD_WRITE_DATA(0x12); LCD_WRITE_DATA(0x81); LCD_WRITE_COMMAND(0xE8); LCD_WRITE_DATA(0x85); LCD_WRITE_DATA(0x00); LCD_WRITE_DATA(0x78); LCD_WRITE_COMMAND(0xCB); LCD_WRITE_DATA(0x39); LCD_WRITE_DATA(0x2C); LCD_WRITE_DATA(0x00); LCD_WRITE_DATA(0x33); LCD_WRITE_DATA(0x06); LCD_WRITE_COMMAND(0xF7); LCD_WRITE_DATA(0x20); LCD_WRITE_COMMAND(0xEA); LCD_WRITE_DATA(0x00); LCD_WRITE_DATA(0x00); /*VRH[5:0]*/ LCD_WRITE_COMMAND(0xC0); LCD_WRITE_DATA(0x21); LCD_WRITE_COMMAND(0xC1); LCD_WRITE_DATA(0x10); LCD_WRITE_COMMAND(0xC5); LCD_WRITE_DATA(0x31); LCD_WRITE_DATA(0x3C); LCD_WRITE_COMMAND(0x36); LCD_WRITE_DATA(0x08); LCD_WRITE_COMMAND(0xB0); /*E0,E9D340*/ LCD_WRITE_DATA(0xE9); LCD_WRITE_COMMAND(0xB1); LCD_WRITE_DATA(0x00); LCD_WRITE_DATA(0x13); LCD_WRITE_COMMAND(0xB6); LCD_WRITE_DATA(0x0A); LCD_WRITE_DATA(0xA2); LCD_WRITE_COMMAND(0xF2); LCD_WRITE_DATA(0x02); LCD_WRITE_COMMAND(0xF6); LCD_WRITE_DATA(0x01); LCD_WRITE_DATA(0x30); LCD_WRITE_DATA(0x07); LCD_WRITE_COMMAND(0x26); LCD_WRITE_DATA(0x01); LCD_WRITE_COMMAND(0xE0); LCD_WRITE_DATA(0x0F); LCD_WRITE_DATA(0x30); LCD_WRITE_DATA(0x24); LCD_WRITE_DATA(0x08); LCD_WRITE_DATA(0x07); LCD_WRITE_DATA(0x03); LCD_WRITE_DATA(0x51); LCD_WRITE_DATA(0x50); LCD_WRITE_DATA(0x45); LCD_WRITE_DATA(0x0a); LCD_WRITE_DATA(0x15); LCD_WRITE_DATA(0x04); LCD_WRITE_DATA(0x10); LCD_WRITE_DATA(0x40); LCD_WRITE_DATA(0x00); LCD_WRITE_COMMAND(0xE1); LCD_WRITE_DATA(0x00); LCD_WRITE_DATA(0x15); LCD_WRITE_DATA(0x0a); LCD_WRITE_DATA(0x12); LCD_WRITE_DATA(0x07); LCD_WRITE_DATA(0x13); LCD_WRITE_DATA(0x21); LCD_WRITE_DATA(0x22); LCD_WRITE_DATA(0x38); LCD_WRITE_DATA(0x32); LCD_WRITE_DATA(0x06); LCD_WRITE_DATA(0x03); LCD_WRITE_DATA(0x20); LCD_WRITE_DATA(0x2c); LCD_WRITE_DATA(0x34); LCD_WRITE_COMMAND(0x36); LCD_WRITE_DATA(0x08); LCD_WRITE_COMMAND(0x11); sunxi_lcd_delay_ms(120); LCD_WRITE_COMMAND(0x29); /*Display on*/ LCD_WRITE_COMMAND(0x2C); } void lcd_reflush(void) { /************** Start Initial Sequence ***********/ /************** Reset LCD Driver *****************/ ili9341c_spi_reset_1; sunxi_lcd_delay_ms(1); ili9341c_spi_reset_0; /*Delay 10ms This delay time is necessary*/ sunxi_lcd_delay_ms(10); ili9341c_spi_reset_1; /*Delay 120 ms*/ sunxi_lcd_delay_ms(120); /************** Start Initial Sequence ***********/ /*Pixel Format Set*/ LCD_WRITE_COMMAND(0x3A); LCD_WRITE_DATA(0x55); LCD_WRITE_COMMAND(0xF6); LCD_WRITE_DATA(0x01); LCD_WRITE_DATA(0x33); LCD_WRITE_COMMAND(0xB5); LCD_WRITE_DATA(0x04); LCD_WRITE_DATA(0x04); LCD_WRITE_DATA(0x0A); LCD_WRITE_DATA(0x14); LCD_WRITE_COMMAND(0x35); LCD_WRITE_DATA(0x00); LCD_WRITE_COMMAND(0xCF); LCD_WRITE_DATA(0x00); LCD_WRITE_DATA(0xEA); LCD_WRITE_DATA(0xF0); LCD_WRITE_COMMAND(0xED); LCD_WRITE_DATA(0x64); LCD_WRITE_DATA(0x03); LCD_WRITE_DATA(0x12); LCD_WRITE_DATA(0x81); LCD_WRITE_COMMAND(0xE8); LCD_WRITE_DATA(0x85); LCD_WRITE_DATA(0x00); LCD_WRITE_DATA(0x78); LCD_WRITE_COMMAND(0xCB); LCD_WRITE_DATA(0x39); LCD_WRITE_DATA(0x2C); LCD_WRITE_DATA(0x00); LCD_WRITE_DATA(0x33); LCD_WRITE_DATA(0x06); LCD_WRITE_COMMAND(0xF7); LCD_WRITE_DATA(0x20); LCD_WRITE_COMMAND(0xEA); LCD_WRITE_DATA(0x00); LCD_WRITE_DATA(0x00); /*VRH[5:0]*/ LCD_WRITE_COMMAND(0xC0); LCD_WRITE_DATA(0x21); LCD_WRITE_COMMAND(0xC1); LCD_WRITE_DATA(0x10); LCD_WRITE_COMMAND(0xC5); LCD_WRITE_DATA(0x4F); LCD_WRITE_DATA(0x38); LCD_WRITE_COMMAND(0x36); LCD_WRITE_DATA(0x08); LCD_WRITE_COMMAND(0xB0); LCD_WRITE_DATA(0xE9); LCD_WRITE_COMMAND(0xB1); LCD_WRITE_DATA(0x00); LCD_WRITE_DATA(0x13); LCD_WRITE_COMMAND(0xB6); LCD_WRITE_DATA(0x0A); LCD_WRITE_DATA(0xA2); LCD_WRITE_COMMAND(0xF2); LCD_WRITE_DATA(0x02); LCD_WRITE_COMMAND(0xF6); LCD_WRITE_DATA(0x01); LCD_WRITE_DATA(0x30); LCD_WRITE_DATA(0x07); LCD_WRITE_COMMAND(0x26); LCD_WRITE_DATA(0x01); LCD_WRITE_COMMAND(0xE0); LCD_WRITE_DATA(0x0F); LCD_WRITE_DATA(0x30); LCD_WRITE_DATA(0x24); LCD_WRITE_DATA(0x08); LCD_WRITE_DATA(0x07); LCD_WRITE_DATA(0x03); LCD_WRITE_DATA(0x51); LCD_WRITE_DATA(0x50); LCD_WRITE_DATA(0x45); LCD_WRITE_DATA(0x0a); LCD_WRITE_DATA(0x15); LCD_WRITE_DATA(0x04); LCD_WRITE_DATA(0x10); LCD_WRITE_DATA(0x40); LCD_WRITE_DATA(0x00); LCD_WRITE_COMMAND(0xE1); LCD_WRITE_DATA(0x00); LCD_WRITE_DATA(0x15); LCD_WRITE_DATA(0x0a); LCD_WRITE_DATA(0x12); LCD_WRITE_DATA(0x07); LCD_WRITE_DATA(0x13); LCD_WRITE_DATA(0x21); LCD_WRITE_DATA(0x22); LCD_WRITE_DATA(0x38); LCD_WRITE_DATA(0x32); LCD_WRITE_DATA(0x06); LCD_WRITE_DATA(0x03); LCD_WRITE_DATA(0x20); LCD_WRITE_DATA(0x2c); LCD_WRITE_DATA(0x34); LCD_WRITE_COMMAND(0x36); LCD_WRITE_DATA(0x08); LCD_WRITE_COMMAND(0x11); sunxi_lcd_delay_ms(120); LCD_WRITE_COMMAND(0x29); /*Display on*/ LCD_WRITE_COMMAND(0x2C); } static s32 lcd_user_defined_func(u32 sel, u32 para1, u32 para2, u32 para3) { return 0; } struct __lcd_panel ili9341_80_panel = { /* panel driver name, must mach the name of lcd_drv_name in sys_config.fex */ .name = "ili9341_80", .func = { .cfg_panel_info = lcd_cfg_panel_info, .cfg_open_flow = lcd_open_flow, .cfg_close_flow = lcd_close_flow, .lcd_user_defined_func = lcd_user_defined_func, }, };H文件
#ifndef __ILI9341_80_PANEL_H__ #define __ILI9341_80_PANEL_H__ #include "panels.h" extern struct __lcd_panel ili9341_80_panel; #endif2.在kconfig添加驱动项
文件lichee/brandy-2.0/u-boot-2018/drivers/video/sunxi/disp2/disp/lcd/Kconfig，增加config LCD_SUPPORT_ILI9341_80_PANEL bool "LCD support ili9341 i80 panel" default y ---help--- If you want to support led panel for display driver, select it.This panel used for ili9341 i80 mode.- makfile添加编译
文件lichee/brandy-2.0/u-boot-2018/drivers/video/sunxi/disp2/disp/Makefile，在屏幕编译部分添加
disp-$(CONFIG_LCD_SUPPORT_HE0801A068) += lcd/he0801a068.o ... disp-$(CONFIG_LCD_SUPPORT_K101_MM2QA01_A) += lcd/K101_MM2QA01_A.o disp-$(CONFIG_LCD_SUPPORT_ILI9341_80_PANEL) += lcd/ili9341_80.o- 将上面的panel添加到panels
文件lichee/brandy-2.0/u-boot-2018/drivers/video/sunxi/disp2/disp/lcd/panels.h
在后面最后一行#endif前添加
#ifdef CONFIG_LCD_SUPPORT_ILI9341_80_PANEL extern __lcd_panel_t ili9341_80_panel; #endif文件lichee/brandy-2.0/u-boot-2018/drivers/video/sunxi/disp2/disp/lcd/panels.c
panel_array结构体最后的null前面添加#ifdef CONFIG_LCD_SUPPORT_ILI9341_80_PANEL &ili9341_80_panel, #endif- 修改设备树
在lichee/linux-5.4/arch/riscv/boot/dts/sunxi/sun20iw1p1.dtsi添加I80的引脚分配
pio: pinctrl@2000000 { ... I8080_16bit_pins_a: I8080_16bit@0 { pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", \ "PD6", "PD7" ,"PD8","PD9","PD10", "PD11","PD12","PD13","PD14","PD15", \ "PD18", "PD19", "PD20", "PD21"; function = "lcd0"; drive-strength = <30>; bias-disable; }; I8080_16bit_pins_b: I8080_16bit@1 { pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", \ "PD6", "PD7" ,"PD8","PD9","PD10", "PD11","PD12","PD13","PD14","PD15", \ "PD18", "PD19", "PD20", "PD21"; function = "io_disabled"; bias-disable; }; }在device/config/chips/f133/configs/mq_r/linux-5.4/board.dts
添加lcd0的配置，将其他lcd0屏蔽
根据Tina_lcd的文档，lcd_cpu_if取值0： 18bit/1cycle (RGB666) 2: 16bit/3cycle (RGB666) 4： 16bit/2cycle (RGB666) 6： 16bit/2cycle (RGB666) 8： 16bit/1cycle (RGB565) 10： 9bit/1cycle (RGB666) 12： 8bit/3cycle (RGB666) 14： 8bit/2cycle (RGB565)/*
;8080 320240/
&lcd0 {
lcd_used = <1>;
lcd_driver_name = "ili9341_80";
lcd_backlight = <80>;
lcd_if = <1>;
lcd_cpu_if = <8>;
lcd_x = <320>;
lcd_y = <240>;
lcd_width = <108>;
lcd_height = <64>;
lcd_dclk_freq = <16>;
lcd_hbp = <20>;
lcd_ht = <360>;
lcd_hspw = <10>;
lcd_vbp = <8>;
lcd_vt = <256>;
lcd_vspw = <4>;lcd_pwm_used = <1>; lcd_pwm_ch = <7>; lcd_pwm_freq = <500>; lcd_pwm_pol = <0>; /* lcd_lvds_if = <0>; lcd_lvds_colordepth = <1>; lcd_lvds_mode = <0>; */ lcd_frm = <0>; lcd_io_phase = <0x0000>; lcd_gamma_en = <0>; lcd_bright_curve_en = <0>; lcd_cmap_en = <0>; deu_mode = <0>; lcdgamma4iep = <22>; smart_color = <90>; pinctrl-0 = <&I8080_16bit_pins_a>; pinctrl-1 = <&I8080_16bit_pins_b>; lcd_gpio_0 = <&pio PD 16 GPIO_ACTIVE_HIGH>; status = "okay";};
在device/config/chips/f133/configs/mq_r/uboot-board.dts同样修改/* ;8080 320*240*/ &lcd0 { lcd_used = <1>; lcd_driver_name = "ili9341_80"; lcd_backlight = <80>; lcd_if = <1>; lcd_cpu_if = <8>; lcd_x = <320>; lcd_y = <240>; lcd_width = <108>; lcd_height = <64>; lcd_dclk_freq = <16>; lcd_hbp = <20>; lcd_ht = <360>; lcd_hspw = <10>; lcd_vbp = <8>; lcd_vt = <256>; lcd_vspw = <4>; lcd_pwm_used = <1>; lcd_pwm_ch = <7>; lcd_pwm_freq = <500>; lcd_pwm_pol = <0>; /* lcd_lvds_if = <0>; lcd_lvds_colordepth = <1>; lcd_lvds_mode = <0>; */ lcd_frm = <0>; lcd_io_phase = <0x0000>; lcd_gamma_en = <0>; lcd_bright_curve_en = <0>; lcd_cmap_en = <0>; deu_mode = <0>; lcdgamma4iep = <22>; smart_color = <90>; pinctrl-0 = <&I8080_16bit_pins_a>; pinctrl-1 = <&I8080_16bit_pins_b>; lcd_gpio_0 = <&pio PD 16 GPIO_ACTIVE_HIGH>; status = "okay"; };board.dts和uboot_board.dts中disp部分如下：
&disp { disp_init_enable = <1>; disp_mode = <0>; screen0_output_type = <1>; screen0_output_mode = <4>; screen1_output_type = <1>; screen1_output_mode = <4>; screen1_output_format = <0>; screen1_output_bits = <0>; screen1_output_eotf = <4>; screen1_output_cs = <257>; screen1_output_range = <2>; screen1_output_scan = <0>; screen1_output_aspect_ratio = <8>; dev0_output_type = <1>; dev0_output_mode = <4>; dev0_screen_id = <0>; dev0_do_hpd = <0>; dev1_output_type = <4>; dev1_output_mode = <10>; dev1_screen_id = <1>; dev1_do_hpd = <1>; def_output_dev = <0>; fb0_format = <0>; /* fb0_width = <320>; fb0_height = <240>; */ fb0_width = <320>; fb0_height = <240>; fb1_format = <0>; fb1_width = <0>; fb1_height = <0>; chn_cfg_mode = <1>; disp_para_zone = <1>; /*VCC-LCD*/ /* dc1sw-supply = <®_dc1sw>;*/ /*VCC-DSI*/ /* eldo3-supply = <®_eldo3>;*/ /*VCC-PD*/ /* dcdc1-supply = <®_dcdc1>;*/ };- 在lichee/brandy-2.0/u-boot-2018/configs/sun20iw1p1_defconfig屏幕部分添加
CONFIG_LCD_SUPPORT_ILI9341_80_PANEL=y - 编译打包烧录
这是整个操作步骤，最后结果就是开头部分，是哪里没有改到还是弄错了的
- 在lichee/brandy-2.0/u-boot-2018/drivers/video/sunxi/disp2/disp/lcd/路径添加ili9341_80.c和ili9341_80.h
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