Any update on the source code? I have downloaded d1_freertos_20211105_4.rar.
I have done an independent version, pretty much came to the same results as here. All tick timer stuff works fine using CSR time and MMIO MTIMECMP. The comments about 'stability' bother me, mine runs for hours and hours doing simple stuff.
While working on my drivers for UART, TMR, SPI, etc. I always start with POLLING, then do INTERRUPT, then do DMA (where needed). All my polling stuff works fine. I can't get ANY of my interrupt stuff to work. My main problem is that I can't get ANY of the Peripherals to trigger the PLIC_IP registers to even initiate an External Interrupt to the CLINT. I've checked enables, priorities etc. Think I have them all set correctly.
I downloaded this version because it looked like it had some interrupt stuff in it. After searching through all the source code with a fine tooth comb I can only find the 'potential' for the interrupt, never a call from driver or application code to enable/use it.
Has anyone done any external interrupts (TMR or UART) in a FREERTOS Bare Metal environment?
Is there some secret mux or clock enable to get the TMR peripheral to connect to the PLIC to connect to MEI of CLINT? OpenSBI does enable the RISCV_CFG_BGR registers and I had hopes that would be the missing link, but it didn't fix it. MXSTATUS for Supervisor Delegation etc. isn't needed since FREERTOS runs in Machine mode. Any other suggestions?
Of course Linux/Tina must use interrupts but I've searched for hours in source code and can't find anything. Could be buried deep in the DTS.
-Ed
