全志在线开发者论坛

shz18877605430

@chengwei_peng 好像改了也没用。

shz18877605430

@abcdef 在 tina linux 开发摄像头屏幕预览，录制功能中说：

disp_mgr_set_layer_config2

大佬，解决了吗？我也遇到一样的问题。

shz18877605430

各位大佬救救急！！！

T113-s3获取ov5640下枚举格式失败，再if(0 != ioctl(fd,VIDIOC_ENUM_FMT,&fmtdesc))处直接break掉了。

说明一下：ov5640正常使用没有问题，能拍照，已测试过的。

#include <sys/types.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <sys/ioctl.h>
#include <unistd.h>
#include <stdio.h>
#include <string.h>
#include <linux/types.h>
#include <linux/videodev2.h>

/* ./app_ov5640 </dev/video0>*/
int main(int argc,char **argv)
{
    int fd;
    struct v4l2_fmtdesc fmtdesc;
    struct v4l2_frmsizeenum fsenum;
    int fmt_index = 0;
    int frame_index = 0;
    
    if(argc != 2){
        printf("Usage %s </dev/videoX>,print format detail for video device\n",argv[0]);
        return -1;
    }

    /* open */
    fd = open(argv[1],O_RDWR);
    if(fd < 0){
        printf("can not open %s\n",argv[1]);
        return -1;
    }

    while(1)
    {
        /* 枚举格式 */
        fmtdesc.index = fmt_index;  //比如从0开始
        fmtdesc.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;    //指定type为"捕获"
        
        if(0 != ioctl(fd,VIDIOC_ENUM_FMT,&fmtdesc))
            break;

        frame_index = 0;
        while(1)
        {
            /* 枚举这种个格式所支持的帧大小*/
            memset(&fsenum,0,sizeof(struct v4l2_frmsizeenum));
            fsenum.pixel_format = fmtdesc.pixelformat;
            fsenum.index = frame_index;

            if(ioctl(fd,VIDIOC_ENUM_FRAMESIZES,&fsenum) == 0){
                printf("format %s,%d, framesize %d: %d x %d\n",fmtdesc.description,fmtdesc.pixelformat,frame_index,fsenum.discrete.width,fsenum.discrete.height);
            }else{
                break;
            }
            frame_index++;
        }
        fmt_index++;
    }

    return 0;
}

shz18877605430

nand flash切换到SD卡启动，挂载分区的时候报错，文件系统均改为ext4le ,内核已开启ext4文件系统，以及make menuconfig下的e2fprogs，但是还是不行，配置如下：

env


#kernel command arguments
earlyprintk=sunxi-uart,0x02500C00
initcall_debug=0
console=ttyS3,115200
nand_root=/dev/ubiblock0_5
mmc_root=/dev/mmcblk0p5
mtd_name=sys
rootfstype=squashfs
root_partition=rootfs
boot_partition=boot
init=/sbin/init
loglevel=8
cma=8M
mac=
wifi_mac=
bt_mac=
specialstr=
keybox_list=widevine,ec_key,ec_cert1,ec_cert2,ec_cert3,rsa_key,rsa_cert1,rsa_cert2,rsa_cert3
dsp0_partition=dsp0
rootdelay=2
#set kernel cmdline if boot.img or recovery.img has no cmdline we will use this
setargs_nand=setenv bootargs ubi.mtd=${mtd_name} ubi.block=0,${root_partition} earlyprintk=${earlyprintk} clk_ignore_unused initcall_debug=${initcall_debug} console=${console} loglevel=${loglevel} root=${nand_root} rootfstype=${rootfstype} init=${init} partitions=${partitions} cma=${cma} snum=${snum} mac_addr=${mac} wifi_mac=${wifi_mac} bt_mac=${bt_mac} specialstr=${specialstr} gpt=1
setargs_nand_ubi=setenv bootargs ubi.mtd=${mtd_name} ubi.block=0,${root_partition} earlyprintk=${earlyprintk} clk_ignore_unused initcall_debug=${initcall_debug} console=${console} loglevel=${loglevel} root=${nand_root} rootfstype=${rootfstype} init=${init} partitions=${partitions} cma=${cma} snum=${snum} mac_addr=${mac} wifi_mac=${wifi_mac} bt_mac=${bt_mac} specialstr=${specialstr} gpt=1
setargs_mmc=setenv  bootargs earlyprintk=${earlyprintk} clk_ignore_unused initcall_debug=${initcall_debug} console=${console} loglevel=${loglevel} root=${mmc_root}  init=${init} partitions=${partitions} cma=${cma} snum=${snum} mac_addr=${mac} wifi_mac=${wifi_mac} bt_mac=${bt_mac} specialstr=${specialstr} gpt=1
#nand command syntax: sunxi_flash read address partition_name read_bytes
#0x4007f800 = 0x40080000(kernel entry) - 0x800(boot.img header 2k)
#boot_dsp0=sunxi_flash read 45000000 ${dsp0_partition};bootr 45000000 0 0
#boot_normal=sunxi_flash read 45000000 ${boot_partition};bootm 45000000
boot_dsp0=sunxi_flash read 40000000 ${dsp0_partition};bootr 40000000 0 0
boot_normal=sunxi_flash read 41000000 ${boot_partition};bootm 41000000
boot_recovery=sunxi_flash read 43000000 recovery;bootm 43000000
boot_fastboot=fastboot

#uboot system env config
bootdelay=1
#default bootcmd, will change at runtime according to key press
#default nand boot
bootcmd=run setargs_mmc boot_normal

sys_config

;----------------------------------------------------------------------------------
;storage_type   = boot medium, 0-nand, 1-sd, 2-emmc, 3-nor, 4-emmc3, 5-spinand -1(defualt)auto scan
;----------------------------------------------------------------------------------
[target]
boot_clock   	= 1008
storage_type    = 1
nand_use_ubi	= 0

board.dts

&spi0 {
	clock-frequency = <100000000>;
	pinctrl-0 = <&spi0_pins_a &spi0_pins_b>;
	pinctrl-1 = <&spi0_pins_c>;
	pinctrl-names = "default", "sleep";
	/*spi-supply = <&reg_dcdc1>;*/
	spi_slave_mode = <0>;
	spi0_cs_number = <1>;
    spi0_cs_bitmap = <1>;
	status = "disabled";

	spi-nand@0 {
		compatible = "spi-nand";
		spi-max-frequency=<100000000>;
		reg = <0x0>;
		spi-rx-bus-width=<0x04>;
		spi-tx-bus-width=<0x04>;
		status="disabled";
	};

	spi-nor@0 {
		compatible = "jedec,spi-nor";
		spi-max-frequency=<30000000>;
		reg = <0x0>;
		spi-rx-bus-width=<0x01>;
		spi-tx-bus-width=<0x01>;
		status="disabled";
	};
};

&sdc0 {
	bus-width = <4>;
	cd-gpios = <&pio PF 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; 
	/*non-removable;*/
	/*broken-cd;*/
	/*cd-inverted;*/
	/*data3-detect;*/
	/*card-pwr-gpios = <&pio PH 14 1 1 2 0xffffffff>;*/
	cd-used-24M;
	cap-sd-highspeed;
	/*sd-uhs-sdr50;*/
	/*sd-uhs-ddr50;*/
	/*sd-uhs-sdr104;*/
	no-sdio;
	//no-mmc;
	sunxi-power-save-mode;
	/*sunxi-dis-signal-vol-sw;*/
	max-frequency = <150000000>;
	ctl-spec-caps = <0x8>;
	/*vmmc-supply = <&reg_dcdc1>;*/
	/*vqmmc33sw-supply = <&reg_dcdc1>;*/
	/*vdmmc33sw-supply = <&reg_dcdc1>;*/
	/*vqmmc18sw-supply = <&reg_eldo1>;*/
	/*vdmmc18sw-supply = <&reg_eldo1>;*/
	status = "okay";
};

syslog如下：

shz18877605430

参照了“T113的主线linux（最新gcc+awboot+最新kernel+最新buildroot）”，发现内核起来之后，读分区的时候失败了，日志如下所示。各位大佬指点指点一下，谢谢。

[    1.115794] [drm] Initialized sun4i-drm 1.0.0 20150629 for display-engine on minor 0
[    1.125610] spi-nand spi0.0: GigaDevice SPI NAND was found.
[    1.131241] spi-nand spi0.0: 128 MiB, block size: 128 KiB, page size: 2048, OOB size: 128
[    1.140134] 4 fixed-partitions partitions found on MTD device spi0.0
[    1.146506] Creating 4 MTD partitions on "spi0.0":
[    1.151335] 0x000000000000-0x000000040000 : "awboot"
[    1.156617] ------------[ cut here ]------------
[    1.161243] kernel BUG at drivers/dma/dmaengine.h:54!
[    1.166290] Internal error: Oops - BUG: 0 [#1] SMP ARM
[    1.171424] Modules linked in:
[    1.174482] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 6.1.0-rc3-443875-gb466df90d48f-dirty #3
[    1.182998] Hardware name: Generic DT based system
[    1.187782] PC is at sun6i_dma_interrupt+0x1a8/0x1ac
[    1.192759] LR is at sun6i_dma_interrupt+0xec/0x1ac
[    1.197639] pc : [<c04a362c>]    lr : [<c04a3570>]    psr: 60000193
[    1.203898] sp : c0d01d68  ip : 0626c000  fp : 00000000
[    1.209116] r10: 00000000  r9 : 00000010  r8 : c11ff440
[    1.214333] r7 : 00000000  r6 : c122810c  r5 : c11ff640  r4 : 00000007
[    1.220852] r3 : c122810c  r2 : c1b32b80  r1 : 00000000  r0 : c1228168
[    1.227372] Flags: nZCv  IRQs off  FIQs on  Mode SVC_32  ISA ARM  Segment none
[    1.234586] Control: 10c5387d  Table: 4000406a  DAC: 00000051
[    1.240323] Register r0 information: non-slab/vmalloc memory
[    1.245980] Register r1 information: NULL pointer
[    1.250679] Register r2 information: slab kmalloc-128 start c1b32b80 pointer offset 0 size 128
[    1.256689] spi_master spi0: spi0.0: timeout transferring 1 bytes@100000000Hz for 110(100)ms
[    1.259295] Register r3 information: non-slab/vmalloc memory
[    1.267737] spi-nand spi0.0: SPI transfer failed: -110
[    1.273363] Register r4 information: non-paged memory
[    1.278504] spi_master spi0: failed to transfer one message from queue
[    1.283533] Register r5 information: slab kmalloc-512 start c11ff600 pointer offset 64 size 512
[    1.290560] 0x000000040000-0x000000080000 : "dtb"
[    1.298740] Register r6 information: non-slab/vmalloc memory
[    1.298747] Register r7 information: NULL pointer
[    1.298752] Register r8 information: slab kmalloc-512 start c11ff400 pointer offset 64 size 512
[    1.298768] Register r9 information: zero-size pointer
[    1.298773] Register r10 information: NULL pointer
[    1.332396] Register r11 information: NULL pointer
[    1.337183] Register r12 information: non-paged memory
[    1.342316] Process swapper/0 (pid: 0, stack limit = 0x(ptrval))
[    1.348316] Stack: (0xc0d01d68 to 0xc0d02000)
[    1.352672] 1d60:                   c04a3484 c113b080 c092766c 00000000 0000001e c12ed000
[    1.360841] 1d80: c0d01dd8 00000018 40000006 c016a854 c1b26500 00000001 c12ed000 c092766c
[    1.369010] 1da0: c12ed06c c0c5d208 c880a00c c016a9ac c12ed000 c092766c c880a000 c016f1e4
[    1.377178] 1dc0: c0d052fc c0d7a978 c880a000 c016a108 c0d052fc c046c77c c0c5ddfc c0d01e08
[    1.385347] 1de0: 00000000 c0d01e3c c0c5de40 c0d08100 00000018 c08b8a08 c015d428 20000113
[    1.393517] 1e00: ffffffff c0100ba8 c0d03c88 c0d03c8c c0d03c8c ffffffff c122814c c1228150
[    1.401686] 1e20: c1228150 c6ec7328 c0c5de40 00000040 00000018 40000006 0000000c c0d01e58
[    1.406688] spi_master spi0: spi0.0: timeout transferring 1 bytes@100000000Hz for 110(100)ms
[    1.409854] 1e40: 00000000 c015d428 20000113 ffffffff 00000051 7610cb08 00000000 c883569c
[    1.418289] spi-nand spi0.0: SPI transfer failed: -110
[    1.426436] 1e60: c1228150 ffffffff 00000000 7610cb08 c122810c c0121a08 c04a3484 c113b080
[    1.431573] spi_master spi0: failed to transfer one message from queue
[    1.439723] 1e80: c092766c c122814c c11ff53c c0121cb8 00000000 c0d03098 00000100 c0d08100
[    1.439732] 1ea0: c0d01eb0 c0d03080 00000018 c0101384 c880a00c c0d01ee8 c0d03080 c0c5b3b0
[    1.462566] 1ec0: 0000000a c0c5de40 c0c5b324 ffff8b43 c0d03d40 04200002 c880a000 c016a108
[    1.470735] 1ee0: c0d052fc c0d08100 60000013 ffffffff c0d01f4c 00000056 c0d08100 c0c44a68
[    1.478904] 1f00: 00000000 c01221e0 c0107464 c01222a0 c0107464 c0100ba8 00000005 00000000
[    1.487073] 1f20: 00000d99 c01160c0 00000000 c0d04f0c c0d08100 c0d04f54 00000056 00000000
[    1.495241] 1f40: c0c44a68 00000000 c0d03d80 c0d01f68 c0107460 c0107464 60000013 ffffffff
[    1.503410] 1f60: 00000051 c0d04f0c 00000000 c08bfb9c 00000000 c01555b4 000000ec c0d04ec0
[    1.511579] 1f80: 10c0387d c0e1a678 00000056 c01558e8 c0d0c244 c08b8e34 c0def040 c0c00a98
[    1.519747] 1fa0: c0def040 c0c010cc ffffffff ffffffff 00000000 c0c006ec c0d08100 00000000
[    1.527916] 1fc0: 00000000 c0c44a68 7616ca08 00000000 00000000 c0c00420 00000051 10c0387d
[    1.536086] 1fe0: ffffffff 44000000 410fc075 10c5387d 00000000 00000000 00000000 00000000
[    1.544260]  sun6i_dma_interrupt from __handle_irq_event_percpu+0x44/0x118
[    1.546682] spi_master spi0: spi0.0: timeout transferring 1 bytes@100000000Hz for 110(100)ms
[    1.551149]  __handle_irq_event_percpu from handle_irq_event+0x44/0x8c
[    1.559584] spi-nand spi0.0: SPI transfer failed: -110
[    1.566082]  handle_irq_event from handle_fasteoi_irq+0x98/0x18c
[    1.571229] spi_master spi0: failed to transfer one message from queue
[    1.577203]  handle_fasteoi_irq from generic_handle_domain_irq+0x28/0x38
[    1.577220]  generic_handle_domain_irq from gic_handle_irq+0x74/0x88
[    1.584144] 0x000000080000-0x000000800000 : "kernel"
[    1.590420]  gic_handle_irq from generic_handle_arch_irq+0x34/0x44
[    1.590437]  generic_handle_arch_irq from __irq_svc+0x88/0xb0
[    1.613643] Exception stack(0xc0d01e08 to 0xc0d01e50)
[    1.618693] 1e00:                   c0d03c88 c0d03c8c c0d03c8c ffffffff c122814c c1228150
[    1.626862] 1e20: c1228150 c6ec7328 c0c5de40 00000040 00000018 40000006 0000000c c0d01e58
[    1.635028] 1e40: 00000000 c015d428 20000113 ffffffff
[    1.640075]  __irq_svc from wake_up_var+0x50/0x94
[    1.644788]  wake_up_var from tasklet_clear_sched+0x4c/0xa8
[    1.650359]  tasklet_clear_sched from tasklet_action_common.constprop.0+0xc0/0x108
[    1.657931]  tasklet_action_common.constprop.0 from __do_softirq+0x104/0x27c
[    1.664981]  __do_softirq from __irq_exit_rcu+0xa4/0xc8
[    1.670210]  __irq_exit_rcu from irq_exit+0x8/0x10
[    1.675006]  irq_exit from __irq_svc+0x88/0xb0
[    1.679454] Exception stack(0xc0d01f18 to 0xc0d01f60)
[    1.684500] 1f00:                                                       00000005 00000000
[    1.692669] 1f20: 00000d99 c01160c0 00000000 c0d04f0c c0d08100 c0d04f54 00000056 00000000
[    1.700838] 1f40: c0c44a68 00000000 c0d03d80 c0d01f68 c0107460 c0107464 60000013 ffffffff
[    1.706686] spi_master spi0: spi0.0: timeout transferring 1 bytes@100000000Hz for 110(100)ms
[    1.709002]  __irq_svc from arch_cpu_idle+0x38/0x3c
[    1.717442] spi-nand spi0.0: SPI transfer failed: -110
[    1.722292]  arch_cpu_idle from default_idle_call+0x24/0x34
[    1.727433] spi_master spi0: failed to transfer one message from queue
[    1.732980]  default_idle_call from do_idle+0xa4/0x120
[    1.744622]  do_idle from cpu_startup_entry+0x18/0x1c
[    1.749673]  cpu_startup_entry from rest_init+0xa8/0xac
[    1.754899]  rest_init from arch_post_acpi_subsys_init+0x0/0x8
[    1.760744] Code: e28800fc 1afffff2 ebf1f9c1 eafffff0 (e7f001f2)
[    1.766832] ---[ end trace 0000000000000000 ]---
[    1.771443] Kernel panic - not syncing: Fatal exception in interrupt
[    1.777792] CPU1: stopping
[    1.780501] CPU: 1 PID: 0 Comm: swapper/1 Tainted: G      D            6.1.0-rc3-443875-gb466df90d48f-dirty #3
[    1.790490] Hardware name: Generic DT based system
[    1.795277]  unwind_backtrace from show_stack+0x10/0x14
[    1.800508]  show_stack from dump_stack_lvl+0x40/0x4c
[    1.805559]  dump_stack_lvl from do_handle_IPI+0xec/0x124
[    1.810959]  do_handle_IPI from ipi_handler+0x18/0x20
[    1.816011]  ipi_handler from handle_percpu_devid_irq+0x78/0x134
[    1.822019]  handle_percpu_devid_irq from generic_handle_domain_irq+0x28/0x38
[    1.829156]  generic_handle_domain_irq from gic_handle_irq+0x74/0x88
[    1.835512]  gic_handle_irq from generic_handle_arch_irq+0x34/0x44
[    1.841692]  generic_handle_arch_irq from call_with_stack+0x18/0x20
[    1.847965]  call_with_stack from __irq_svc+0x98/0xb0
[    1.853021] Exception stack(0xc8849f68 to 0xc8849fb0)
[    1.858069] 9f60:                   00000005 00000000 000012d1 c01160c0 00000001 c0d04f0c
[    1.866237] 9f80: c104ee80 c0d04f54 4000406a 410fc075 00000000 00000000 c0d03d80 c8849fb8
[    1.874403] 9fa0: c0107460 c0107464 60000013 ffffffff
[    1.879447]  __irq_svc from arch_cpu_idle+0x38/0x3c
[    1.884329]  arch_cpu_idle from default_idle_call+0x24/0x34
[    1.889908]  default_idle_call from do_idle+0xa4/0x120
[    1.895049]  do_idle from cpu_startup_entry+0x18/0x1c
[    1.900100]  cpu_startup_entry from secondary_start_kernel+0x118/0x120
[    1.906626]  secondary_start_kernel from 0x401015a0
[    1.911510] ---[ end Kernel panic - not syncing: Fatal exception in interrupt ]---

shz18877605430

@shz18877605430 各位大佬，用什么交叉工具链能编译出可以在tina T113板子上运行呢？

shz18877605430

各位大佬，指点一下。

自己下载了buildroot-2022.05.2，然后用了gcc-linaro-7.2.1-2017.11-x86_64_arm-linux-gnueabi 的交叉编译链，编译出来的vsftpd再开发板上无法运行。

但是我自己写了一个APP程序，用了和buildroot一样的工具链编译，编译出来的程序无法再开发板上运行，如果用sdk下的编译器是可以再板子上运行。其中，图中所示第一个app是不可以运行的。app_ok是可以运行的。

shz18877605430

@qq1844641696 在全志T113-s3使用ov5640加载insmod vin_v4l2.ko报错中说：

请问您解决了吗？我也是差不多这个问题

没有哦

shz18877605430

@whycan 勾选了。

shz18877605430

大佬们，帮忙看看，运行rtk_hciattach -n -s 115200 ttyS1 rtk_h5 & 出现了ERROR: Can't set device 93, Protocol not supported 。

shz18877605430

@qq1844641696 没有捏

shz18877605430

@whycan 晕哥，我改了还是不行。这个源码我也看了，link的时候，对比不过，link返回了NULL。

shz18877605430

全志T113-s3使用ov5640加载insmod vin_v4l2.ko报错，各位大佬救救急，搞了很久了，一直没有眉目。

配置如下：

board.dts

/*
 * Allwinner Technology CO., Ltd.
 */

/dts-v1/;

 /* optee used 7MB: SHM 2M: OS: 1M: TA:4M*/
/memreserve/ 0x41B00000 0x00100000;
/* DSP used 1MB */
/*/memreserve/ 0x42000000 0x00100000;*/
#include "sun8iw20p1.dtsi"

/{
	model = "sun8iw20";
	compatible = "allwinner,r528", "arm,sun8iw20p1";

	reg_vdd_cpu: vdd-cpu {
		compatible = "sunxi-pwm-regulator";
		pwms = <&pwm 3 5000 0>;
		regulator-name = "vdd_cpu";
		regulator-min-microvolt = <810000>;
		regulator-max-microvolt = <1160000>;
		regulator-ramp-delay = <25>;
		regulator-always-on;
		regulator-boot-on;
		status = "okay";
	};

	reg_usb1_vbus: usb1-vbus {
		compatible = "regulator-fixed";
		regulator-name = "usb1-vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-enable-ramp-delay = <1000>;
		gpio = <&pio PB 3 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};
};

&cpu0 {
	cpu-supply = <&reg_vdd_cpu>;
};

&pio {
	sdc0_pins_a: sdc0@0 {
		allwinner,pins = "PF0", "PF1", "PF2",
				 "PF3", "PF4", "PF5";
		allwinner,function = "sdc0";
		allwinner,muxsel = <2>;
		allwinner,drive = <3>;
		allwinner,pull = <1>;
		pins = "PF0", "PF1", "PF2",
		       "PF3", "PF4", "PF5";
		function = "sdc0";
		drive-strength = <30>;
		bias-pull-up;
		power-source = <3300>;
	};


	sdc0_pins_b: sdc0@1 {
		pins = "PF0", "PF1", "PF2",
		       "PF3", "PF4", "PF5";
		function = "sdc0";
		drive-strength = <30>;
		bias-pull-up;
		power-source = <1800>;
	};

	sdc0_pins_c: sdc0@2 {
		pins = "PF0", "PF1", "PF2",
			"PF3", "PF4", "PF5";
		function = "gpio_in";
	};

	/* TODO: add jtag pin */
	sdc0_pins_d: sdc0@3 {
		pins = "PF2", "PF4";
		function = "uart0";
		drive-strength = <10>;
		bias-pull-up;
	};

	sdc0_pins_e: sdc0@4 {
		pins = "PF0", "PF1", "PF3",
			"PF5";
		function = "jtag";
		drive-strength = <10>;
		bias-pull-up;
	};


	sdc1_pins_a: sdc1@0 {
		pins = "PG0", "PG1", "PG2",
		       "PG3", "PG4", "PG5";
		function = "sdc1";
		drive-strength = <30>;
		bias-pull-up;
	};

	sdc1_pins_b: sdc1@1 {
		pins = "PG0", "PG1", "PG2",
		       "PG3", "PG4", "PG5";
			function = "gpio_in";
	};

	sdc2_pins_a: sdc2@0 {
		allwinner,pins = "PC2", "PC3", "PC4",
				 "PC5", "PC6", "PC7";
		allwinner,function = "sdc2";
		allwinner,muxsel = <3>;
		allwinner,drive = <3>;
		allwinner,pull = <1>;
		pins = "PC2", "PC3", "PC4",
			"PC5", "PC6", "PC7";
		function = "sdc2";
		drive-strength = <30>;
		bias-pull-up;
	};

	sdc2_pins_b: sdc2@1 {
		pins = "PC2", "PC3", "PC4",
		       "PC5", "PC6", "PC7";
		function = "gpio_in";
	};

	wlan_pins_a:wlan@0 {
		pins = "PG11";
		function = "clk_fanout1";
	};

    uart0_pins_a: uart0_pins@0 {  /* For EVB1 board */
        pins = "PF2", "PF4";
        function = "uart0";
        drive-strength = <10>;
        bias-pull-up;
    };

    uart0_pins_b: uart0_pins@1 {  /* For EVB1 board */
        pins = "PF2", "PF4";
        function = "gpio_in";
    };

	uart1_pins_a: uart1_pins@0 {  /* For EVB1 board */
		pins = "PG6", "PG7", "PG8", "PG9";
		function = "uart1";
		drive-strength = <10>;
		bias-pull-up;
	};

	uart1_pins_b: uart1_pins {  /* For EVB1 board */
		pins = "PG6", "PG7", "PG8", "PG9";
		function = "gpio_in";
	};

	uart2_pins_a: uart2_pins@0 {  /* For EVB1 board */
		pins = "PC0", "PC1";
		function = "uart2";
		drive-strength = <10>;
		bias-pull-up;
	};

	uart2_pins_b: uart2_pins@1 {  /* For EVB1 board */
		pins = "PC0", "PC1";
		function = "gpio_in";
	};

	uart3_pins_a: uart3_pins@0 {  /* For awol nezha board */
		pins = "PB6", "PB7";
		function = "uart3";
		muxsel = <7>;
		drive-strength = <10>;
		bias-pull-up;
	};

	uart3_pins_b: uart3_pins@1 {  /* For awol nezha board */
		pins = "PB6", "PB7";
		function = "gpio_in";
	};

	twi0_pins_a: twi0@0 {
		pins = "PB10", "PB11";	/*sck sda*/
		function = "twi0";
		drive-strength = <10>;
	};

	twi0_pins_b: twi0@1 {
		pins = "PB10", "PB11";
		function = "gpio_in";
	};

	twi1_pins_a: twi1@0 {
		pins = "PB4", "PB5";
		function = "twi1";
		drive-strength = <10>;
	};

	twi1_pins_b: twi1@1 {
		pins = "PB4", "PB5";
		function = "gpio_in";
	};

    twi2_pins_a: twi2@0 {
        pins = "PE12", "PE13";
        function = "twi2";
        drive-strength = <10>;
    };

    twi2_pins_b: twi2@1 {
        pins = "PE12", "PE13";
        function = "gpio_in";
    };

	twi3_pins_a: twi3@0 {
		pins = "PE6", "PE7";
		function = "twi3";
		drive-strength = <10>;
	};

	twi3_pins_b: twi3@1 {
		pins = "PE6", "PE7";
		function = "gpio_in";
	};

	dmic_pins_a: dmic@0 {
		/* DMIC_PIN: CLK, DATA0, DATA1, DATA2, DATA3*/
		pins = "PB12", "PB11", "PB10", "PE14", "PB8";
		function = "dmic";
		drive-strength = <20>;
		bias-disable;
	};

	dmic_pins_b: dmic@1 {
		pins = "PB12", "PB11", "PB10", "PE14", "PB8";
		function = "io_disabled";
		drive-strength = <20>;
		bias-disable;
	};

	daudio0_pins_a: daudio0@0 {
		pins = "PE17", "PE16", "PE15", "PE14", "PE13";
		function = "i2s0";
		drive-strength = <20>;
		bias-disable;
	};

	daudio0_pins_b: daudio0_sleep@0 {
		pins = "PE17", "PE16", "PE15", "PE14", "PE13";
		function = "io_disabled";
		drive-strength = <20>;
		bias-disable;
	};

	daudio1_pins_a: daudio1@0 {
		pins = "PG11", "PG12", "PG13", "PG14", "PG15";
		function = "i2s1";
		drive-strength = <20>;
		bias-disable;
	};

	daudio1_pins_b: daudio1_sleep@0 {
		pins = "PG11", "PG12", "PG13", "PG14", "PG15";
		function = "io_disabled";
		drive-strength = <20>;
		bias-disable;
	};

	daudio2_pins_a: daudio2@0 {
		/* I2S_PIN: MCLK, BCLK, LRCK */
		pins = "PF6", "PF3", "PF5";
		function = "i2s2";
		drive-strength = <20>;
		bias-disable;
	};

	daudio2_pins_b: daudio2@1 {
		/* I2S_PIN: DOUT0 */
		pins = "PF1";
		function = "i2s2_dout";
		drive-strength = <20>;
		bias-disable;
	};

	daudio2_pins_c: daudio2@2 {
		/* I2S_PIN: DIN0 */
		pins = "PF0";
		function = "i2s2_din";
		drive-strength = <20>;
		bias-disable;
	};

	daudio2_pins_d: daudio2_sleep@0 {
		pins = "PF6", "PF3", "PF5", "PF1", "PF0";
		function = "io_disabled";
		drive-strength = <20>;
		bias-disable;
	};

	spdif_pins_a: spdif@0 {
		/* SPDIF_PIN: SPDIF_OUT */
		pins = "PG18";
		function = "spdif";
		drive-strength = <20>;
		bias-disable;
	};

	spdif_pins_b: spdif_sleep@0 {
		pins = "PG18";
		function = "io_disabled";
		drive-strength = <20>;
		bias-disable;
	};

	spi0_pins_a: spi0@0 {
		pins = "PC2", "PC4", "PC5"; /* clk, mosi, miso */
		function = "spi0";
		muxsel = <2>;
		drive-strength = <10>;
	};

	spi0_pins_b: spi0@1 {
		pins = "PC3", "PC7", "PC6";
		function = "spi0";
		muxsel = <2>;
		drive-strength = <10>;
		bias-pull-up;   /* cs, hold, wp should be pulled up */
	};

	spi0_pins_c: spi0@2 {
		pins = "PC2", "PC3", "PC4", "PC5","PC6", "PC7";
		function = "gpio_in";
		muxsel = <0>;
		drive-strength = <10>;
	};

	spi1_pins_a: spi1@0 {
		pins = "PD11", "PD12", "PD13"; /* clk, mosi, miso */
		function = "spi1";
		drive-strength = <10>;
	};

	spi1_pins_b: spi1@1 {
		pins = "PD10", "PD14", "PD15";
		function = "spi1";
		drive-strength = <10>;
		bias-pull-up;   /* cs, hold, wp should be pulled up */
	};

	spi1_pins_c: spi1@2 {
		pins = "PD10", "PD11", "PD12", "PD13","PD14", "PD15";
		function = "gpio_in";
		drive-strength = <10>;
	};

	ledc_pins_a: ledc@0 {
		pins = "PG13";
		function = "ledc";
		drive-strength = <10>;
	};

	ledc_pins_b: ledc@1 {
		pins = "PG13";
		function = "gpio_in";
	};

	pwm0_pin_a: pwm0@0 {
		pins = "PD16";
		function = "pwm0";
		drive-strength = <10>;
		bias-pull-up;
	};

	pwm0_pin_b: pwm0@1 {
		pins = "PD16";
		function = "gpio_in";
		bias-disable;
	};

	pwm2_pin_a: pwm2@0 {
		pins = "PD18";
		function = "pwm2";
		drive-strength = <10>;
		bias-pull-up;
	};

	pwm2_pin_b: pwm2@1 {
		pins = "PD18";
		function = "gpio_out";
	};

	pwm7_pin_a: pwm7@0 {
		pins = "PD22";
		function = "pwm7";
		drive-strength = <10>;
		bias-pull-up;
	};

	pwm7_pin_b: pwm7@1 {
		pins = "PD22";
		function = "gpio_in";
	};


	s_cir0_pins_a: s_cir@0 {
		pins = "PB7";
		function = "ir";
		drive-strength = <10>;
		bias-pull-up;
	};

	s_cir0_pins_b: s_cir@1 {
		pins = "PB7";
		function = "gpio_in";
	};

	ir1_pins_a: ir1@0 {
		pins = "PB0";
		function = "ir";
		drive-strength = <10>;
		bias-pull-up;
	};

	ir1_pins_b: ir1@1 {
		pins = "PB0";
		function = "gpio_in";
	};
};

&uart0 {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&uart0_pins_a>;
	pinctrl-1 = <&uart0_pins_b>;
	status = "disabled";
};

&uart1 {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&uart1_pins_a>;
	pinctrl-1 = <&uart1_pins_b>;
	status = "disabled";
};

&uart2 {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&uart2_pins_a>;
	pinctrl-1 = <&uart2_pins_b>;
	status = "disabled";
};

/* for debug */
&uart3 {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&uart3_pins_a>;
	pinctrl-1 = <&uart3_pins_b>;
	status = "okay";
};

/* for dsp debug
&uart3 {
	compatible = "allwinner,sun20iw1-dsp-uart";
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&uart3_pins_a>;
	pinctrl-1 = <&uart3_pins_b>;
	status = "okay";
};
*/

&soc {
	card0_boot_para@2 {
		/*
		 * Avoid dtc compiling warnings.
		 * @TODO: Developer should modify this to the actual value
		 */
		reg = <0x0 0x2 0x0 0x0>;
		device_type = "card0_boot_para";
		card_ctrl = <0x0>;
		card_high_speed = <0x1>;
		card_line = <0x4>;
		pinctrl-0 = <&sdc0_pins_a>;
	};

	card2_boot_para@3 {
		/*
		 * Avoid dtc compiling warnings.
		 * @TODO: Developer should modify this to the actual value
		 */
		reg = <0x0 0x3 0x0 0x0>;
		device_type = "card2_boot_para";
		card_ctrl = <0x2>;
		card_high_speed = <0x1>;
		card_line = <0x4>;
		pinctrl-0 = <&sdc2_pins_a>;
		/*pinctrl-0 = <&sdc0_pins_a>;*/
		/*sdc_ex_dly_used = <0x2>;*/
		sdc_io_1v8 = <0x1>;
		/*sdc_type = "tm4";*/
		sdc_tm4_hs200_max_freq = <150>;
		sdc_tm4_hs400_max_freq = <100>;
		sdc_ex_dly_used = <2>;
		/*sdc_tm4_win_th = <8>;*/
		/*sdc_dis_host_caps = <0x180>;*/
	};

	rfkill: rfkill@0 {
		compatible    = "allwinner,sunxi-rfkill";
		chip_en;
		power_en;
		pinctrl-0 = <&wlan_pins_a>;
		pinctrl-names = "default";
		status        = "okay";

		wlan: wlan@0 {
			compatible    = "allwinner,sunxi-wlan";
			clock-names = "32k-fanout1";
			clocks = <&ccu CLK_FANOUT1_OUT>;
			wlan_busnum    = <0x1>;
			wlan_regon    = <&pio PG 12 GPIO_ACTIVE_HIGH>;
			wlan_hostwake  = <&pio PG 10 GPIO_ACTIVE_HIGH>;
			/*wlan_power    = "VCC-3V3";*/
			/*wlan_power_vol = <3300000>;*/
			/*interrupt-parent = <&pio>;
			interrupts = < PG 10 IRQ_TYPE_LEVEL_HIGH>;*/
			wakeup-source;

		};
		
		bt: bt@0 {
			compatible    = "allwinner,sunxi-bt";
			clock-names = "32k-fanout1";
			clocks = <&ccu CLK_FANOUT1_OUT>;
			/*bt_power_num = <0x01>;*/
			/*bt_power      = "axp803-dldo1";*/
			/*bt_io_regulator = "axp803-dldo1";*/
			/*bt_io_vol = <3300000>;*/
			/*bt_power_vol = <330000>;*/
			bt_rst_n      = <&pio PG 15 GPIO_ACTIVE_LOW>;
			status        = "okay";
		};
	};

	btlpm: btlpm@0 {
		compatible  = "allwinner,sunxi-btlpm";
		uart_index  = <0x1>;
		bt_wake     = <&pio PG 15 GPIO_ACTIVE_HIGH>;
		bt_hostwake = <&pio PG 14 GPIO_ACTIVE_HIGH>;
		status      = "okay";
	};

	addr_mgt: addr_mgt@0 {
		compatible     = "allwinner,sunxi-addr_mgt";
		type_addr_wifi = <0x0>;
		type_addr_bt   = <0x0>;
		type_addr_eth  = <0x0>;
		status         = "okay";
	};
};

&sdc2 {
	non-removable;
	bus-width = <4>;
	mmc-ddr-1_8v;
	mmc-hs200-1_8v;
	no-sdio;
	no-sd;
	ctl-spec-caps = <0x308>;
	cap-mmc-highspeed;
	sunxi-power-save-mode;
	sunxi-dis-signal-vol-sw;
	mmc-bootpart-noacc;
	max-frequency = <150000000>;
	/*vmmc-supply = <&reg_dcdc1>;*/
	/*emmc io vol 3.3v*/
	/*vqmmc-supply = <&reg_aldo1>;*/
	/*emmc io vol 1.8v*/
	/*vqmmc-supply = <&reg_eldo1>;*/
	status = "disabled";
};

&sdc0 {
	bus-width = <4>;
	cd-gpios = <&pio PF 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; 
	/*non-removable;*/
	/*broken-cd;*/
	/*cd-inverted;*/
	/*data3-detect;*/
	/*card-pwr-gpios = <&pio PH 14 1 1 2 0xffffffff>;*/
	cd-used-24M;
	cap-sd-highspeed;
	/*sd-uhs-sdr50;*/
	/*sd-uhs-ddr50;*/
	/*sd-uhs-sdr104;*/
	no-sdio;
	no-mmc;
	sunxi-power-save-mode;
	/*sunxi-dis-signal-vol-sw;*/
	max-frequency = <150000000>;
	ctl-spec-caps = <0x8>;
	/*vmmc-supply = <&reg_dcdc1>;*/
	/*vqmmc33sw-supply = <&reg_dcdc1>;*/
	/*vdmmc33sw-supply = <&reg_dcdc1>;*/
	/*vqmmc18sw-supply = <&reg_eldo1>;*/
	/*vdmmc18sw-supply = <&reg_eldo1>;*/
	status = "okay";
};

&sdc1 {
	bus-width = <4>;
	no-mmc;
	no-sd;
	cap-sd-highspeed;
	/*sd-uhs-sdr12*/
	/*sd-uhs-sdr25;*/
	/*sd-uhs-sdr50;*/
	/*sd-uhs-ddr50;*/
	/*sd-uhs-sdr104;*/
	/*sunxi-power-save-mode;*/
	/*sunxi-dis-signal-vol-sw;*/
	cap-sdio-irq;
	keep-power-in-suspend;
	ignore-pm-notify;
	max-frequency = <150000000>;
	ctl-spec-caps = <0x8>;
	status = "okay";
};


/*
tvd configuration
used                   (create device, 0: do not create device, 1: create device)
agc_auto_enable        (0: agc manual mode,agc_manual_value is valid; 1: agc auto mode)
agc_manual_value       (agc manual value, default value is 64)
cagc_enable            (cagc        0: disable, 1: enable)
fliter_used            (3d fliter   0: disable, 1: enable)
support two PMU power  (tvd_power0, tvd_power1)
support two GPIO power (tvd_gpio0, tvd_gpio1)
NOTICE: If tvd need pmu power or gpio power,params need be configured under [tvd]
tvd_sw                 (the switch of all tvd driver.)
tvd_interface          (0: cvbs, 1: ypbpr,)
tvd_format             (0:TVD_PL_YUV420 , 1: MB_YUV420, 2: TVD_PL_YUV422)
tvd_system             (0:ntsc, 1:pal)
tvd_row                (total row number in multi channel mode 1-2)
tvd_column             (total column number in multi channel mode 1-2)
tvd_channelx_en        (0:disable, 1~4:position in multi channel mode,In single channel
                       mode,mean enable)
tvd_row*tvd_column is the total tvd channel number to be used in multichannel mode
+--------------------+--------------------+
|                    |                    |
|                    |                    |
|         1          |         2          |
|                    |                    |
|                    |                    |
+--------------------+--------------------+
|                    |                    |
|                    |                    |
|         3          |         4          |
|                    |                    |
|                    |                    |
+--------------------+--------------------+
*/

&tvd {
	tvd_sw          = <1>;
	tvd_interface   = <0>;
	tvd_format      = <0>;
	tvd_system      = <1>;
	tvd_row         = <1>;
	tvd_column      = <1>;
	tvd_channel0_en = <1>;
	tvd_channel1_en = <0>;
	tvd_channel2_en = <0>;
	tvd_channel3_en = <0>;
	/*tvd_gpio0 = <&pio PD 22 GPIO_ACTIVE_HIGH>;*/
	/*tvd_gpio1 = <&pio PD 23 GPIO_ACTIVE_HIGH>;*/
	/*tvd_gpio2 = <&pio PD 24 GPIO_ACTIVE_HIGH>;*/
	/*	dc1sw-supply = <&reg_dc1sw>;*/
	/*	eldo3-supply = <&reg_eldo3>;*/
	/*tvd_power0      = "dc1sw"*/
	/*tvd_power1      = "eldo3"*/
};

&tvd0 {
	used                    = <1>;
	agc_auto_enable         = <1>;
	agc_manual_value        = <64>;
	cagc_enable             = <1>;
	fliter_used             = <1>;
};

/* Audio Driver modules */
&sunxi_rpaf_dsp0 {
	status = "disabled";
};

/* if audiocodec is used, sdc0 and uart0 should be closed to enable PA. */
&codec {
	/* MIC and headphone gain setting */
	mic1gain 	= <0x1F>;
	mic2gain 	= <0x1F>;
	mic3gain 	= <0x1F>;
	/* ADC/DAC DRC/HPF func enabled */
        /* 0x1:DAP_HP_EN; 0x2:DAP_SPK_EN; 0x3:DAP_HPSPK_EN */
	adcdrc_cfg 	= <0x0>;
	adchpf_cfg 	= <0x1>;
	dacdrc_cfg 	= <0x0>;
	dachpf_cfg 	= <0x0>;
	/* Volume about */
	digital_vol 	= <0x00>;
	lineout_vol 	= <0x1a>;
	headphonegain	= <0x03>;
	/* Pa enabled about */
	pa_level 	= <0x01>;
	pa_pwr_level 	= <0x01>;
	pa_msleep_time 	= <0x78>;
	/* gpio-spk	= <&pio PF 2 GPIO_ACTIVE_HIGH>;*/
	/* gpio-spk-pwr	= <&pio PF 4 GPIO_ACTIVE_HIGH>; */
	/* CMA config about */
	playback_cma	= <128>;
	capture_cma	= <256>;
	/* regulator about */
	/* avcc-supply	= <&reg_aldo1>; */
	/* hpvcc-supply	= <&reg_eldo1>; */
	status = "okay";
};

&sndcodec {
	hp_detect_case	= <0x00>;
	jack_enable	= <0x01>;
	status = "okay";
};

&dummy_cpudai {
	status = "okay";
};

&dmic {
	pinctrl-names   = "default","sleep";
	pinctrl-0       = <&dmic_pins_a>;
	pinctrl-1       = <&dmic_pins_b>;
	status = "disabled";
};

&dmic_codec {
	status = "disabled";
};

&sounddmic {
	status = "disabled";
};

/*-----------------------------------------------------------------------------
 * pcm_lrck_period	16/32/64/128/256
 * slot_width_select	16bits/20bits/24bits/32bits
 * frametype		0 --> short frame = 1 clock width;
 *			1 --> long frame = 2 clock width;
 * tdm_config		0 --> pcm
 *			1 --> i2s
 * mclk_div		0 --> not output
 *			1/2/4/6/8/12/16/24/32/48/64/96/128/176/192
 *			(set mclk as external codec clk source, freq is pll_audio/mclk_div)
 * pinctrl_used		0 --> I2S/PCM use for internal
 *			1 --> I2S/PCM use for external audio
 * daudio_type:		0 --> external audio type
 *---------------------------------------------------------------------------*/
&daudio0 {
	mclk_div 	= <0x01>;
	frametype 	= <0x00>;
	tdm_config 	= <0x01>;
	sign_extend 	= <0x00>;
	msb_lsb_first 	= <0x00>;
	pcm_lrck_period = <0x80>;
	slot_width_select = <0x20>;
	pinctrl-names   = "default", "sleep";
	pinctrl-0       = <&daudio0_pins_a>;
	pinctrl-1       = <&daudio0_pins_b>;
	pinctrl_used	= <0x0>;
	status = "disabled";
};

/*-----------------------------------------------------------------------------
 * simple-audio-card,name	name of sound card, e.g.
 *				"snddaudio0" --> use for external audio
 * sound-dai			"snd-soc-dummy" --> use for I2S
 *				"ac108" --> use for external audio of ac108
 *---------------------------------------------------------------------------*/
&sounddaudio0 {
	/* simple-audio-card,format = "i2s"; */
	/* simple-audio-card,frame-master = <&daudio0_master>; */
	/* simple-audio-card,bitclock-master = <&daudio0_master>; */
	/* simple-audio-card,bitclock-inversion; */
	/* simple-audio-card,frame-inversion; */
	status = "disabled";
	daudio0_master: simple-audio-card,codec {
		/* sound-dai = <&ac108>; */
	};
};

&daudio1 {
	mclk_div 	= <0x01>;
	frametype 	= <0x00>;
	tdm_config 	= <0x01>;
	sign_extend 	= <0x00>;
	msb_lsb_first 	= <0x00>;
	pcm_lrck_period = <0x80>;
	slot_width_select = <0x20>;
	pinctrl-names   = "default", "sleep";
	pinctrl-0       = <&daudio1_pins_a>;
	pinctrl-1       = <&daudio1_pins_b>;
	pinctrl_used	= <0x0>;
	status = "disabled";
};

&sounddaudio1 {
	status = "disabled";
	daudio1_master: simple-audio-card,codec {
		/* sound-dai = <&ac108>; */
	};
};

&daudio2 {
	mclk_div 	= <0x01>;
	frametype 	= <0x00>;
	tdm_config 	= <0x01>;
	sign_extend 	= <0x00>;
	tx_data_mode 	= <0x00>;
	rx_data_mode 	= <0x00>;
	msb_lsb_first 	= <0x00>;
	pcm_lrck_period = <0x80>;
	slot_width_select = <0x20>;
	asrc_function_en  = <0x00>;
	pinctrl-names   = "default", "sleep";
	pinctrl-0       = <&daudio2_pins_a &daudio2_pins_b &daudio2_pins_c>;
	pinctrl-1       = <&daudio2_pins_d>;
	pinctrl_used	= <0x1>;
	daudio_type	= <0x0>;
	status = "disabled";
};

&sounddaudio2 {
	status = "disabled";
	daudio2_master: simple-audio-card,codec {
		/* sound-dai = <&ac108>; */
	};
};

&spdif {
	pinctrl-names   = "default","sleep";
	pinctrl-0       = <&spdif_pins_a>;
	pinctrl-1       = <&spdif_pins_b>;
	status = "disabled";
};

&soundspdif {
	status = "disabled";
};

/*
 *usb_port_type: usb mode. 0-device, 1-host, 2-otg.
 *usb_detect_type: usb hotplug detect mode. 0-none, 1-vbus/id detect, 2-id/dpdm detect.
 *usb_detect_mode: 0-thread scan, 1-id gpio interrupt.
 *usb_id_gpio: gpio for id detect.
 *usb_det_vbus_gpio: gpio for id detect. gpio or "axp_ctrl";
 *usb_wakeup_suspend：0-SUPER_STANDBY, 1-USB_STANDBY.
 */
&usbc0 {
	device_type = "usbc0";
	usb_port_type = <0x2>;
	usb_detect_type = <0x1>;
	usb_detect_mode = <0>;
	usb_id_gpio = <&pio PB 8 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	usb_det_vbus_gpio = <&pio PB 9 GPIO_ACTIVE_LOW>;
	usb_wakeup_suspend = <0>;
	usb_serial_unique = <0>;
	usb_serial_number = "20080411";
	rndis_wceis = <1>;
	status = "okay";
};

&ehci0 {
	drvvbus-supply = <&reg_usb1_vbus>;
};

&ohci0 {
	drvvbus-supply = <&reg_usb1_vbus>;
};

&usbc1 {
	device_type = "usbc1";
    usb_port_type = <0x01>;
    sb_detect_type = <0x1>;	
	usb_regulator_io = "nocare";
	usb_wakeup_suspend = <0>;
	status = "okay";
};

&ehci1 {
	status = "okay";
};

&ohci1 {
	status = "okay";
};

&twi0 {
	clock-frequency = <400000>;
	pinctrl-0 = <&twi0_pins_a>;
	pinctrl-1 = <&twi0_pins_b>;
	pinctrl-names = "default", "sleep";
	status = "disabled";

	eeprom@50 {
		compatible = "atmel,24c16";
		reg = <0x50>;
		status = "disabled";
	};
};

&twi1 {
	clock-frequency = <400000>;
	pinctrl-0 = <&twi1_pins_a>;
	pinctrl-1 = <&twi1_pins_b>;
	pinctrl-names = "default", "sleep";
	status = "disabled";
};

&twi2 {
	clock-frequency = <400000>;
	pinctrl-0 = <&twi2_pins_a>;
	pinctrl-1 = <&twi2_pins_b>;
	pinctrl-names = "default", "sleep";
	dmas = <&dma 45>, <&dma 45>;
	dma-names = "tx", "rx";
	status = "okay";

	/* pcf8574-usage:
	 * only use gpio0~7, 0 means PP0.
	 * pin set:
	 * gpios = <&pcf8574 0 GPIO_ACTIVE_LOW>;
	 * interrupt set:
	 * interrupt-parent = <&pcf8574>;
	 * interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
	 */
	/*pcf8574: gpio@38 {
		compatible = "nxp,pcf8574";
		reg = <0x38>;
		gpio_base = <2020>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
		interrupt-parent = <&pio>;
		interrupts = <PB 2 IRQ_TYPE_EDGE_FALLING>;
		status = "disabled";
	};
	*/
	
	ctp@38 {
                compatible = "focaltech,fts";
                reg = <0x38>;
                status = "okay";
				interrupt-parent = <&pio>;
				interrupts = <PB 3 IRQ_TYPE_LEVEL_LOW>;
				focaltech,reset-gpio = <&pio PB 2 GPIO_ACTIVE_HIGH>;
				focaltech,irq-gpio = <&pio PB 3 IRQ_TYPE_LEVEL_LOW>;
				focaltech,max-touch-number = <2>;
				focaltech,display-coords = <0 0 800 480>;
				focaltech,reg_vdd = <&reg_pio3_3>;
				focaltech,reg_avdd = <&reg_pio3_3>;
	};
};

&twi3 {
	clock-frequency = <400000>;
	pinctrl-0 = <&twi3_pins_a>;
	pinctrl-1 = <&twi3_pins_b>;
	pinctrl-names = "default", "sleep";
	status = "disabled";
};
/*
&gmac0 {
	phy-mode = "rmii";
	use_ephy25m = <0>;
	pinctrl-0 = <&gmac_pins_a>;
	pinctrl-1 = <&gmac_pins_b>;
	pinctrl-names = "default", "sleep";
	phy-rst = <&pio PE 10 GPIO_ACTIVE_HIGH>;
	status = "okay";
};*/

&spi0 {
	clock-frequency = <100000000>;
	pinctrl-0 = <&spi0_pins_a &spi0_pins_b>;
	pinctrl-1 = <&spi0_pins_c>;
	pinctrl-names = "default", "sleep";
	/*spi-supply = <&reg_dcdc1>;*/
	spi_slave_mode = <0>;
	spi0_cs_number = <1>;
    spi0_cs_bitmap = <1>;
	status = "okay";

	spi-nand@0 {
		compatible = "spi-nand";
		spi-max-frequency=<100000000>;
		reg = <0x0>;
		spi-rx-bus-width=<0x04>;
		spi-tx-bus-width=<0x04>;
		status="okay";
	};

	spi-nor@0 {
		compatible = "jedec,spi-nor";
		spi-max-frequency=<30000000>;
		reg = <0x0>;
		spi-rx-bus-width=<0x01>;
		spi-tx-bus-width=<0x01>;
		status="disabled";
	};
};

&spi1 {
	clock-frequency = <100000000>;
	pinctrl-0 = <&spi1_pins_a &spi1_pins_b>;
	pinctrl-1 = <&spi1_pins_c>;
	pinctrl-names = "default", "sleep";
	spi_slave_mode = <0>;
	status = "disabled";

	spi_board1@0 {
		device_type = "spi_board1";
		compatible = "rohm,dh2228fv";
		spi-max-frequency = <0x5f5e100>;
		reg = <0x0>;
		spi-rx-bus-width = <0x4>;
		spi-tx-bus-width = <0x4>;
		status = "disabled";
	};
};

&ledc {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&ledc_pins_a>;
	pinctrl-1 = <&ledc_pins_b>;
	led_count = <3>;
	output_mode = "GRB";
	reset_ns = <84>;
	t1h_ns = <800>;
	t1l_ns = <320>;
	t0h_ns = <300>;
	t0l_ns = <800>;
	wait_time0_ns = <84>;
	wait_time1_ns = <84>;
	wait_data_time_ns = <600000>;
	status	= "okay";
};

&keyboard0 {
	key0 = <210 0x160>;
	wakeup-source;
	status = "disabled";
};

/*----------------------------------------------------------------------------------
disp init configuration

disp_mode             (0:screen0<screen0,fb0>)
screenx_output_type   (0:none; 1:lcd; 2:tv; 3:hdmi;5:vdpo)
screenx_output_mode   (used for hdmi output, 0:480i 1:576i 2:480p 3:576p 4:720p50)
                      (5:720p60 6:1080i50 7:1080i60 8:1080p24 9:1080p50 10:1080p60)
screenx_output_format (for hdmi, 0:RGB 1:yuv444 2:yuv422 3:yuv420)
screenx_output_bits   (for hdmi, 0:8bit 1:10bit 2:12bit 2:16bit)
screenx_output_eotf   (for hdmi, 0:reserve 4:SDR 16:HDR10 18:HLG)
screenx_output_cs     (for hdmi, 0:undefined  257:BT709 260:BT601  263:BT2020)
screenx_output_dvi_hdmi (for hdmi, 0:undefined 1:dvi mode 2:hdmi mode)
screen0_output_range   (for hdmi, 0:default 1:full 2:limited)
screen0_output_scan    (for hdmi, 0:no data 1:overscan 2:underscan)
screen0_output_aspect_ratio  (for hdmi, 8-same as original picture 9-4:3 10-16:9 11-14:9)
fbx format            (4:RGB655 5:RGB565 6:RGB556 7:ARGB1555 8:RGBA5551 9:RGB888 10:ARGB8888 12:ARGB4444)
fbx pixel sequence    (0:ARGB 1:BGRA 2:ABGR 3:RGBA)
fb0_scaler_mode_enable(scaler mode enable, used FE)
fbx_width,fbx_height  (framebuffer horizontal/vertical pixels, fix to output resolution while equal 0)
lcdx_backlight        (lcd init backlight,the range:[0,256],default:197
lcdx_yy               (lcd init screen bright/contrast/saturation/hue, value:0~100, default:50/50/57/50)
lcd0_contrast         (LCD contrast, 0~100)
lcd0_saturation       (LCD saturation, 0~100)
lcd0_hue              (LCD hue, 0~100)
framebuffer software rotation setting:
disp_rotation_used:   (0:disable; 1:enable,you must set fbX_width to lcd_y,
set fbX_height to lcd_x)
degreeX:              (X:screen index; 0:0 degree; 1:90 degree; 3:270 degree)
degreeX_Y:            (X:screen index; Y:layer index 0~15; 0:0 degree; 1:90 degree; 3:270 degree)
devX_output_type : config output type in bootGUI framework in UBOOT-2018.
				   (0:none; 1:lcd; 2:tv; 4:hdmi;)
devX_output_mode : config output resolution(see include/video/sunxi_display2.h) of bootGUI framework in UBOOT-2018
devX_screen_id   : config display index of bootGUI framework in UBOOT-2018
devX_do_hpd      : whether do hpd detectation or not in UBOOT-2018
chn_cfg_mode     : Hardware DE channel allocation config. 0:single display with 6
				   channel, 1:dual display with 4 channel in main display and 2 channel in second
                   display, 2:dual display with 3 channel in main display and 3 channel in second
                   in display.
----------------------------------------------------------------------------------*/
&disp {
	disp_init_enable         = <1>;
	disp_mode                = <0>;

	screen0_output_type      = <1>;
	screen0_output_mode      = <4>;

	screen1_output_type      = <3>;
	screen1_output_mode      = <4>;
	
	screen1_output_format    = <0>;
	screen1_output_bits      = <0>;
	screen1_output_eotf      = <4>;
	screen1_output_cs        = <257>;
	screen1_output_dvi_hdmi  = <2>;
	screen1_output_range     = <2>;
	screen1_output_scan      = <0>;
	screen1_output_aspect_ratio = <8>;
	dev0_output_type         = <1>;
	dev0_output_mode         = <4>;
	dev0_screen_id           = <0>;
	dev0_do_hpd              = <0>;

	dev1_output_type         = <4>;
	dev1_output_mode         = <10>;
	dev1_screen_id           = <1>;
	dev1_do_hpd              = <1>;

	def_output_dev           = <0>;
	hdmi_mode_check          = <1>;
	disp_rotation_used		 = <1>;
	degree0					 = <0>;
	fb0_format               = <0>;
	fb0_buffer_num           = <1>;	
	/*fb0_width                = <800>;*/
	/*fb0_height               = <480>;*/  /*read from lcd*/
	fb1_format               = <0>;
	fb1_width                = <0>;
	fb1_height               = <0>;
	chn_cfg_mode             = <1>;

	disp_para_zone           = <1>;
	/*VCC-LCD*/
/*	dc1sw-supply = <&reg_dc1sw>;*/
	/*VCC-DSI*/
/*	eldo3-supply = <&reg_eldo3>;*/
	/*VCC-PD*/
/*	dcdc1-supply = <&reg_dcdc1>;*/
};

/*----------------------------------------------------------------------------------
;lcd0 configuration

;lcd_if:               0:hv(sync+de); 1:8080; 2:ttl; 3:lvds; 4:dsi; 5:edp; 6:extend dsi
;lcd_hv_if             0:Parallel RGB; 8:Serial RGB; 10:Dummy RGB; 11: RGB Dummy;12:CCIR656
;lcd_hv_clk_phase      0:0 degree;1:90 degree;2:180 degree;3:270 degree
;lcd_hv_sync_polarity  0:vs low,hs low; 1:vs high,hslow; 2:vs low,hs high; 3:vs high,hs high
;lcd_hv_syuv_seq       0:YUYV; 1:YVYU; 2:UYVY; 3:VYUY
;lcd_cpu_if            0:18bit/1 cycle parallel(RGB666); 4:16bit/1cycle parallel (RGB565)
;                      6:18bit/3 cycle parallel(RGB666); 7:16bit/2cycle parallel (RGB565)
;lcd_cpu_te            0:frame auto trigger; 1:frame triggered by te rising edge; 2:frame triggered by te falling edge;
;lcd_dsi_if            0:video mode; 1: Command mode; 2:video burst mode
;lcd_dsi_te            0:frame auto trigger; 1:frame triggered by te rising edge; 2:frame triggered by te falling edge;
;lcd_x:                lcd horizontal resolution
;lcd_y:                lcd vertical resolution
;lcd_width:            width of lcd in mm
;lcd_height:           height of lcd in mm
;lcd_dclk_freq:        in MHZ unit
;lcd_pwm_freq:         in HZ unit
;lcd_pwm_pol:          lcd backlight PWM polarity
;lcd_pwm_max_limit     lcd backlight PWM max limit(<=255)
;lcd_hbp:              hsync back porch(pixel) + hsync plus width(pixel);
;lcd_ht:               hsync total cycle(pixel)
;lcd_vbp:              vsync back porch(line) + vysnc plus width(line)
;lcd_vt:               vysnc total cycle(line)
;lcd_hspw:             hsync plus width(pixel)
;lcd_vspw:             vysnc plus width(pixel)
;lcd_lvds_if:          0:single link;  1:dual link
;lcd_lvds_colordepth:  0:8bit; 1:6bit
;lcd_lvds_mode:        0:NS mode; 1:JEIDA mode
;lcd_frm:              0:disable; 1:enable rgb666 dither; 2:enable rgb656 dither
;lcd_io_phase:         0:noraml; 1:intert phase(0~3bit: vsync phase; 4~7bit:hsync phase;
;                      8~11bit:dclk phase; 12~15bit:de phase)
;lcd_gamma_en          lcd gamma correction enable
;lcd_bright_curve_en   lcd bright curve correction enable
;lcd_cmap_en           lcd color map function enable
;deu_mode              0:smoll lcd screen; 1:large lcd screen(larger than 10inch)
;lcdgamma4iep:         Smart Backlight parameter, lcd gamma vale * 10;
;                      decrease it while lcd is not bright enough; increase while lcd is too bright
;smart_color           90:normal lcd screen 65:retina lcd screen(9.7inch)
;Pin setting for special function ie.LVDS, RGB data or vsync
;   name(donot care) = port:PD12<pin function><pull up or pull down><drive ability><output level>
;Pin setting for gpio:
;   lcd_gpio_X     = port:PD12<pin function><pull up or pull down><drive ability><output level>
;Pin setting for backlight enable pin
;   lcd_bl_en     = port:PD12<pin function><pull up or pull down><drive ability><output level>
;fsync setting, pulse to csi
;lcd_fsync_en          (0:disable fsync,1:enable)
;lcd_fsync_act_time    (active time of fsync, unit:pixel)
;lcd_fsync_dis_time    (disactive time of fsync, unit:pixel)
;lcd_fsync_pol         (0:positive;1:negative)
;gpio config: <&pio for cpu or &r_pio for cpus, port, port num, pio function,
pull up or pull down(default 0), driver level(default 1), data>
;For dual link lvds: use lvds2link_pins_a  and lvds2link_pins_b instead
;For rgb24: use rgb24_pins_a  and rgb24_pins_b instead
;For lvds1: use lvds1_pins_a  and lvds1_pins_b instead
;For lvds0: use lvds0_pins_a  and lvds0_pins_b instead
;----------------------------------------------------------------------------------*/
&lcd0 {
	// 800 * 480 RGB LCD 
	lcd_used            = <1>;

	lcd_driver_name     = "default_lcd";
	lcd_backlight       = <50>;
	lcd_if              = <0>;

	lcd_x               = <800>;
	lcd_y               = <480>;
	lcd_width           = <108>;
	lcd_height          = <65>;
	lcd_dclk_freq       = <24>;

	lcd_pwm_used        = <1>;
	lcd_pwm_ch          = <9>;
	lcd_pwm_freq        = <50000>;
	lcd_pwm_pol         = <0>;

	lcd_hbp             = <12>;
	lcd_ht              = <816>;
	lcd_hspw            = <4>;
	lcd_vbp             = <12>;
	lcd_vt              = <496>;
	lcd_vspw            = <4>;

	lcd_lvds_if         = <0>;
	lcd_lvds_colordepth = <1>;
	lcd_lvds_mode       = <0>;
	lcd_frm             = <0>;
	lcd_io_phase        = <0x0000>;
	lcd_gamma_en        = <0>;
	lcd_bright_curve_en = <0>;
	lcd_cmap_en         = <0>;

	deu_mode            = <0>;
	lcdgamma4iep        = <22>;
	smart_color         = <90>;

	pinctrl-0 = <&rgb18_pins_a>;
	pinctrl-1 = <&rgb18_pins_b>;

};

&pwm0 {
	pinctrl-names = "active", "sleep";
	pinctrl-0 = <&pwm0_pin_a>;
	pinctrl-1 = <&pwm0_pin_b>;
	status = "okay";
};

&pwm2 {
	pinctrl-names = "active", "sleep";
	pinctrl-0 = <&pwm2_pin_a>;
	pinctrl-1 = <&pwm2_pin_b>;
	status = "okay";
};


&pwm7 {
	pinctrl-names = "active", "sleep";
	pinctrl-0 = <&pwm7_pin_a>;
	pinctrl-1 = <&pwm7_pin_b>;
	status = "okay";
};

&rtp {
	allwinner,tp-sensitive-adjust = <0xf>;
	allwinner,filter-type = <0x1>;
	allwinner,ts-attached;
	status = "disabled";
};

&tpadc {
	key_cnt = <5>;
	key1 = <420 115>;
	key2 = <870 114>;
	key3 = <1290 119>;
	key4 = <1630 373>;
	key5 = <1950 28>;
	status = "disabled";
};

&gpadc {
	channel_num = <1>;
	channel_select = <0x01>;
	channel_data_select = <0>;
	channel_compare_select = <0x01>;
	channel_cld_select = <0x01>;
	channel_chd_select = <0>;
	channel0_compare_lowdata = <1600000>;
	channel0_compare_higdata = <1200000>;
	channel1_compare_lowdata = <460000>;
	channel1_compare_higdata = <1200000>;
	key_cnt = <5>;
	key0_vol = <210>;
	key0_val = <0x19c>;
	key1_vol = <410>;
	key1_val = <0x197>;
	key2_vol = <590>;
	key2_val = <158>;
	key3_vol = <750>;
	key3_val = <28>;
	key4_vol = <880>;
	key4_val = <28>;
	status = "okay";
	wakeup-source;
};

&s_cir0 {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&s_cir0_pins_a>;
	pinctrl-1 = <&s_cir0_pins_b>;
	ir_protocol_used		= <0>;
	ir_addr_code0			= <0x0>;
	status = "okay";
};

&ir1 {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&ir1_pins_a>;
	pinctrl-1 = <&ir1_pins_b>;
	status = "disabled";
};

&vind0 {
	csi_top = <378000000>;
	csi_isp = <327000000>;
	status = "okay"; /* enable twi and ver1 spi-nand max freq 30M */

	actuator0: actuator@5809450 {
		device_type = "actuator0";
		actuator0_name = "ad5820_act";
		actuator0_slave = <0x18>;
		actuator0_af_pwdn = <>;
		actuator0_afvdd = "afvcc-csi";
		actuator0_afvdd_vol = <2800000>;
		status = "okay";
	};

	flash0: flash@5809460 {
		device_type = "flash0";
		flash0_type = <2>;
		flash0_en = <>;
		flash0_mode = <>;
		flash0_flvdd = "";
		flash0_flvdd_vol = <>;
		device_id = <0>;
		status = "okay";
	};
	
	sensor0: sensor@5809470 {
		reg = <0x0 0x05809470 0x0 0x10>;
		device_type = "sensor0";
		compatible = "allwinner,sunxi-sensor";
		sensor0_mname = "ov5640";
		sensor0_twi_cci_id = <2>;
		sensor0_twi_addr = <0x78>;
		sensor0_mclk_id = <0>;
		sensor0_pos = "rear";
		sensor0_isp_used = <0>;
		sensor0_fmt = <0>;
		sensor0_stby_mode = <0>;
		sensor0_vflip = <0>;
		sensor0_hflip = <0>;
		sensor0_iovdd-supply = <>;
		sensor0_iovdd_vol = <>;
		sensor0_avdd-supply = <>;
		sensor0_avdd_vol = <>;
		sensor0_dvdd-supply = <>;
		sensor0_dvdd_vol = <>;
		sensor0_power_en = <>;
		sensor0_reset = <>;
		sensor0_pwdn = <>;
		sensor0_sm_vs = <>;
		flash_handle = <&flash0>;
		act_handle = <&actuator0>;
		device_id = <0>;
		status  = "okay";
	};


	sensor1:sensor@5809480 {
		device_type = "sensor1";
		sensor1_mname = "ov5640";
		compatible = "allwinner,sunxi-sensor";
		sensor1_twi_cci_id = <1>;
		sensor1_twi_addr = <0x6c>;
		sensor1_mclk_id = <1>;
		sensor1_pos = "front";
		sensor1_isp_used = <0>;
		sensor1_fmt = <0>;
		sensor1_stby_mode = <0>;
		sensor1_vflip = <0>;
		sensor1_hflip = <0>;
		sensor1_iovdd-supply = <>;
		sensor1_iovdd_vol = <>;
		sensor1_avdd-supply = <>;
		sensor1_avdd_vol = <>;
		sensor1_dvdd-supply = <>;
		sensor1_dvdd_vol = <>;
		sensor1_power_en = <>;
		sensor1_reset = <&pio PE 7 GPIO_ACTIVE_LOW>;
		sensor1_pwdn = <&pio PE 6 GPIO_ACTIVE_LOW>;
		status	= "disabled";
	};

	vinc0:vinc@5809000 {
		vinc0_csi_sel = <0>;
		vinc0_mipi_sel = <0xff>;
		vinc0_isp_sel = <0>;
		vinc0_isp_tx_ch = <0>;
		vinc0_tdm_rx_sel = <0xff>;
		vinc0_rear_sensor_sel = <0>;
		vinc0_front_sensor_sel = <0>;
		vinc0_sensor_list = <0>;
		status = "okay";
	};
	vinc1:vinc@5809200 {
		vinc1_csi_sel = <0>;
		vinc1_mipi_sel = <0xff>;
		vinc1_isp_sel = <0>;
		vinc1_isp_tx_ch = <1>;
		vinc1_tdm_rx_sel = <0xff>;
		vinc1_rear_sensor_sel = <0>;
		vinc1_front_sensor_sel = <0>;
		vinc1_sensor_list = <0>;
		status = "okay";
	};
};

sun8iw20p1.dtsi

/*
 * Allwinner Technology CO., Ltd. sun8iw20p1 platform
 *
 * modify base on juno.dts
 */
 /* optee used 7MB: SHM 2M: OS: 1M: TA:4M*/
/memreserve/ 0x41B00000 0x00100000;

#include <dt-bindings/clock/sun8iw20-ccu.h>
#include <dt-bindings/clock/sun8iw20-r-ccu.h>
#include <dt-bindings/clock/sun8iw20-rtc.h>
#include <dt-bindings/reset/sun8iw20-ccu.h>
#include <dt-bindings/reset/sun8iw20-r-ccu.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/gpio/sun4i-gpio.h>
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/power/r528-power.h>

/ {
	model = "sun8iw20";
	compatible = "allwinner,sun8iw20p1";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		serial3 = &uart3;
		serial4 = &uart4;
		serial5 = &uart5;
		spi0 = &spi0;
		spi1 = &spi1;
		twi0 = &twi0;
		twi1 = &twi1;
		twi2 = &twi2;
		twi3 = &twi3;
		mmc0 = &sdc0;
		mmc2 = &sdc2;
		pwm = &pwm;
		pwm0 = &pwm0;
		pwm1 = &pwm1;
		pwm2 = &pwm2;
		pwm3 = &pwm3;
		pwm4 = &pwm4;
		pwm5 = &pwm5;
		pwm6 = &pwm6;
		pwm7 = &pwm7;
		ir0 = &s_cir0;
		ve0 = &ve;
		tv0 = &tv0;
		tvd = &tvd;
		tvd0 = &tvd0;
		share_space0 = &share_space0;
	};

	chosen {
		bootargs = "earlyprintk=sunxi-uart,0x2500000 loglevel=8 initcall_debug=0 console=ttyS0 init=/init";
		//bootargs = "loglevel=8 initcall_debug=0 console=ttyS0 init=/init";
		linux,initrd-start = <0x0 0x0>;
		linux,initrd-end = <0x0 0x0>;
	};

	firmware {
		optee {
			compatible = "linaro,optee-tz";
			method = "smc";
		};
	};

	cpus {
		enable-method = "allwinner,sun8iw20p1";
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7","arm,armv7";
			reg = <0x0>;
			enable-method = "psci";
			clocks = <&ccu CLK_CPUX>;
			dynamic-power-coefficient = <156>;
			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
			operating-points-v2 = <&cpu_opp_table>;
			#cooling-cells = <2>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a7","arm,armv7";
			reg = <0x1>;
			enable-method = "psci";
			clocks = <&ccu CLK_CPUX>;
			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
			operating-points-v2 = <&cpu_opp_table>;
			#cooling-cells = <2>;
		};

		idle-states {
			entry-method = "arm,psci";

			CPU_SLEEP: cpu-sleep {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x0010000>;
				entry-latency-us = <46>;
				exit-latency-us = <59>;
				min-residency-us = <3570>;
				local-timer-stop;
			};

			CLUSTER_SLEEP: cluster-sleep {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x1010000>;
				entry-latency-us = <47>;
				exit-latency-us = <74>;
				min-residency-us = <5000>;
				local-timer-stop;
			};
		};

	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	dump_reg: dump_reg@20000 {
		compatible = "allwinner,sunxi-dump-reg";
		reg = <0x0 0x00020000 0x0 0x0004>;
		/* 0x00020000: dump_reg test addr, 0x0004: dump_reg test size */
	};

	cpu_opp_table: cpu-opp-table {
		compatible = "allwinner,sun50i-operating-points";
		nvmem-cells = <&speedbin_efuse>, <&cpubin_efuse>;
		nvmem-cell-names = "speed", "bin";
		opp-shared;

		opp@480000000 {
			opp-hz = /bits/ 64 <480000000>;
			clock-latency-ns = <244144>; /* 8 32k periods */
			opp-microvolt-a0 = <900000>;
			opp-microvolt-a1 = <900000>;
			opp-microvolt-a2 = <900000>;

			opp-microvolt-b0 = <950000>;
			opp-supported-hw = <0x3>;
		};

		opp@720000000 {
			opp-hz = /bits/ 64 <720000000>;
			clock-latency-ns = <244144>; /* 8 32k periods */
			opp-microvolt-a0 = <900000>;
			opp-microvolt-a1 = <900000>;
			opp-microvolt-a2 = <900000>;

			opp-microvolt-b0 = <950000>;
			opp-supported-hw = <0x3>;
		};

		opp@912000000 {
			opp-hz = /bits/ 64 <912000000>;
			clock-latency-ns = <244144>; /* 8 32k periods */
			opp-microvolt-a0 = <950000>;
			opp-microvolt-a1 = <900000>;
			opp-microvolt-a2 = <900000>;

			opp-microvolt-b0 = <950000>;
			opp-supported-hw = <0x3>;
		};

		opp@1008000000 {
			opp-hz = /bits/ 64 <1008000000>;
			clock-latency-ns = <244144>; /* 8 32k periods */
			opp-microvolt-a0 = <1000000>;
			opp-microvolt-a1 = <900000>;
			opp-microvolt-a2 = <900000>;

			opp-microvolt-b0 = <950000>;
			opp-supported-hw = <0x3>;
		};

		opp@1104000000 {
			opp-hz = /bits/ 64 <1104000000>;
			clock-latency-ns = <244144>; /* 8 32k periods */
			opp-microvolt-a0 = <1050000>;
			opp-microvolt-a1 = <950000>;
			opp-microvolt-a2 = <950000>;

			opp-microvolt-b0 = <950000>;
			opp-supported-hw = <0x3>;
		};

		opp@1200000000 {
			opp-hz = /bits/ 64 <1200000000>;
			clock-latency-ns = <244144>; /* 8 32k periods */
			opp-microvolt-a0 = <1100000>;
			opp-microvolt-a1 = <1000000>;
			opp-microvolt-a2 = <1000000>;

			opp-supported-hw = <0x1>;
		};
	};


	dcxo24M: dcxo24M_clk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <24000000>;
		clock-output-names = "dcxo24M";
	};

	rc_16m: rc16m_clk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <16000000>;
		clock-accuracy = <300000000>;
		clock-output-names = "rc-16m";
	};

	ext_32k: ext32k_clk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <32768>;
		clock-output-names = "ext-32k";
	};

	dram: dram {
		compatible = "allwinner,dram";
		clocks = <&ccu CLK_PLL_DDR0>;
		clock-names = "pll_ddr";
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0x00000000 0x40000000 0x00000000 0x20000000>;
	};

	share_space0: share_space@42100000 {
		#address-cells = <1>;
		#size-cells = <1>;
		deice_tpye = "share_space0";
		/* dsp write addr and len */
		/* arm write addr and len */
		/* dsp log addr and len */
		/* reserve */
		reg = <	0x42100000 0x00001000
			0x42101000 0x00001000
			0x42102000 0x0000E000
			0x00000000 0x00000000>;
	};

	gic: interrupt-controller@3020000 {
		compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
		#interrupt-cells = <3>;
		#address-cells = <0>;
		device_type = "gic";
		interrupt-controller;
		reg = <0x0 0x03021000 0 0x1000>, /* GIC Dist */
		      <0x0 0x03022000 0 0x2000>, /* GIC CPU */
		      <0x0 0x03024000 0 0x2000>, /* GIC VCPU Control */
		      <0x0 0x03026000 0 0x2000>; /* GIC VCPU */
		interrupts = <GIC_PPI 9 0xf04>; /* GIC Maintenence IRQ */
	};

	timer_arch {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
		clock-frequency = <24000000>;
		arm,cpu-registers-not-fw-configured;
		interrupt-parent = <&gic>;
		arm,no-tick-in-suspend;
	};

	pmu {
		compatible = "arm,cortex-a7-pmu";
		interrupts = <GIC_SPI 172 4>,
			     <GIC_SPI 173 4>;
	};

	power: power-management@ff000000 {
		compatible = "allwinner,r528-pmu", "syscon", "simple-mfd";
		reg = <0x0 0x07001000 0x0 0x400>;

		pd: power-controller {
			compatible = "allwinner,r528-power-controller";
			clocks = <&r_ccu CLK_R_PPU>;
			clock-names = "ppu";
			resets = <&r_ccu RST_R_PPU>;
			reset-names = "ppu_rst";
			#power-domain-cells = <1>;
			#address-cells = <1>;
			#size-cells = <0>;

			/* These power domains are grouped by VD_SYS */
			pd_ve@R528_PD_VE {
				reg = <R528_PD_VE>;
			};
		};
	};

	mmu_aw: iommu@2010000 {
		compatible = "allwinner,sunxi-iommu";
		reg = <0x0 0x02010000 0x0 0x1000>;
		interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "iommu-irq";
		clocks = <&ccu CLK_BUS_IOMMU>;
		clock-names = "iommu";
		#iommu-cells = <2>;
		status = "okay";
	};

	reg_pio1_8: pio-18 {
		compatible = "regulator-fixed";
		regulator-name = "pio-18";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
	};

	reg_pio3_3: pio-33 {
		compatible = "regulator-fixed";
		regulator-name = "pio-33";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	thermal-zones {
		cpu_thermal_zone: cpu_thermal_zone {
			polling-delay-passive = <500>;
			polling-delay = <1000>;
			thermal-sensors = <&ths 0>;
			sustainable-power = <589>;

			cpu_trips: trips {
				cpu_threshold: trip-point@0 {
					temperature = <70000>;
					type = "passive";
					hysteresis = <0>;
				};
				cpu_target: trip-point@1 {
					temperature = <90000>;
					type = "passive";
					hysteresis = <0>;
				};
				cpu_crit: cpu_crit@0 {
					temperature = <110000>;
					type = "critical";
					hysteresis = <0>;
				};
			};

			cooling-maps {
				map0 {
					trip = <&cpu_target>;
					cooling-device = <&cpu0
					THERMAL_NO_LIMIT
					THERMAL_NO_LIMIT>;
					contribution = <1024>;
				};
			};
		};
	};

	soc: soc@3000000 {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		device_type = "soc";

		sram_ctrl: sram_ctrl@3000000 {
			compatible = "allwinner,sram_ctrl";
			reg = <0x0 0x3000000 0 0x16C>;
			soc_ver {
				offset = <0x24>;
				mask = <0x7>;
				shift = <0>;
				ver_a = <0x18590000>;
				ver_b = <0x18590002>;
				ver_d = <0x18590003>;
			};

			soc_id {
				offset = <0x200>;
				mask = <0x1>;
				shift = <22>;
			};

			soc_bin {
				offset = <0x0>;
				mask = <0x3ff>;
				shift = <0x0>;
			};

		};

		rtc_ccu: rtc_ccu@7090000 {
			compatible = "allwinner,sun8iw20-rtc-ccu";
			device_type = "rtc-ccu";
			reg = <0x0 0x07090000 0x0 0x320>;  /* The same as rtc */
			#clock-cells = <1>;
		};

		ccu: ccu@2001000 {
			compatible = "allwinner,sun8iw20-ccu";
			reg = <0x0 0x02001000 0x0 0x1000>;
			clocks = <&dcxo24M>, <&rtc_ccu CLK_OSC32K>, <&rtc_ccu CLK_IOSC>;
			clock-names = "hosc", "losc", "iosc";
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		r_ccu: r_ccu@7010000 {
			compatible = "allwinner,sun8iw20-r-ccu";
			reg = <0x0 0x07010000 0x0 0x240>;
			clocks = <&dcxo24M>, <&rtc_ccu CLK_OSC32K>, <&rtc_ccu CLK_IOSC>,
				 <&ccu CLK_PLL_PERIPH0>;
			clock-names = "hosc", "losc", "iosc", "pll-periph0";
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		rtc: rtc@7090000 {
			compatible = "allwinner,sun8iw20-rtc";
			device_type = "rtc";
			wakeup-source;
			reg = <0x0 0x07090000 0x0 0x320>;
			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&r_ccu CLK_R_AHB_BUS_RTC>, <&rtc_ccu CLK_RTC_1K>, <&rtc_ccu CLK_RTC_SPI>;
			clock-names = "r-ahb-rtc", "rtc-1k", "rtc-spi";
			resets = <&r_ccu RST_R_AHB_BUS_RTC>;
			gpr_cur_pos = <6>;
		};

		dma:dma-controller@3002000 {
			compatible = "allwinner,sun8iw20-dma";
			reg = <0x0 0x03002000 0x0 0x1000>;
			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
			clock-names = "bus", "mbus";
			dma-channels = <8>;
			dma-requests = <48>;
			resets = <&ccu RST_BUS_DMA>;
			#dma-cells = <1>;
		};

		soc_timer0: timer@2050000 {
			compatible = "allwinner,sun4i-a10-timer";
			device_type = "soc_timer";
			reg = <0x0 0x02050000 0x0 0xA0>;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&dcxo24M>;
		};

		wdt: watchdog@20500A0 {
			compatible = "allwinner,sun6i-a31-wdt";
			reg = <0x0 0x020500A0 0x0 0x20>;  /* In Timers Spec */
			interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;  /* In GIC Spec */
		};

		mbus0: mbus-controller@3102000 {
			compatible = "allwinner,sun8i-mbus";
			reg = <0x0 0x03102000 0x0 0x1000>;  /* In SDRAM Controller Spec: DRAMC Common Register */
			#mbus-cells = <1>;
		};

		pio: pinctrl@2000000 {
			compatible = "allwinner,sun8iw20-pinctrl";
			reg = <0x0 0x02000000 0x0 0x500>;
			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,  /* AW1859_GIC_Spec: GPIOB: 101-32=69 */
				     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
			device_type = "pio";
			clocks = <&ccu CLK_APB0>, <&dcxo24M>, <&rtc_ccu CLK_OSC32K>;
			clock-names = "apb", "hosc", "losc";
			gpio-controller;
			#gpio-cells = <3>;
			interrupt-controller;
			#interrupt-cells = <3>;
			#size-cells = <0>;
			vcc-pf-supply = <&reg_pio1_8>;
			vcc-pfo-supply = <&reg_pio3_3>;

			test_pins_a: test_pins@0 {
				allwinner,pins = "PB0", "PB1";
				allwinner,function = "test";
				allwinner,muxsel = <0x9>;
				allwinner,drive = <1>;
				allwinner,pull = <1>;
			};
			test_pins_b: test_pins@1 {
				pins = "PB0", "PB1";
				function = "io_disabled";
				allwinner,muxsel = <0xF>;
				allwinner,drive = <1>;
				allwinner,pull = <1>;
			};

			csi_mclk0_pins_a: csi_mclk0@0 {
				pins = "PE3";
				function = "csi0";
				drive-strength = <10>;
			};
			csi_mclk0_pins_b: csi_mclk0@1 {
				pins = "PE3";
				function = "gpio_in";
			};
			csi0_pins_a: csi0@0 {
				pins = "PE2", "PE0", "PE1", "PE4", "PE5",
						 "PE6", "PE7", "PE8", "PE9", "PE10", "PE11";
				function = "ncsi0";
				drive-strength = <10>;
			};
			csi0_pins_b: csi0@1 {
				pins = "PE2", "PE0", "PE1", "PE4", "PE5",
						 "PE6", "PE7", "PE8", "PE9", "PE10", "PE11";
				function = "io_disabled";
				drive-strength = <10>;
			};

			lvds0_pins_a: lvds0@0 {
				pins  = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9";
				function = "lvds0";
				drive-strength = <30>;
				bias-disable;
			};

			lvds0_pins_b: lvds0@1 {
				pins  = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9";
				function = "io_disabled";
				drive-strength = <30>;
				bias-disable;
			};

			rgb24_pins_a: rgb24@0 {
				pins = "PB2", "PB3", "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", \
					"PB4", "PB5", "PD6", "PD7", "PD8", "PD9", "PD10", "PD11", \
					"PB6", "PB7", "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", \
					"PD18", "PD19", "PD20", "PD21";
				function = "lcd0";
				drive-strength = <30>;
				bias-disable;
			};

			rgb24_pins_b: rgb24@1 {
				pins = "PB2", "PB3", "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", \
					"PB4", "PB5", "PD6", "PD7", "PD8", "PD9", "PD10", "PD11", \
					"PB6", "PB7", "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", \
					"PD18", "PD19", "PD20", "PD21";
				function = "io_disabled";
				bias-disable;
			};

			rgb18_pins_a: rgb18@0 {
				pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", \
					"PD6", "PD7", "PD8", "PD9", "PD10", "PD11", \
					"PD12", "PD13", "PD14", "PD15", "PD16", "PD17", \
					"PD18", "PD19", "PD20", "PD21";
				function = "lcd0";
				drive-strength = <30>;
				bias-disable;
			};

			rgb18_pins_b: rgb18@1 {
				pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", \
					"PD6", "PD7", "PD8", "PD9", "PD10", "PD11", \
					"PD12", "PD13", "PD14", "PD15", "PD16", "PD17", \
					"PD18", "PD19", "PD20", "PD21";
				function = "io_disabled";
				bias-disable;
			};

			dsi2lane_pins_a: dsi2lane@0 {
				pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5";
				function = "dsi";
				drive-strength = <30>;
				bias-disable;
			};

			dsi2lane_pins_b: dsi2lane@1 {
				pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5";
				function = "io_disabled";
				bias-disable;
			};

			dsi4lane_pins_a: dsi4lane@0 {
				pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9";
				function = "dsi";
				drive-strength = <30>;
				bias-disable;
			};

			dsi4lane_pins_b: dsi4lane@1 {
				pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9";
				function = "io_disabled";
				bias-disable;
			};

		};

		pinctrl_test: pinctrl_test@0 {
			reg = <0x0 0x0 0x0 0x0>;
			compatible = "allwinner,sunxi-pinctrl-test";
			device_type = "pinctrl-test";
			/* For pin state selecting test */
			pinctrl-0 = <&test_pins_a>;
			pinctrl-1 = <&test_pins_b>;
			pinctrl-names = "default", "sleep";
			/* For pin basic_function/irq test */
			test-gpios = <&pio PB 0 GPIO_ACTIVE_LOW>;
			interrupt-parent = <&pio>;
			interrupts = <PB 1 IRQ_TYPE_LEVEL_HIGH>;
		};

		uart0: uart@2500000 {
			compatible = "allwinner,sun8i-uart";
			device_type = "uart0";
			reg = <0x0 0x02500000 0x0 0x400>;
			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
			sunxi,uart-fifosize = <64>;
			clocks = <&ccu CLK_BUS_UART0>;
			clock-names = "uart0";
			resets = <&ccu RST_BUS_UART0>;
			uart0_port = <0>;
			uart0_type = <2>;
			status = "disabled";
		};

		uart1: uart@2500400 {
			compatible = "allwinner,sun8i-uart";
			device_type = "uart1";
			reg = <0x0 0x02500400 0x0 0x400>;
			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
			sunxi,uart-fifosize = <256>;
			clocks = <&ccu CLK_BUS_UART1>;
			clock-names = "uart1";
			resets = <&ccu RST_BUS_UART1>;
			uart1_port = <1>;
			uart1_type = <4>;
			status = "okay";
		};

		uart2: uart@2500800 {
			compatible = "allwinner,sun8i-uart";
			device_type = "uart2";
			reg = <0x0 0x02500800 0x0 0x400>;
			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
			sunxi,uart-fifosize = <256>;
			clocks = <&ccu CLK_BUS_UART2>;
			clock-names = "uart2";
			resets = <&ccu RST_BUS_UART2>;
			uart2_port = <2>;
			uart2_type = <4>;
			status = "disabled";
		};

		uart3: uart@2500c00 {
			compatible = "allwinner,sun8i-uart";
			device_type = "uart3";
			reg = <0x0 0x02500c00 0x0 0x400>;
			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
			sunxi,uart-fifosize = <256>;
			clocks = <&ccu CLK_BUS_UART3>;
			clock-names = "uart3";
			resets = <&ccu RST_BUS_UART3>;
			uart3_port = <3>;
			uart3_type = <4>;
			status = "disabled";
		};

		uart4: uart@2501000 {
			compatible = "allwinner,sun8i-uart";
			device_type = "uart4";
			reg = <0x0 0x02501000 0x0 0x400>;
			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
			sunxi,uart-fifosize = <256>;
			clocks = <&ccu CLK_BUS_UART4>;
			clock-names = "uart4";
			resets = <&ccu RST_BUS_UART4>;
			uart4_port = <4>;
			uart4_type = <2>;
			status = "disabled";
		};

		uart5: uart@2501400 {
			compatible = "allwinner,sun8i-uart";
			device_type = "uart5";
			reg = <0x0 0x02501400 0x0 0x400>;
			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
			sunxi,uart-fifosize = <256>;
			clocks = <&ccu CLK_BUS_UART5>;
			clock-names = "uart5";
			resets = <&ccu RST_BUS_UART5>;
			uart5_port = <5>;
			uart5_type = <2>;
			status = "disabled";
		};
		cryptoengine: ce@03040000 {
			compatible = "allwinner,sunxi-ce";
			device_name = "ce";
			reg = <0x0 0x03040000 0x0 0xa0>, /* non-secure space */
			      <0x0 0x03040800 0x0 0xa0>; /* secure space */
			interrupts = <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>, /*non-secure*/
				   <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>; /* secure*/
			clock-frequency = <400000000>; /* 400MHz */
			clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>, <&ccu CLK_MBUS_CE>,
					<&ccu CLK_PLL_PERIPH0_2X>;
			clock-names = "bus_ce", "ce_clk", "mbus_ce", "pll_periph0_2x";
			resets = <&ccu RST_BUS_CE>;
			status = "okay";
		};

		gmac0: eth@4500000 {
			compatible = "allwinner,sunxi-gmac";
			reg = <0x0 0x04500000 0x0 0x10000>,
			      <0x0 0x03000030 0x0 0x4>;
			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "gmacirq";
			clocks = <&ccu CLK_BUS_EMAC0>, <&ccu CLK_EMAC0_25M>;
			clock-names = "gmac", "ephy";
			resets = <&ccu RST_BUS_EMAC0>;
			device_type = "gmac0";
			gmac-power0;
			gmac-power1;
			gmac-power2;
			status = "disabled";
		};

		sdc2: sdmmc@4022000 {
			compatible = "allwinner,sunxi-mmc-v4p6x";
			device_type = "sdc2";
			reg = <0x0 0x04022000 0x0 0x1000>;
			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&dcxo24M>,
				 <&ccu CLK_PLL_PERIPH0_2X>,
				 <&ccu CLK_MMC2>,
				 <&ccu CLK_BUS_MMC2>;
			clock-names = "osc24m","pll_periph","mmc","ahb";
			resets = <&ccu RST_BUS_MMC2>;
			reset-names = "rst";
			pinctrl-names = "default","sleep";
			pinctrl-0 = <&sdc2_pins_a>;
			pinctrl-1 = <&sdc2_pins_b>;
			bus-width = <4>;
			req-page-count = <2>;
			cap-mmc-highspeed;
			cap-cmd23;
			mmc-cache-ctrl;
			non-removable;
			/*max-frequency = <200000000>;*/
			max-frequency = <50000000>;
			cap-erase;
			mmc-high-capacity-erase-size;
			no-sdio;
			no-sd;
			/*-- speed mode --*/
			/*sm0: DS26_SDR12*/
			/*sm1: HSSDR52_SDR25*/
			/*sm2: HSDDR52_DDR50*/
			/*sm3: HS200_SDR104*/
			/*sm4: HS400*/
			/*-- frequency point --*/
			/*f0: CLK_400K*/
			/*f1: CLK_25M*/
			/*f2: CLK_50M*/
			/*f3: CLK_100M*/
			/*f4: CLK_150M*/
			/*f5: CLK_200M*/

			sdc_tm4_sm0_freq0 = <0>;
			sdc_tm4_sm0_freq1 = <0>;
			sdc_tm4_sm1_freq0 = <0x00000000>;
			sdc_tm4_sm1_freq1 = <0>;
			sdc_tm4_sm2_freq0 = <0x00000000>;
			sdc_tm4_sm2_freq1 = <0>;
			sdc_tm4_sm3_freq0 = <0x05000000>;
			sdc_tm4_sm3_freq1 = <0x00000005>;
			sdc_tm4_sm4_freq0 = <0x00050000>;
			sdc_tm4_sm4_freq1 = <0x00000004>;
			sdc_tm4_sm4_freq0_cmd = <0>;
			sdc_tm4_sm4_freq1_cmd = <0>;

			/*vmmc-supply = <&reg_3p3v>;*/
			/*vqmc-supply = <&reg_3p3v>;*/
			/*vdmc-supply = <&reg_3p3v>;*/
			/*vmmc = "vcc-card";*/
			/*vqmc = "";*/
			/*vdmc = "";*/
			/*sunxi-power-save-mode;*/
		};

		sdc0: sdmmc@4020000 {
			compatible = "allwinner,sunxi-mmc-v5p3x";
			device_type = "sdc0";
			reg = <0x0 0x04020000 0x0 0x1000>;
			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&dcxo24M>,
				 <&ccu CLK_PLL_PERIPH0_2X>,
				 <&ccu CLK_MMC0>,
				 <&ccu CLK_BUS_MMC0>;
			clock-names = "osc24m","pll_periph","mmc","ahb";
			resets = <&ccu RST_BUS_MMC0>;
			reset-names = "rst";
			pinctrl-names = "default","mmc_1v8","sleep","uart_jtag";
			pinctrl-0 = <&sdc0_pins_a>;
			pinctrl-1 = <&sdc0_pins_b>;
			pinctrl-2 = <&sdc0_pins_c>;
			pinctrl-3 = <&sdc0_pins_d &sdc0_pins_e>;
			max-frequency = <50000000>;
			bus-width = <4>;
			req-page-count = <2>;
			/*non-removable;*/
			/*broken-cd;*/
			/*cd-inverted*/
			/*cd-gpios = <&pio PF 6 GPIO_ACTIVE_LOW>;*/
			/* vmmc-supply = <&reg_3p3v>;*/
			/* vqmc-supply = <&reg_3p3v>;*/
			/* vdmc-supply = <&reg_3p3v>;*/
			/*vmmc = "vcc-card";*/
			/*vqmc = "";*/
			/*vdmc = "";*/
			cap-sd-highspeed;
			cap-wait-while-busy;
			no-sdio;
			no-mmc;
			/*sd-uhs-sdr50;*/
			/*sd-uhs-ddr50;*/
			/*cap-sdio-irq;*/
			/*keep-power-in-suspend;*/
			/*ignore-pm-notify;*/
			/*sunxi-power-save-mode;*/
			/*sunxi-dly-400k = <1 0 0 0>; */
			/*sunxi-dly-26M  = <1 0 0 0>;*/
			/*sunxi-dly-52M  = <1 0 0 0>;*/
			/*sunxi-dly-52M-ddr4  = <1 0 0 0>;*/
			/*sunxi-dly-52M-ddr8  = <1 0 0 0>;*/
			/*sunxi-dly-104M  = <1 0 0 0>;*/
			/*sunxi-dly-208M  = <1 0 0 0>;*/
			/*sunxi-dly-104M-ddr  = <1 0 0 0>;*/
			/*sunxi-dly-208M-ddr  = <1 0 0 0>;*/
		};

		sdc1: sdmmc@4021000 {
			compatible = "allwinner,sunxi-mmc-v5p3x";
			device_type = "sdc1";
			reg = <0x0 0x04021000 0x0 0x1000>;
			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&dcxo24M>,
				 <&ccu CLK_PLL_PERIPH0_2X>,
				 <&ccu CLK_MMC1>,
				 <&ccu CLK_BUS_MMC1>;
			clock-names = "osc24m","pll_periph","mmc","ahb";
			resets = <&ccu RST_BUS_MMC1>;
			reset-names = "rst";
			pinctrl-names = "default","sleep";
			pinctrl-0 = <&sdc1_pins_a>;
			pinctrl-1 = <&sdc1_pins_b>;
			max-frequency = <50000000>;
			bus-width = <4>;
			/*broken-cd;*/
			/*cd-inverted*/
			/*cd-gpios = <&pio PG 6 6 1 2 0>;*/
			/* vmmc-supply = <&reg_3p3v>;*/
			/* vqmc-supply = <&reg_3p3v>;*/
			/* vdmc-supply = <&reg_3p3v>;*/
			/*vmmc = "vcc-card";*/
			/*vqmc = "";*/
			/*vdmc = "";*/
			cap-sd-highspeed;
			no-mmc;
			/*sd-uhs-sdr50;*/
			/*sd-uhs-ddr50;*/
			/*sd-uhs-sdr104;*/
			/*cap-sdio-irq;*/
			keep-power-in-suspend;
			/*ignore-pm-notify;*/
			/*sunxi-power-save-mode;*/
			/*sunxi-dly-400k = <1 0 0 0 0>; */
			/*sunxi-dly-26M  = <1 0 0 0 0>;*/
			/*sunxi-dly-52M  = <1 0 0 0 0>;*/
			sunxi-dly-52M-ddr4  = <1 0 0 0 2>;
			/*sunxi-dly-52M-ddr8  = <1 0 0 0 0>;*/
			sunxi-dly-104M  = <1 0 0 0 1>;
			/*sunxi-dly-208M  = <1 1 0 0 0>;*/
			sunxi-dly-208M  = <1 0 0 0 1>;
			/*sunxi-dly-104M-ddr  = <1 0 0 0 0>;*/
			/*sunxi-dly-208M-ddr  = <1 0 0 0 0>;*/

			status = "okay";
		};

		tpadc: tpadc@2009c00 {
			compatible = "allwinner,tp_key";
			reg = <0x0 0x02009c00 0x0 0x400>;
			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_TPADC>, <&ccu CLK_BUS_TPADC>;
			clock-names = "mod", "bus";
			clock-frequency = <1000000>;
			resets = <&ccu RST_BUS_TPADC>;
			status = "disabled";
		};

		rtp:rtp@2009c00 {
			compatible = "allwinner,sun8i-ts";
			reg = <0x0 0x02009c00 0x0 0x400>;
			clocks = <&ccu CLK_TPADC>, <&ccu CLK_BUS_TPADC>;
			clock-names = "mod", "bus";
			clock-frequency = <1000000>;
			resets = <&ccu RST_BUS_TPADC>;
			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
		};

		spi0: spi@4025000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sun8i-spi";
			device_type = "spi0";
			reg = <0x0 0x04025000 0x0 0x1000>;
			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_PLL_PERIPH0>, <&ccu CLK_SPI0>, <&ccu CLK_BUS_SPI0>;
			clock-names = "pll", "mod", "bus";
			resets = <&ccu RST_BUS_SPI0>;
			clock-frequency = <100000000>;
			spi0_cs_number = <1>;
			spi0_cs_bitmap = <1>;
			dmas = <&dma 22>, <&dma 22>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		spi1: spi@4026000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sun8i-spi";
			device_type = "spi1";
			reg = <0x0 0x04026000 0x0 0x1000>;
			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_PLL_PERIPH0>, <&ccu CLK_SPI1>, <&ccu CLK_BUS_SPI1>;
			clock-names = "pll", "mod", "bus";
			resets = <&ccu RST_BUS_SPI1>;
			clock-frequency = <100000000>;
			spi1_cs_number = <1>;
			spi1_cs_bitmap = <1>;
			dmas = <&dma 23>, <&dma 23>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		ve: ve@1c0e000 {
			    compatible = "allwinner,sunxi-cedar-ve";
			    reg = <0x0 0x01c0e000 0x0 0x1000>,
				<0x0 0x03000000 0x0 0x10>,
				<0x0 0x03001000 0x0 0x1000>;
			    interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
			    clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, <&ccu CLK_MBUS_VE>;
			    clock-names = "bus_ve", "ve", "mbus_ve";
			    resets = <&ccu RST_BUS_VE>;
			    power-domains = <&pd R528_PD_VE>;
			    iommus = <&mmu_aw 0 1>;
			    status = "okay";
		};

		twi0: twi@2502000{
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sun8i-twi";
			device_type = "twi0";
			reg = <0x0 0x02502000 0x0 0x400>;
			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_I2C0>;
			resets = <&ccu RST_BUS_I2C0>;
			clock-names = "bus";
			clock-frequency = <400000>;
			status = "disabled";
		};

		twi1: twi@2502400{
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sun8i-twi";
			device_type = "twi1";
			reg = <0x0 0x02502400 0x0 0x400>;
			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_I2C1>;
			resets = <&ccu RST_BUS_I2C1>;
			clock-names = "bus";
			clock-frequency = <200000>;
			status = "disabled";
		};

		twi2: twi@2502800{
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sun8i-twi";
			device_type = "twi2";
			reg = <0x0 0x02502800 0x0 0x400>;
			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_I2C2>;
			resets = <&ccu RST_BUS_I2C2>;
			clock-names = "bus";
			clock-frequency = <100000>;
			status = "disabled";
		};

		twi3: twi@2502c00{
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sun8i-twi";
			device_type = "twi3";
			reg = <0x0 0x02502c00 0x0 0x400>;
			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_I2C3>;
			resets = <&ccu RST_BUS_I2C3>;
			clock-names = "bus";
			clock-frequency = <100000>;
			status = "disabled";
		};

		ledc: ledc@2008000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sunxi-leds";
			reg = <0x0 0x02008000 0x0 0x400>;
			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "ledcirq";
			clocks = <&ccu CLK_LEDC>, <&ccu CLK_BUS_LEDC>;
			clock-names = "clk_ledc", "clk_cpuapb";
			dmas = <&dma 42>, <&dma 42>;
			dma-names = "rx", "tx";
			resets = <&ccu RST_BUS_LEDC>;
			reset-names = "ledc_reset";
			status = "disable";
		};

		pwm: pwm@2000c00 {
			#pwm-cells = <0x3>;
			compatible = "allwinner,sunxi-pwm";
			reg = <0x0 0x02000c00 0x0 0x400>;
			clocks = <&ccu CLK_BUS_PWM>;
			resets = <&ccu RST_BUS_PWM>;
			pwm-number = <8>;
			pwm-base = <0x0>;
			sunxi-pwms = <&pwm0>, <&pwm1>, <&pwm2>, <&pwm3>, <&pwm4>,
				<&pwm5>, <&pwm6>, <&pwm7>;
		};

		pwm0: pwm0@2000c10 {
			compatible = "allwinner,sunxi-pwm0";
			pinctrl-names = "active", "sleep";
			reg = <0x0 0x02000c10 0x0 0x4>;
			reg_base = <0x02000c00>;
		};

		pwm1: pwm1@2000c11 {
			compatible = "allwinner,sunxi-pwm1";
			pinctrl-names = "active", "sleep";
			reg = <0x0 0x02000c11 0x0 0x4>;
			reg_base = <0x02000c00>;
		};

		pwm2: pwm2@2000c12 {
			compatible = "allwinner,sunxi-pwm2";
			pinctrl-names = "active", "sleep";
			reg = <0x0 0x02000c12 0x0 0x4>;
			reg_base = <0x02000c00>;
		};

		pwm3: pwm3@2000c13 {
			compatible = "allwinner,sunxi-pwm3";
			pinctrl-names = "active", "sleep";
			reg = <0x0 0x02000c13 0x0 0x4>;
			reg_base = <0x02000c00>;
		};

		pwm4: pwm4@2000c14 {
			compatible = "allwinner,sunxi-pwm4";
			pinctrl-names = "active", "sleep";
			reg = <0x0 0x02000c14 0x0 0x4>;
			reg_base = <0x02000c00>;
		};

		pwm5: pwm5@2000c15 {
			compatible = "allwinner,sunxi-pwm5";
			pinctrl-names = "active", "sleep";
			reg = <0x0 0x02000c15 0x0 0x4>;
			reg_base = <0x02000c00>;
		};

		pwm6: pwm6@2000c16 {
			compatible = "allwinner,sunxi-pwm6";
			pinctrl-names = "active", "sleep";
			reg = <0x0 0x02000c16 0x0 0x4>;
			reg_base = <0x02000c00>;
		};

		pwm7: pwm7@2000c17 {
			compatible = "allwinner,sunxi-pwm7";
			pinctrl-names = "active", "sleep";
			reg = <0x0 0x02000c17 0x0 0x4>;
			reg_base = <0x02000c00>;
		};

		lcd_fb0: lcd_fb0@0 {
			compatible = "allwinner,sunxi-lcd_fb0";
			pinctrl-names = "active","sleep";

			status = "okay";
		};

		keyboard0: keyboard@2009800 {
			compatible = "allwinner,keyboard_1350mv";
			reg = <0x0 0x02009800 0x0 0x400>;
			interrupts = <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>;
			clocks = <&ccu CLK_BUS_LRADC>;
			clock-names = "mclk";
			resets = <&ccu RST_BUS_LRADC>;
			key_cnt = <5>;
			key0 = <210 115>;
			key1 = <410 114>;
			key2 = <590 139>;
			key3 = <750 28>;
			key4 = <880 172>;
			wakeup-source;
			status = "okay";
		};

		sid@3006000 {
			compatible = "allwinner,sun8iw20p1-sid", "allwinner,sunxi-sid";
			reg = <0x0 0x03006000 0 0x1000>;
			#address-cells = <1>;
			#size-cells = <1>;

			secure_status {
				reg = <0x0 0>;
				offset = <0xa0>;
				size = <0x4>;
			};

			chipid {
				reg = <0x0 0>;
				offset = <0x200>;
				size = <0x10>;
			};

			rotpk {
				reg = <0x0 0>;
				offset = <0x140>;
				size = <0x4>;
			};

			speedbin_efuse: speedbin@00 {
				reg = <0x00 4>;
			};

			cpubin_efuse: cpubin@28 {
				reg = <0x28 4>;
			};

			ths_calib: calib@14 {
				reg = <0x14 8>;
			};
		};

		gpadc: gpadc@2009000 {
			compatible = "allwinner,sunxi-gpadc";
			reg = <0x0 0x02009000 0x0 0x400>;
			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_GPADC>;
			clock-names = "bus";
			resets = <&ccu RST_BUS_GPADC>;
			status = "okay";
		};

		vind0: vind@5800800 {
			compatible = "allwinner,sunxi-vin-media", "simple-bus";
			#address-cells = <2>;
			#size-cells = <2>;
			ranges;
			device_id = <0>;
			csi_top = <336000000>;
			csi_isp = <327000000>;
			reg = <0x0 0x05800800 0x0 0x200>,
				<0x0 0x05800000 0x0 0x800>;
			clocks = <&ccu CLK_CSI_TOP>, <&ccu CLK_PLL_VIDEO1_2X>,
				<&ccu CLK_CSI0_MCLK>, <&dcxo24M>, <&ccu CLK_PLL_VIDEO1>,
				<&ccu CLK_BUS_CSI>, <&ccu CLK_MBUS_CSI>;
			clock-names = "csi_top", "csi_top_src",
					"csi_mclk0", "csi_mclk0_24m", "csi_mclk0_pll",
					"csi_bus", "csi_mbus";
			resets = <&ccu RST_BUS_CSI>;
			reset-names = "csi_ret";
			pinctrl-names = "mclk0-default", "mclk0-sleep";
			pinctrl-0 = <&csi_mclk0_pins_a>;
			pinctrl-1 = <&csi_mclk0_pins_b>;
			status = "okay";

			csi0: csi@5801000{
				compatible = "allwinner,sunxi-csi";
				reg = <0x0 0x05801000 0x0 0x1000>;
				interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
				pinctrl-names = "default","sleep";
				pinctrl-0 = <&csi0_pins_a>;
				pinctrl-1 = <&csi0_pins_b>;
				device_id = <0>;
				iommus = <&mmu_aw 1 1>;
				status = "okay";
			};
			isp0: isp@5809410 {
				compatible = "allwinner,sunxi-isp";
				reg = <0x0 0x05809410 0x0 0x10>;
				device_id = <0xfe>;

				status = "okay";
			};
			isp1: isp@5809420 {
				compatible = "allwinner,sunxi-isp";
				reg = <0x0 0x05809420 0x0 0x10>;
				device_id = <0xff>;
				status = "okay";
			};
			scaler0: scaler@5809430 {
				compatible = "allwinner,sunxi-scaler";
				reg = <0x0 0x05809430 0x0 0x10>;
				device_id = <0xfe>;
				status = "okay";
			};
			scaler1: scaler@5809440 {
				compatible = "allwinner,sunxi-scaler";
				reg = <0x0 0x05809440 0x0 0x10>;
				device_id = <0xff>;
				status = "okay";
			};
			actuator0: actuator@5809450 {
				compatible = "allwinner,sunxi-actuator";
				device_type = "actuator0";
				reg = <0x0 0x05809450 0x0 0x10>;
				actuator0_name = "ad5820_act";
				actuator0_slave = <0x18>;
				actuator0_af_pwdn = <>;
				actuator0_afvdd = "afvcc-csi";
				actuator0_afvdd_vol = <2800000>;
				status = "disabled";
			};
			flash0: flash@5809460 {
				device_type = "flash0";
				compatible = "allwinner,sunxi-flash";
				reg = <0x0 0x05809460 0x0 0x10>;
				flash0_type = <2>;
				flash0_en = <>;
				flash0_mode = <>;
				flash0_flvdd = "";
				flash0_flvdd_vol = <>;
				device_id = <0>;
				status = "disabled";
			};
			sensor0: sensor@5809470 {
				reg = <0x0 0x05809470 0x0 0x10>;
				device_type = "sensor0";
				compatible = "allwinner,sunxi-sensor";
				sensor0_mname = "ov5640";
				sensor0_twi_cci_id = <2>;
				sensor0_twi_addr = <0x78>;
				sensor0_mclk_id = <0>;
				sensor0_pos = "rear";
				sensor0_isp_used = <0>;
				sensor0_fmt = <0>;
				sensor0_stby_mode = <0>;
				sensor0_vflip = <0>;
				sensor0_hflip = <0>;
				sensor0_iovdd-supply = <>;
				sensor0_iovdd_vol = <>;
				sensor0_avdd-supply = <>;
				sensor0_avdd_vol = <>;
				sensor0_dvdd-supply = <>;
				sensor0_dvdd_vol = <>;
				sensor0_power_en = <>;
				sensor0_reset = <&pio PE 9 GPIO_ACTIVE_LOW>;
				sensor0_pwdn = <&pio PE 8 GPIO_ACTIVE_LOW>;
				sensor0_sm_vs = <>;
				flash_handle = <&flash0>;
				act_handle = <&actuator0>;
				device_id = <0>;
				status	= "disabled";
			};
			sensor1: sensor@5809480 {
				reg = <0x0 0x05809480 0x0 0x10>;
				device_type = "sensor1";
				compatible = "allwinner,sunxi-sensor";
				sensor1_mname = "ov5647";
				sensor1_twi_cci_id = <3>;
				sensor1_twi_addr = <0x6c>;
				sensor1_mclk_id = <1>;
				sensor1_pos = "front";
				sensor1_isp_used = <0>;
				sensor1_fmt = <0>;
				sensor1_stby_mode = <0>;
				sensor1_vflip = <0>;
				sensor1_hflip = <0>;
				sensor1_iovdd-supply = <>;
				sensor1_iovdd_vol = <>;
				sensor1_avdd-supply = <>;
				sensor1_avdd_vol = <>;
				sensor1_dvdd-supply = <>;
				sensor1_dvdd_vol = <>;
				sensor1_power_en = <>;
				sensor1_reset = <&pio PE 7 GPIO_ACTIVE_LOW>;
				sensor1_pwdn = <&pio PE 6 GPIO_ACTIVE_LOW>;
				sensor1_sm_vs = <>;
				flash_handle = <>;
				act_handle = <>;
				device_id = <1>;
				status	= "disabled";
			};
			vinc0: vinc@5809000 {
				compatible = "allwinner,sunxi-vin-core";
				device_type = "vinc0";
				reg = <0x0 0x05809000 0x0 0x200>;
				interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
				vinc0_csi_sel = <0>;
				vinc0_mipi_sel = <0xff>;
				vinc0_isp_sel = <0>;
				vinc0_tdm_rx_sel = <0xff>;
				vinc0_rear_sensor_sel = <0>;
				vinc0_front_sensor_sel = <0>;
				vinc0_sensor_list = <0>;
				device_id = <0>;
				iommus = <&mmu_aw 1 1>;
				status = "okay";
			};
			vinc1: vinc@5809200 {
				device_type = "vinc1";
				compatible = "allwinner,sunxi-vin-core";
				reg = <0x0 0x05809200 0x0 0x200>;
				interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
				vinc1_csi_sel = <0>;
				vinc1_mipi_sel = <0xff>;
				vinc1_isp_sel = <1>;
				vinc1_tdm_rx_sel = <0xff>;
				vinc1_rear_sensor_sel = <0>;
				vinc1_front_sensor_sel = <0>;
				vinc1_sensor_list = <0>;
				device_id = <1>;
				iommus = <&mmu_aw 1 1>;
				status = "okay";
			};

		};
		s_cir0: s_cir@7040000 {
			compatible = "allwinner,s_cir";
			reg = <0x0 0x07040000 0x0 0x400>;
			interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&r_ccu CLK_R_APB0_BUS_IRRX>, <&dcxo24M>, <&r_ccu CLK_R_APB0_IRRX>;
			clock-names = "bus", "pclk", "mclk";
			resets = <&r_ccu RST_R_APB0_BUS_IRRX>;
			status = "disabled";
		};

		ir1: ir@2003000 {
			compatible = "allwinner,irtx";
			reg = <0x0 0x02003000 0x0 0x400>;
			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_IR_TX>, <&dcxo24M>, <&ccu CLK_IR_TX>;
			clock-names = "bus", "pclk", "mclk";
			resets = <&ccu RST_BUS_IR_TX>;
			status = "disabled";
		};

		di: deinterlace@5400000 {
			compatible = "allwinner,sunxi-deinterlace";
			reg = <0x0 0x05400000 0x0 0x0000ffff>;
			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_DI>,
				 <&ccu CLK_BUS_DI>,
				 <&ccu CLK_PLL_PERIPH0_2X>;
			clock-names = "clk_di",
				      "pll_periph",
				      "clk_bus_di";
			resets = <&ccu RST_BUS_DI>;
			reset-names = "rst_bus_di";

			assigned-clocks = <&ccu CLK_DI>;
			assigned-clock-parents = <&ccu CLK_PLL_PERIPH0_2X>;
			assigned-clock-rates = <300000000>;

			iommus = <&mmu_aw 4 1>;
			status = "okay";
		};

		g2d: g2d@5410000 {
			compatible = "allwinner,sunxi-g2d";
			reg = <0x0 0x05410000 0x0 0x3ffff>;
			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_G2D>, <&ccu CLK_G2D>, <&ccu CLK_MBUS_G2D>;
			clock-names = "bus", "g2d", "mbus_g2d";
			resets = <&ccu RST_BUS_G2D>;
			iommus = <&mmu_aw 3 1>;
			status = "okay";
		};

		disp: disp@5000000 {
			compatible = "allwinner,sunxi-disp";
			reg = <0x0 0x05000000 0x0 0x3fffff>,	/* de0 */
			      <0x0 0x05460000 0x0 0xfff>,	/*display_if_top*/
			      <0x0 0x05461000 0x0 0xfff>,	/* tcon-lcd0 */
			      <0x0 0x05470000 0x0 0xfff>,	/* tcon-tv */
			      <0x0 0x05450000 0x0 0x1fff>;	/* dsi0*/
			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,/*tcon-lcd0*/
				     <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,/*tcon-tv */
				     <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;/*dsi*/
			clocks = <&ccu CLK_DE0>,
				 <&ccu CLK_DE0>,
				 <&ccu CLK_BUS_DE0>,
				 <&ccu CLK_BUS_DE0>,
				 <&ccu CLK_BUS_DPSS_TOP0>,
				 <&ccu CLK_BUS_DPSS_TOP0>,
				 <&ccu CLK_MIPI_DSI>,
				 <&ccu CLK_BUS_MIPI_DSI>,
				 <&ccu CLK_TCON_LCD0>,
				 <&ccu CLK_TCON_TV>,
				 <&ccu CLK_BUS_TCON_LCD0>,
				 <&ccu CLK_BUS_TCON_TV>,
				 <&ccu CLK_MIPI_DSI>,
				 <&ccu CLK_BUS_MIPI_DSI>;
			clock-names = "clk_de0",
					"clk_de1",
					"clk_bus_de0",
					"clk_bus_de1",
					"clk_bus_dpss_top0",
					"clk_bus_dpss_top1",
					"clk_mipi_dsi0",
					"clk_bus_mipi_dsi0",
					"clk_tcon0",
					"clk_tcon1",/*tcon-tv actually*/
					"clk_bus_tcon0",
					"clk_bus_tcon1",/*tcon-tv actually*/
					"clk_mipi_dsi0",
					"clk_bus_mipi_dsi0";
			resets = <&ccu RST_BUS_DE0>,
				 <&ccu RST_BUS_DE0>,
				 <&ccu RST_BUS_DPSS_TOP0>,
				 <&ccu RST_BUS_DPSS_TOP0>,
				 <&ccu RST_BUS_MIPI_DSI>,
				 <&ccu RST_BUS_TCON_LCD0>,
				 <&ccu RST_BUS_TCON_TV>,
				 <&ccu RST_BUS_LVDS0>;
			reset-names = "rst_bus_de0",
					"rst_bus_de1",
					"rst_bus_dpss_top0",
					"rst_bus_dpss_top1",
					"rst_bus_mipi_dsi0",
					"rst_bus_tcon0",
					"rst_bus_tcon1",
					"rst_bus_lvds0";

			assigned-clocks = <&ccu CLK_DE0>,
			<&ccu CLK_MIPI_DSI>,
			<&ccu CLK_TCON_LCD0>,
			<&ccu CLK_TCON_TV>;
			assigned-clock-parents = <&ccu CLK_PLL_PERIPH0_2X>,
			<&ccu CLK_PLL_PERIPH0>,
			<&ccu CLK_PLL_VIDEO0_4X>,
			<&ccu CLK_PLL_VIDEO1_4X>;
			assigned-clock-rates = <300000000>,
			<150000000>,
			<0>,
			<0>;

			boot_disp = <0>;
			boot_disp1 = <0>;
			boot_disp2 = <0>;
			fb_base = <0>;
			iommus = <&mmu_aw 2 0>;
			status = "okay";
		};

		lcd0: lcd0@5461000 {
			compatible = "allwinner,sunxi-lcd0";
			reg = <0x0 0x05461000 0x0 0xfff>;
			pinctrl-names = "active","sleep";
			status = "okay";
		};

		tv0: tv0@5600000 {
			compatible = "allwinner,sunxi-tv";
			reg = <0x0 0x05600000 0x0 0x3fff>,
				<0x0 0x05604000 0x0 0x3fff>;
			clocks = <&ccu CLK_BUS_TVE_TOP>,
				 <&ccu CLK_TVE>,
				 <&ccu CLK_BUS_TVE>;
			clock-names = "clk_bus_tve_top",
				      "clk_tve",
				      "clk_bus_tve";
			resets = <&ccu RST_BUS_TVE_TOP>,
				 <&ccu RST_BUS_TVE>;
			reset-names = "rst_bus_tve_top", "rst_bus_tve";

			device_type = "tv0";
			pinctrl-names = "active","sleep";
			status = "okay";
		};

		hwspinlock: hwspinlock@0x3005000 {
			compatible = "allwinner,sunxi-hwspinlock";
			reg = <0x0 0x3005000 0x0 0x1000>;
			#hwlock-cells = <1>;
			clocks = <&ccu CLK_BUS_SPINLOCK>;
			clock-names = "clk_hwspinlock_bus";
			resets = <&ccu RST_BUS_SPINLOCK>;
			reset-names = "rst";
			num-locks = <32>;
			status = "disabled";
		};
		/* old msgbox in dts
		msgbox: msgbox@3003000 {
			compatible = "sunxi,msgbox-amp";
			reg = <0x0 0x03003000 0x0 0x1000>,
			      <0x0 0x01701000 0x0 0x1000>,
			      <0x0 0x0601f000 0x0 0x1000>;
			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_MSGBOX0>;
			rpmsg_id = "sunxi,dsp-msgbox","sunxi,dsp-power-msgbox";
			resets = <&ccu RST_BUS_MSGBOX0>;
			reset-names = "rst";
			msgbox_amp_counts = <3>;
			msgbox_amp_local = <0>;
			rpmsg_amp_remote-0 = <1>;
			rpmsg_read_channel-0 = <1>;
			rpmsg_write_channel-0 = <1>;
			rpmsg_amp_remote-1 = <1>;
			rpmsg_read_channel-1 = <0>;
			rpmsg_write_channel-1 = <0>;
		}; */
		msgbox: msgbox@3003000 {
			compatible = "allwinner,sun8iw20-msgbox";
			#mbox-cells = <1>;
			reg = <0x0 0x03003000 0x0 0x1000>,
			      <0x0 0x01701000 0x0 0x1000>,
			      <0x0 0x0601f000 0x0 0x1000>;
			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_MSGBOX0>;
			resets = <&ccu RST_BUS_MSGBOX0>;
			reset-names = "rst";
			local_id = <0>;
			status = "okay";
		};

		hdmi: hdmi@5500000 {
			compatible = "allwinner,sunxi-hdmi";
			reg = <0x0 0x05500000 0x0 0xfffff>;
			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_HDMI>,
				<&ccu CLK_HDMI_24M>,
				<&ccu CLK_HDMI_CEC>,
				<&ccu CLK_TCON_TV>;
			clock-names = "clk_bus_hdmi",
					"clk_ddc",
					"clk_cec",
					"clk_tcon_tv";
			resets = <&ccu RST_BUS_HDMI_SUB>,
				<&ccu RST_BUS_HDMI_MAIN>;
			reset-names = "rst_bus_sub",
				      "rst_bus_main";
			assigned-clocks = <&ccu CLK_HDMI_CEC>;
			assigned-clock-parents = <&ccu CLK_HDMI_CEC_32K>;
			assigned-clock-rates = <0>;
			status = "okay";
		};
		usbc0:usbc0@0 {
			device_type = "usbc0";
			compatible = "allwinner,sunxi-otg-manager";
			usb_port_type = <2>;
			usb_detect_type = <1>;
			usb_id_gpio;
			usb_det_vbus_gpio;
			usb_regulator_io = "nocare";
			usb_wakeup_suspend = <0>;
			usb_luns = <3>;
			usb_serial_unique = <0>;
			usb_serial_number = "20080411";
			rndis_wceis = <1>;
			status = "okay";
		};

		udc:udc-controller@0x04100000 {
			compatible = "allwinner,sunxi-udc";
			reg = <0x0 0x04100000 0x0 0x1000>, /*udc base*/
			      <0x0 0x00000000 0x0 0x100>; /*sram base*/
			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_OTG>;
			clock-names = "bus_otg";
			resets = <&ccu RST_BUS_OTG>, <&ccu RST_USB_PHY0>;
			reset-names = "otg", "phy";
			status = "okay";
		};

		ehci0:ehci0-controller@0x04101000 {
			compatible = "allwinner,sunxi-ehci0";
			reg = <0x0 0x04101000 0x0 0xFFF>, /*hci0 base*/
			      <0x0 0x00000000 0x0 0x100>, /*sram base*/
			      <0x0 0x04100000 0x0 0x1000>; /*otg base*/
			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_EHCI0>;
			clock-names = "bus_hci";
			resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_USB_PHY0>;
			reset-names = "hci", "phy";
			hci_ctrl_no = <0>;
			status = "okay";
		};

		ohci0:ohci0-controller@0x04101400 {
			compatible = "allwinner,sunxi-ohci0";
			reg = <0x0 0x04101400 0x0 0xFFF>, /*hci0 base*/
			      <0x0 0x00000000 0x0 0x100>, /*sram base*/
			      <0x0 0x04100000 0x0 0x1000>; /*otg base*/
			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_OHCI0>, <&ccu CLK_USB_OHCI0>;
			clock-names = "bus_hci", "ohci";
			resets = <&ccu RST_BUS_OHCI0>, <&ccu RST_USB_PHY0>;
			reset-names = "hci", "phy";
			hci_ctrl_no = <0>;
			status = "okay";
		};

		usbc1:usbc1@0 {
			device_type = "usbc1";
			usb_regulator_io = "nocare";
			usb_wakeup_suspend = <0>;
			status = "disable";
		};

		ehci1:ehci1-controller@0x04200000 {
			compatible = "allwinner,sunxi-ehci1";
			reg = <0x0 0x04200000 0x0 0xFFF>, /*ehci1 base*/
			      <0x0 0x00000000 0x0 0x100>, /*sram base*/
			      <0x0 0x04100000 0x0 0x1000>; /*otg base*/
			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_EHCI1>;
			clock-names = "bus_hci";
			resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_USB_PHY1>;
			reset-names = "hci", "phy";
			hci_ctrl_no = <1>;
			status = "disable";
		};

		ohci1:ohci1-controller@0x04200400 {
			compatible = "allwinner,sunxi-ohci1";
			reg = <0x0 0x04200400 0x0 0xFFF>, /*ohci1 base*/
			      <0x0 0x00000000 0x0 0x100>, /*sram base*/
			      <0x0 0x04100000 0x0 0x1000>; /*otg base*/
			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_OHCI1>, <&ccu CLK_USB_OHCI1>;
			clock-names = "bus_hci", "ohci";
			resets = <&ccu RST_BUS_OHCI1>, <&ccu RST_USB_PHY1>;
			reset-names = "hci", "phy";
			hci_ctrl_no = <1>;
			status = "disable";
		};

		/* codec addr: 0x02030000, the others is invalid to avoid build warining */
		codec:codec@2030000 {
			#sound-dai-cells = <0>;
			compatible = "allwinner,sunxi-internal-codec";
			reg = <0x0 0x02030000 0x0 0x34c>;
			clocks = <&ccu CLK_PLL_AUDIO0>,
				 <&ccu CLK_PLL_AUDIO1_DIV5>,
				 <&ccu CLK_AUDIO_DAC>,
				 <&ccu CLK_AUDIO_ADC>,
				 <&ccu CLK_BUS_AUDIO_CODEC>;
			clock-names = "pll_audio0", "pll_audio1_div5",
				      "audio_clk_dac", "audio_clk_adc",
				      "audio_clk_bus";
			resets = <&ccu RST_BUS_AUDIO_CODEC>;
			rx_sync_en  = <0x00>;
			device_type = "codec";
			status = "okay";
		};

		dummy_cpudai:dummy_cpudai@203034c {
			compatible = "allwinner,sunxi-dummy-cpudai";
			reg = <0x0 0x0203034c 0x0 0x4>;
			tx_fifo_size    = <128>;
			rx_fifo_size    = <256>;
			dac_txdata      = <0x02030020>;
			adc_txdata      = <0x02030040>;
			playback_cma    = <128>;
			capture_cma     = <256>;
			device_type = "cpudai";
			dmas = <&dma 7>, <&dma 7>;
			dma-names = "tx", "rx";
			status = "okay";
		};

		sndcodec:sound@2030340 {
			compatible = "allwinner,sunxi-codec-machine";
			reg = <0x0 0x02030340 0x0 0x4>;
			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
			sunxi,audio-codec = <&codec>;
			sunxi,cpudai-controller = <&dummy_cpudai>;
			device_type = "sndcodec";
			status = "okay";
		};

		sunxi_rpaf_dsp0:rpaf-dsp@203034c {
			compatible = "allwinner,rpaf-dsp0";
			device_type = "sunxi_rpaf_dsp0";
			dsp_id = <0x0>;
			status = "okay";
		};

		/* dmic addr: 0x02031000, the others is invalid to avoid build warining */
		dmic:dmic@2031000{
			#sound-dai-cells = <0>;
			compatible = "allwinner,sunxi-dmic";
			reg = <0x0 0x02031000 0x0 0x50>;
			clocks = <&ccu CLK_PLL_AUDIO0>, /* 98.304M / 90.3168M */
				 <&ccu CLK_DMIC>,
				 <&ccu CLK_BUS_DMIC>;
			clock-names = "pll_audio", "dmic", "dmic_bus";
			resets = <&ccu RST_BUS_DMIC>;
			dmas		= <&dma 8>;
			dma-names	= "rx";
			interrupts	= <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
			clk_parent	= <0x1>;
			capture_cma	= <256>;
			data_vol	= <0xB0>;
			rx_chmap	= <0x76543210>;
			rx_sync_en      = <0x00>;
			device_type = "dmic";
			status = "disabled";
		};

		dmic_codec:sound@2031050{
			#sound-dai-cells = <0>;
			compatible = "dmic-codec";
			reg = <0x0 0x02031050 0x0 0x4>;
			num-channels = <8>;
		};

		sounddmic:sounddmic@2031060 {
			reg = <0x0 0x02031060 0x0 0x4>;
			compatible = "sunxi,simple-audio-card";
			simple-audio-card,name = "snddmic";
			simple-audio-card,capture_only;
			status = "disabled";
			/* simple-audio-card,format = "i2s"; */
			simple-audio-card,cpu {
				sound-dai = <&dmic>;
			};
			simple-audio-card,codec {
				sound-dai = <&dmic_codec>;
			};
		};

		/* daudio0 addr: 0x02032000, the others is invalid to avoid build warining */
		daudio0:daudio@2032000 {
			#sound-dai-cells = <0>;
			compatible = "allwinner,sunxi-daudio";
			reg = <0x0 0x02032000 0x0 0xa0>;
			clocks = <&ccu CLK_PLL_AUDIO0>, /* 98.304M / 90.3168M */
				 <&ccu CLK_I2S0>,
				 <&ccu CLK_BUS_I2S0>;
			clock-names = "pll_audio", "i2s0", "i2s0_bus";
			resets = <&ccu RST_BUS_I2S0>;
			dmas		= <&dma 3>, <&dma 3>;
			dma-names	= "tx", "rx";
			interrupts	= <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl_used		= <0x01>;
			sign_extend		= <0x00>;
			tx_data_mode		= <0x00>;
			rx_data_mode		= <0x00>;
			msb_lsb_first		= <0x00>;
			pcm_lrck_period		= <0x80>;
			slot_width_select	= <0x20>;
			frametype		= <0x00>;
			tdm_config		= <0x01>;
			tdm_num			= <0x00>;
			mclk_div		= <0x00>;
			clk_parent		= <0x00>;
			capture_cma		= <128>;
			playback_cma		= <128>;
			tx_num			= <4>;
			tx_chmap1		= <0x76543210>;
			tx_chmap0		= <0xFEDCBA98>;
			rx_num			= <4>;
			rx_chmap3		= <0x03020100>;
			rx_chmap2		= <0x07060504>;
			rx_chmap1		= <0x0B0A0908>;
			rx_chmap0		= <0x0F0E0D0C>;
			asrc_function_en	= <0x00>;
			rx_sync_en              = <0x00>;
			device_type = "daudio0";
			status = "disabled";
		};

		sounddaudio0: sounddaudio0@20320a0 {
			reg = <0x0 0x020320a0 0x0 0x4>;
			compatible = "sunxi,simple-audio-card";
			simple-audio-card,name = "snddaudio0";
			simple-audio-card,format = "i2s";
			status = "disabled";
			/* simple-audio-card,frame-master = <&daudio0_master>; */
			/* simple-audio-card,bitclock-master = <&daudio0_master>; */
			/* simple-audio-card,bitclock-inversion; */
			/* simple-audio-card,frame-inversion; */
			simple-audio-card,cpu {
				sound-dai = <&daudio0>;
			};
		};

		/* daudio1 addr: 0x02033000, the others is invalid to avoid build warining */
		daudio1:daudio@2033000 {
			#sound-dai-cells = <0>;
			compatible = "allwinner,sunxi-daudio";
			reg = <0x0 0x02033000 0x0 0xa0>;
			clocks = <&ccu CLK_PLL_AUDIO0>, /* 98.304M / 90.3168M */
				 <&ccu CLK_I2S1>,
				 <&ccu CLK_BUS_I2S1>;
			clock-names = "pll_audio", "i2s1", "i2s1_bus";
			resets = <&ccu RST_BUS_I2S1>;
			dmas		= <&dma 4>, <&dma 4>;
			dma-names	= "tx", "rx";
			interrupts	= <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl_used		= <0x01>;
			sign_extend		= <0x00>;
			tx_data_mode		= <0x00>;
			rx_data_mode		= <0x00>;
			msb_lsb_first		= <0x00>;
			pcm_lrck_period		= <0x80>;
			slot_width_select	= <0x20>;
			frametype		= <0x00>;
			tdm_config		= <0x01>;
			tdm_num			= <0x01>;
			mclk_div		= <0x00>;
			clk_parent		= <0x00>;
			capture_cma		= <128>;
			playback_cma		= <128>;
			tx_num			= <4>;
			tx_chmap1		= <0x76543210>;
			tx_chmap0		= <0xFEDCBA98>;
			rx_num			= <4>;
			rx_chmap3		= <0x03020100>;
			rx_chmap2		= <0x07060504>;
			rx_chmap1		= <0x0B0A0908>;
			rx_chmap0		= <0x0F0E0D0C>;
			asrc_function_en	= <0x00>;
			rx_sync_en              = <0x00>;
			device_type = "daudio1";
			status = "disabled";
		};

		sounddaudio1: sounddaudio1@20330a0 {
			reg = <0x0 0x020330a0 0x0 0x4>;
			compatible = "sunxi,simple-audio-card";
			simple-audio-card,name = "snddaudio1";
			simple-audio-card,format = "i2s";
			status = "disabled";
			simple-audio-card,cpu {
				sound-dai = <&daudio1>;
			};
		};

		/* daudio2 addr: 0x02034000, the others is invalid to avoid build warining */
		daudio2:daudio@2034000 {
			#sound-dai-cells = <0>;
			compatible = "allwinner,sunxi-daudio";
			reg = <0x0 0x02034000 0x0 0xa0>;
			clocks = <&ccu CLK_PLL_AUDIO0>, /* 98.304M / 90.3168M */
				 <&ccu CLK_I2S2>,
				 <&ccu CLK_BUS_I2S2>,
				 <&ccu CLK_PLL_AUDIO0_4X>,
				 <&ccu CLK_I2S2_ASRC>;
			resets = <&ccu RST_BUS_I2S2>;
			dmas		= <&dma 5>, <&dma 5>;
			dma-names	= "tx", "rx";
			interrupts	= <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl_used		= <0x01>;
			daudio_type		= <0x00>;
			sign_extend		= <0x00>;
			tx_data_mode		= <0x00>;
			rx_data_mode		= <0x00>;
			msb_lsb_first		= <0x00>;
			pcm_lrck_period		= <0x80>;
			slot_width_select	= <0x20>;
			frametype		= <0x00>;
			tdm_config		= <0x01>;
			tdm_num			= <0x02>;
			mclk_div		= <0x01>;
			clk_parent		= <0x00>;
			capture_cma		= <128>;
			playback_cma		= <128>;
			tx_num			= <4>;
			tx_chmap1		= <0x76543210>;
			tx_chmap0		= <0xFEDCBA98>;
			rx_num			= <4>;
			rx_chmap3		= <0x03020100>;
			rx_chmap2		= <0x07060504>;
			rx_chmap1		= <0x0B0A0908>;
			rx_chmap0		= <0x0F0E0D0C>;
			asrc_function_en	= <0x00>;
			rx_sync_en              = <0x00>;
			device_type = "daudio2";
			status = "disabled";
		};

		sounddaudio2: sounddaudio2@20340a0 {
			reg = <0x0 0x020340a0 0x0 0x4>;
			compatible = "sunxi,simple-audio-card";
			simple-audio-card,name = "snddaudio2";
			simple-audio-card,format = "i2s";
			status = "disabled";
			simple-audio-card,cpu {
				sound-dai = <&daudio2>;
			};
		};

		hdmiaudio: hdmiaudio@20340a4 {
			#sound-dai-cells = <0>;
			reg = <0x0 0x020340a4 0x0 0x4>;
			compatible = "allwinner,sunxi-hdmiaudio";
			status = "disabled";
		};

		/* spdif addr: 0x02036000, the others is invalid to avoid build warining */
		spdif:spdif@2036000 {
			#sound-dai-cells = <0>;
			compatible = "allwinner,sunxi-spdif";
			reg = <0x0 0x02036000 0x0 0x58>;
			clocks = <&ccu CLK_PLL_AUDIO0_4X>,	/* 90.3168M */
				 <&ccu CLK_SPDIF_TX>,
				 <&ccu CLK_BUS_SPDIF>,
				 <&ccu CLK_PLL_AUDIO1>,         /* 98.304M */
				 <&ccu CLK_PLL_AUDIO1_DIV5>,
				 <&ccu CLK_PLL_PERIPH0>,
				 <&ccu CLK_SPDIF_RX>;
			clock-names = "pll_audio0", "spdif", "spdif_bus",
				      "pll_audio1", "pll_audio1_div5",
				      "pll_periph", "spdif_rx";
			resets = <&ccu RST_BUS_SPDIF>;
			dmas		= <&dma 2>, <&dma 2>;
			dma-names	= "tx", "rx";
			interrupts	= <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
			clk_parent	= <0x1>;
			playback_cma	= <128>;
			capture_cma	= <128>;
			rx_sync_en      = <0>;
			device_type = "spdif";
			status = "disabled";
		};

		soundspdif:soundspdif@203605c {
			reg = <0x0 0x0203605c 0x0 0x4>;
			compatible = "sunxi,simple-audio-card";
			simple-audio-card,name = "sndspdif";
			status = "disabled";
			 /* simple-audio-card,format = "i2s"; */
			 simple-audio-card,cpu {
				 sound-dai = <&spdif>;
			 };
			 simple-audio-card,codec {
				 /*snd-soc-dummy*/
			 };
		};

		ths: ths@02009400 {
			compatible = "allwinner,sun8iw20p1-ths";
			reg = <0x0 0x02009400 0x0 0x400>;
			clocks = <&ccu CLK_BUS_THS>;
			clock-names = "bus";
			resets = <&ccu RST_BUS_THS>;
			nvmem-cells = <&ths_calib>;
			nvmem-cell-names = "calibration";
			#thermal-sensor-cells = <1>;
		};

		tvd: tvd@05c00000 {
			compatible = "allwinner,sunxi-tvd";
			reg = <0x0 0x05c00000 0x0 0x00010000>;/*tvd_top*/
			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&ccu CLK_BUS_TVD_TOP>,
			<&ccu CLK_MBUS_TVIN>;
			clock-names = "clk_bus_tvd_top",
			"clk_mbus_tvd";

			resets = <&ccu RST_BUS_TVD_TOP>;
			reset-names = "rst_bus_tvd_top";

			tvd-number = <1>;
			tvds = <&tvd0>;
			status = "okay";
		};

		tvd0: tvd0@05c01000 {
			compatible = "allwinner,sunxi-tvd0";
			reg = <0x0 0x05c01000 0x0 0x00010000>;
			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&ccu CLK_TVD>,
			<&ccu CLK_BUS_TVD>;
			clock-names = "clk_tvd0","clk_bus_tvd0";

			resets = <&ccu RST_BUS_TVD>;
			reset-names = "rst_bus_tvd0";

			assigned-clocks = <&ccu CLK_TVD>;
			assigned-clock-parents = <&ccu CLK_PLL_VIDEO1>;

			tvd_used = <1>;
			tvd_if = <0>;
			status = "okay";
		};

	};
};

config-5.4

#
# Automatically generated file; DO NOT EDIT.
# Linux/arm 5.4.61 Kernel Configuration
#
CONFIG_CC_VERSION_TEXT="arm-openwrt-linux-muslgnueabi-gcc.bin (OpenWrt/Linaro GCC 6.4-2017.11 2017-11) 6.4.1"
CONFIG_CC_IS_GCC=y
CONFIG_GCC_VERSION=60401
CONFIG_CLANG_VERSION=0
CONFIG_CC_CAN_LINK=y
CONFIG_CC_HAS_ASM_GOTO=y
CONFIG_IRQ_WORK=y
CONFIG_BUILDTIME_EXTABLE_SORT=y

#
# General setup
#
CONFIG_INIT_ENV_ARG_LIMIT=32
# CONFIG_COMPILE_TEST is not set
CONFIG_LOCALVERSION=""
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_BUILD_SALT=""
CONFIG_HAVE_KERNEL_GZIP=y
CONFIG_HAVE_KERNEL_LZMA=y
CONFIG_HAVE_KERNEL_XZ=y
CONFIG_HAVE_KERNEL_LZO=y
CONFIG_HAVE_KERNEL_LZ4=y
CONFIG_KERNEL_GZIP=y
# CONFIG_KERNEL_LZMA is not set
# CONFIG_KERNEL_XZ is not set
# CONFIG_KERNEL_LZO is not set
# CONFIG_KERNEL_LZ4 is not set
CONFIG_DEFAULT_HOSTNAME="(none)"
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
# CONFIG_POSIX_MQUEUE is not set
CONFIG_CROSS_MEMORY_ATTACH=y
# CONFIG_USELIB is not set
# CONFIG_AUDIT is not set

#
# IRQ subsystem
#
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_MIGRATION=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_GENERIC_IRQ_CHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_MSI_IOMMU=y
CONFIG_HANDLE_DOMAIN_IRQ=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_SPARSE_IRQ=y
# CONFIG_GENERIC_IRQ_DEBUGFS is not set
# end of IRQ subsystem

CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
CONFIG_ARCH_CLOCKSOURCE_DATA=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_ARCH_HAS_TICK_BROADCAST=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y

#
# Timers subsystem
#
CONFIG_TICK_ONESHOT=y
CONFIG_NO_HZ_COMMON=y
# CONFIG_HZ_PERIODIC is not set
CONFIG_NO_HZ_IDLE=y
# CONFIG_NO_HZ_FULL is not set
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
# end of Timers subsystem

# CONFIG_PREEMPT_NONE is not set
# CONFIG_PREEMPT_VOLUNTARY is not set
CONFIG_PREEMPT=y
CONFIG_PREEMPT_COUNT=y
CONFIG_PREEMPTION=y

#
# CPU/Task time and stats accounting
#
CONFIG_TICK_CPU_ACCOUNTING=y
# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
# CONFIG_IRQ_TIME_ACCOUNTING is not set
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BSD_PROCESS_ACCT_V3=y
# CONFIG_TASKSTATS is not set
# CONFIG_PSI is not set
# end of CPU/Task time and stats accounting

CONFIG_CPU_ISOLATION=y

#
# RCU Subsystem
#
CONFIG_PREEMPT_RCU=y
# CONFIG_RCU_EXPERT is not set
CONFIG_SRCU=y
CONFIG_TREE_SRCU=y
CONFIG_TASKS_RCU=y
CONFIG_RCU_STALL_COMMON=y
CONFIG_RCU_NEED_SEGCBLIST=y
# end of RCU Subsystem

CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
# CONFIG_IKHEADERS is not set
CONFIG_LOG_BUF_SHIFT=20
CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13
CONFIG_GENERIC_SCHED_CLOCK=y

#
# Scheduler features
#
# end of Scheduler features

# CONFIG_CGROUPS is not set
# CONFIG_NAMESPACES is not set
# CONFIG_CHECKPOINT_RESTORE is not set
# CONFIG_SCHED_AUTOGROUP is not set
# CONFIG_SYSFS_DEPRECATED is not set
# CONFIG_RELAY is not set
# CONFIG_BLK_DEV_INITRD is not set
# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_SYSCTL=y
CONFIG_HAVE_UID16=y
CONFIG_BPF=y
CONFIG_EXPERT=y
CONFIG_UID16=y
CONFIG_MULTIUSER=y
# CONFIG_SGETMASK_SYSCALL is not set
# CONFIG_SYSFS_SYSCALL is not set
# CONFIG_SYSCTL_SYSCALL is not set
# CONFIG_FHANDLE is not set
CONFIG_POSIX_TIMERS=y
CONFIG_PRINTK=y
CONFIG_PRINTK_NMI=y
CONFIG_BUG=y
# CONFIG_ELF_CORE is not set
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_FUTEX_PI=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
# CONFIG_AIO is not set
CONFIG_IO_URING=y
CONFIG_ADVISE_SYSCALLS=y
CONFIG_MEMBARRIER=y
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_ALL is not set
CONFIG_KALLSYMS_BASE_RELATIVE=y
# CONFIG_BPF_SYSCALL is not set
# CONFIG_USERFAULTFD is not set
CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
CONFIG_RSEQ=y
# CONFIG_DEBUG_RSEQ is not set
CONFIG_EMBEDDED=y
CONFIG_HAVE_PERF_EVENTS=y
CONFIG_PERF_USE_VMALLOC=y
# CONFIG_PC104 is not set

#
# Kernel Performance Events And Counters
#
CONFIG_PERF_EVENTS=y
# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
# end of Kernel Performance Events And Counters

CONFIG_VM_EVENT_COUNTERS=y
# CONFIG_SLUB_DEBUG is not set
# CONFIG_COMPAT_BRK is not set
# CONFIG_SLAB is not set
CONFIG_SLUB=y
# CONFIG_SLOB is not set
CONFIG_SLAB_MERGE_DEFAULT=y
# CONFIG_SLAB_FREELIST_RANDOM is not set
# CONFIG_SLAB_FREELIST_HARDENED is not set
# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set
CONFIG_SLUB_CPU_PARTIAL=y
# CONFIG_PROFILING is not set
# end of General setup

CONFIG_ARM=y
CONFIG_ARM_HAS_SG_CHAIN=y
CONFIG_ARM_DMA_USE_IOMMU=y
CONFIG_ARM_DMA_IOMMU_ALIGNMENT=8
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_HAVE_PROC_CPU=y
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_ARCH_SUPPORTS_UPROBES=y
CONFIG_ARM_PATCH_PHYS_VIRT=y
CONFIG_GENERIC_BUG=y
CONFIG_PGTABLE_LEVELS=2

#
# System Type
#
CONFIG_MMU=y
CONFIG_ARCH_MMAP_RND_BITS_MIN=8
CONFIG_ARCH_MMAP_RND_BITS_MAX=16
CONFIG_ARCH_MULTIPLATFORM=y
# CONFIG_ARCH_EBSA110 is not set
# CONFIG_ARCH_EP93XX is not set
# CONFIG_ARCH_FOOTBRIDGE is not set
# CONFIG_ARCH_IOP32X is not set
# CONFIG_ARCH_IXP4XX is not set
# CONFIG_ARCH_DOVE is not set
# CONFIG_ARCH_PXA is not set
# CONFIG_ARCH_RPC is not set
# CONFIG_ARCH_SA1100 is not set
# CONFIG_ARCH_S3C24XX is not set
# CONFIG_ARCH_OMAP1 is not set

#
# Multiple platform selection
#

#
# CPU Core family selection
#
# CONFIG_ARCH_MULTI_V6 is not set
CONFIG_ARCH_MULTI_V7=y
CONFIG_ARCH_MULTI_V6_V7=y
# end of Multiple platform selection

# CONFIG_ARCH_VIRT is not set
# CONFIG_ARCH_ACTIONS is not set
# CONFIG_ARCH_ALPINE is not set
# CONFIG_ARCH_ARTPEC is not set
# CONFIG_ARCH_ASPEED is not set
# CONFIG_ARCH_AT91 is not set
# CONFIG_ARCH_BCM is not set
# CONFIG_ARCH_BERLIN is not set
# CONFIG_ARCH_DIGICOLOR is not set
# CONFIG_ARCH_EXYNOS is not set
# CONFIG_ARCH_HIGHBANK is not set
# CONFIG_ARCH_HISI is not set
# CONFIG_ARCH_MXC is not set
# CONFIG_ARCH_KEYSTONE is not set
# CONFIG_ARCH_MEDIATEK is not set
# CONFIG_ARCH_MESON is not set
# CONFIG_ARCH_MILBEAUT is not set
# CONFIG_ARCH_MMP is not set
# CONFIG_ARCH_MVEBU is not set
# CONFIG_ARCH_NPCM is not set

#
# TI OMAP/AM/DM/DRA Family
#
# CONFIG_ARCH_OMAP3 is not set
# CONFIG_ARCH_OMAP4 is not set
# CONFIG_SOC_OMAP5 is not set
# CONFIG_SOC_AM33XX is not set
# CONFIG_SOC_AM43XX is not set
# CONFIG_SOC_DRA7XX is not set
# end of TI OMAP/AM/DM/DRA Family

# CONFIG_ARCH_SIRF is not set
# CONFIG_ARCH_QCOM is not set
# CONFIG_ARCH_RDA is not set
# CONFIG_ARCH_REALVIEW is not set
# CONFIG_ARCH_ROCKCHIP is not set
# CONFIG_ARCH_S5PV210 is not set
# CONFIG_ARCH_RENESAS is not set
# CONFIG_ARCH_SOCFPGA is not set
# CONFIG_PLAT_SPEAR is not set
# CONFIG_ARCH_STI is not set
# CONFIG_ARCH_STM32 is not set
CONFIG_ARCH_SUNXI=y
# CONFIG_MACH_SUN4I is not set
# CONFIG_MACH_SUN5I is not set
# CONFIG_MACH_SUN6I is not set
# CONFIG_MACH_SUN7I is not set
# CONFIG_MACH_SUN8I is not set
# CONFIG_MACH_SUN9I is not set
CONFIG_ARCH_SUN8I=y
# CONFIG_ARCH_SUN8IW15 is not set
CONFIG_ARCH_SUN8IW20=y
# CONFIG_FPGA_V4_PLATFORM is not set
# CONFIG_FPGA_V7_PLATFORM is not set
CONFIG_EVB_PLATFORM=y
CONFIG_SUNXI_SOC_NAME="sun8iw20"
# CONFIG_ARCH_TANGO is not set
# CONFIG_ARCH_TEGRA is not set
# CONFIG_ARCH_UNIPHIER is not set
# CONFIG_ARCH_U8500 is not set
# CONFIG_ARCH_VEXPRESS is not set
# CONFIG_ARCH_WM8850 is not set
# CONFIG_ARCH_ZX is not set
# CONFIG_ARCH_ZYNQ is not set

#
# Processor Type
#
CONFIG_CPU_V7=y
CONFIG_CPU_THUMB_CAPABLE=y
CONFIG_CPU_32v6K=y
CONFIG_CPU_32v7=y
CONFIG_CPU_ABRT_EV7=y
CONFIG_CPU_PABRT_V7=y
CONFIG_CPU_CACHE_V7=y
CONFIG_CPU_CACHE_VIPT=y
CONFIG_CPU_COPY_V6=y
CONFIG_CPU_TLB_V7=y
CONFIG_CPU_HAS_ASID=y
CONFIG_CPU_CP15=y
CONFIG_CPU_CP15_MMU=y

#
# Processor Features
#
# CONFIG_ARM_LPAE is not set
CONFIG_ARM_THUMB=y
# CONFIG_ARM_THUMBEE is not set
CONFIG_ARM_VIRT_EXT=y
CONFIG_SWP_EMULATE=y
# CONFIG_CPU_ICACHE_DISABLE is not set
# CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND is not set
# CONFIG_CPU_BPREDICT_DISABLE is not set
CONFIG_CPU_SPECTRE=y
CONFIG_HARDEN_BRANCH_PREDICTOR=y
CONFIG_KUSER_HELPERS=y
# CONFIG_VDSO is not set
CONFIG_OUTER_CACHE=y
CONFIG_OUTER_CACHE_SYNC=y
CONFIG_MIGHT_HAVE_CACHE_L2X0=y
CONFIG_CACHE_L2X0=y
# CONFIG_CACHE_L2X0_PMU is not set
# CONFIG_PL310_ERRATA_588369 is not set
# CONFIG_PL310_ERRATA_727915 is not set
# CONFIG_PL310_ERRATA_753970 is not set
# CONFIG_PL310_ERRATA_769419 is not set
CONFIG_ARM_L1_CACHE_SHIFT_6=y
CONFIG_ARM_L1_CACHE_SHIFT=6
CONFIG_ARM_DMA_MEM_BUFFERABLE=y
CONFIG_ARM_HEAVY_MB=y
CONFIG_DEBUG_ALIGN_RODATA=y
# CONFIG_ARM_ERRATA_430973 is not set
CONFIG_ARM_ERRATA_643719=y
# CONFIG_ARM_ERRATA_720789 is not set
# CONFIG_ARM_ERRATA_754322 is not set
# CONFIG_ARM_ERRATA_754327 is not set
# CONFIG_ARM_ERRATA_764369 is not set
# CONFIG_ARM_ERRATA_775420 is not set
# CONFIG_ARM_ERRATA_798181 is not set
# CONFIG_ARM_ERRATA_773022 is not set
# CONFIG_ARM_ERRATA_818325_852422 is not set
# CONFIG_ARM_ERRATA_821420 is not set
# CONFIG_ARM_ERRATA_825619 is not set
# CONFIG_ARM_ERRATA_857271 is not set
# CONFIG_ARM_ERRATA_852421 is not set
# CONFIG_ARM_ERRATA_852423 is not set
# CONFIG_ARM_ERRATA_857272 is not set
# end of System Type

#
# Bus support
#
# CONFIG_ARM_ERRATA_814220 is not set
# end of Bus support

#
# Kernel Features
#
CONFIG_HAVE_SMP=y
CONFIG_SMP=y
CONFIG_SMP_ON_UP=y
CONFIG_ARM_CPU_TOPOLOGY=y
CONFIG_SCHED_MC=y
# CONFIG_SCHED_SMT is not set
CONFIG_HAVE_ARM_ARCH_TIMER=y
# CONFIG_MCPM is not set
# CONFIG_BIG_LITTLE is not set
CONFIG_VMSPLIT_3G=y
# CONFIG_VMSPLIT_3G_OPT is not set
# CONFIG_VMSPLIT_2G is not set
# CONFIG_VMSPLIT_1G is not set
CONFIG_PAGE_OFFSET=0xC0000000
CONFIG_NR_CPUS=2
CONFIG_HOTPLUG_CPU=y
CONFIG_ARM_PSCI=y
CONFIG_ARCH_NR_GPIO=416
CONFIG_HZ_FIXED=0
CONFIG_HZ_100=y
# CONFIG_HZ_200 is not set
# CONFIG_HZ_250 is not set
# CONFIG_HZ_300 is not set
# CONFIG_HZ_500 is not set
# CONFIG_HZ_1000 is not set
CONFIG_HZ=100
CONFIG_SCHED_HRTICK=y
# CONFIG_THUMB2_KERNEL is not set
CONFIG_ARM_PATCH_IDIV=y
CONFIG_AEABI=y
CONFIG_OABI_COMPAT=y
CONFIG_HAVE_ARCH_PFN_VALID=y
# CONFIG_HIGHMEM is not set
CONFIG_CPU_SW_DOMAIN_PAN=y
CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
# CONFIG_ARM_MODULE_PLTS is not set
CONFIG_FORCE_MAX_ZONEORDER=11
CONFIG_ALIGNMENT_TRAP=y
# CONFIG_UACCESS_WITH_MEMCPY is not set
# CONFIG_SECCOMP is not set
# CONFIG_PARAVIRT is not set
# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
# CONFIG_XEN is not set
# end of Kernel Features

#
# Boot options
#
CONFIG_USE_OF=y
# CONFIG_ATAGS is not set
CONFIG_ZBOOT_ROM_TEXT=0
CONFIG_ZBOOT_ROM_BSS=0
# CONFIG_ARM_APPENDED_DTB is not set
CONFIG_CMDLINE="loglevel=8 initcall_debug=1 console=ttyS0 init=/init"
# CONFIG_KEXEC is not set
# CONFIG_CRASH_DUMP is not set
CONFIG_AUTO_ZRELADDR=y
# CONFIG_EFI is not set
# end of Boot options

#
# CPU Power Management
#

#
# CPU Frequency scaling
#
# CONFIG_CPU_FREQ is not set
# end of CPU Frequency scaling

#
# CPU Idle
#
# CONFIG_CPU_IDLE is not set
# end of CPU Idle
# end of CPU Power Management

#
# Floating point emulation
#

#
# At least one emulation must be selected
#
# CONFIG_FPE_NWFPE is not set
# CONFIG_FPE_FASTFPE is not set
CONFIG_VFP=y
CONFIG_VFPv3=y
CONFIG_NEON=y
CONFIG_KERNEL_MODE_NEON=y
# end of Floating point emulation

#
# Power management options
#
CONFIG_SUSPEND=y
CONFIG_SUSPEND_FREEZER=y
# CONFIG_SUSPEND_SKIP_SYNC is not set
CONFIG_PM_SLEEP=y
CONFIG_PM_SLEEP_SMP=y
# CONFIG_PM_AUTOSLEEP is not set
CONFIG_PM_WAKELOCKS=y
CONFIG_PM_WAKELOCKS_LIMIT=100
CONFIG_PM_WAKELOCKS_GC=y
CONFIG_PM=y
CONFIG_PM_DEBUG=y
CONFIG_PM_ADVANCED_DEBUG=y
CONFIG_PM_SLEEP_DEBUG=y
# CONFIG_APM_EMULATION is not set
CONFIG_PM_CLK=y
CONFIG_PM_GENERIC_DOMAINS=y
CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
CONFIG_PM_GENERIC_DOMAINS_OF=y
CONFIG_CPU_PM=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARM_CPU_SUSPEND=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
# end of Power management options

#
# Firmware Drivers
#
# CONFIG_FIRMWARE_MEMMAP is not set
# CONFIG_FW_CFG_SYSFS is not set
# CONFIG_QCOM_SCM is not set
# CONFIG_TRUSTED_FOUNDATIONS is not set
CONFIG_HAVE_ARM_SMCCC=y
CONFIG_ARM_PSCI_FW=y
# CONFIG_GOOGLE_FIRMWARE is not set

#
# Tegra firmware driver
#
# end of Tegra firmware driver
# end of Firmware Drivers

# CONFIG_ARM_CRYPTO is not set
# CONFIG_VIRTUALIZATION is not set

#
# General architecture-dependent options
#
CONFIG_HAVE_OPROFILE=y
# CONFIG_KPROBES is not set
CONFIG_JUMP_LABEL=y
# CONFIG_STATIC_KEYS_SELFTEST is not set
CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
CONFIG_ARCH_USE_BUILTIN_BSWAP=y
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
CONFIG_HAVE_OPTPROBES=y
CONFIG_HAVE_NMI=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
CONFIG_HAVE_DMA_CONTIGUOUS=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
CONFIG_ARCH_HAS_KEEPINITRD=y
CONFIG_ARCH_HAS_SET_MEMORY=y
CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y
CONFIG_ARCH_32BIT_OFF_T=y
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
CONFIG_HAVE_RSEQ=y
CONFIG_HAVE_CLK=y
CONFIG_HAVE_HW_BREAKPOINT=y
CONFIG_HAVE_PERF_REGS=y
CONFIG_HAVE_PERF_USER_STACK_DUMP=y
CONFIG_HAVE_ARCH_JUMP_LABEL=y
CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
CONFIG_HAVE_STACKPROTECTOR=y
CONFIG_CC_HAS_STACKPROTECTOR_NONE=y
CONFIG_STACKPROTECTOR=y
CONFIG_STACKPROTECTOR_STRONG=y
CONFIG_LTO_NONE=y
CONFIG_HAVE_CONTEXT_TRACKING=y
CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
CONFIG_MODULES_USE_ELF_REL=y
CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
CONFIG_HAVE_EXIT_THREAD=y
CONFIG_ARCH_MMAP_RND_BITS=8
CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
CONFIG_HAVE_COPY_THREAD_TLS=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_OLD_SIGSUSPEND3=y
CONFIG_OLD_SIGACTION=y
CONFIG_64BIT_TIME=y
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
CONFIG_STRICT_KERNEL_RWX=y
CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
CONFIG_STRICT_MODULE_RWX=y
CONFIG_ARCH_HAS_PHYS_TO_DMA=y
CONFIG_REFCOUNT_FULL=y
# CONFIG_LOCK_EVENT_COUNTS is not set

#
# GCOV-based kernel profiling
#
# CONFIG_GCOV_KERNEL is not set
CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
# end of GCOV-based kernel profiling

CONFIG_PLUGIN_HOSTCC=""
CONFIG_HAVE_GCC_PLUGINS=y
# end of General architecture-dependent options

CONFIG_RT_MUTEXES=y
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
# CONFIG_MODULE_FORCE_LOAD is not set
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
# CONFIG_MODULE_SIG is not set
# CONFIG_MODULE_COMPRESS is not set
# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set
# CONFIG_UNUSED_SYMBOLS is not set
# CONFIG_TRIM_UNUSED_KSYMS is not set
CONFIG_MODULES_TREE_LOOKUP=y
CONFIG_BLOCK=y
CONFIG_BLK_SCSI_REQUEST=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_BLK_DEV_BSGLIB is not set
# CONFIG_BLK_DEV_INTEGRITY is not set
# CONFIG_BLK_DEV_ZONED is not set
# CONFIG_BLK_CMDLINE_PARSER is not set
# CONFIG_BLK_WBT is not set
CONFIG_BLK_DEBUG_FS=y
# CONFIG_BLK_SED_OPAL is not set
# CONFIG_BLK_INLINE_ENCRYPTION is not set

#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
CONFIG_EFI_PARTITION=y
# end of Partition Types

CONFIG_BLK_PM=y

#
# IO Schedulers
#
CONFIG_MQ_IOSCHED_DEADLINE=y
CONFIG_MQ_IOSCHED_KYBER=y
# CONFIG_IOSCHED_BFQ is not set
# end of IO Schedulers

CONFIG_ASN1=y
CONFIG_UNINLINE_SPIN_UNLOCK=y
CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_RWSEM_SPIN_ON_OWNER=y
CONFIG_LOCK_SPIN_ON_OWNER=y
# CONFIG_GKI_HIDDEN_DRM_CONFIGS is not set
# CONFIG_GKI_HIDDEN_REGMAP_CONFIGS is not set
# CONFIG_GKI_HIDDEN_CRYPTO_CONFIGS is not set
# CONFIG_GKI_HIDDEN_SND_CONFIGS is not set
# CONFIG_GKI_HIDDEN_SND_SOC_CONFIGS is not set
# CONFIG_GKI_HIDDEN_MMC_CONFIGS is not set
# CONFIG_GKI_HIDDEN_GPIO_CONFIGS is not set
# CONFIG_GKI_HIDDEN_QCOM_CONFIGS is not set
# CONFIG_GKI_HIDDEN_MEDIA_CONFIGS is not set
# CONFIG_GKI_HIDDEN_VIRTUAL_CONFIGS is not set
# CONFIG_GKI_LEGACY_WEXT_ALLCONFIG is not set
# CONFIG_GKI_HIDDEN_USB_CONFIGS is not set
# CONFIG_GKI_HIDDEN_SOC_BUS_CONFIGS is not set
# CONFIG_GKI_HIDDEN_RPMSG_CONFIGS is not set
# CONFIG_GKI_HIDDEN_GPU_CONFIGS is not set
# CONFIG_GKI_HIDDEN_IRQ_CONFIGS is not set
# CONFIG_GKI_HIDDEN_HYPERVISOR_CONFIGS is not set
# CONFIG_GKI_HACKS_TO_FIX is not set
# CONFIG_GKI_OPT_FEATURES is not set
CONFIG_FREEZER=y

#
# Executable file formats
#
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_ELF_FDPIC is not set
CONFIG_ELFCORE=y
CONFIG_BINFMT_SCRIPT=y
CONFIG_ARCH_HAS_BINFMT_FLAT=y
# CONFIG_BINFMT_FLAT is not set
CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
# CONFIG_BINFMT_MISC is not set
CONFIG_COREDUMP=y
# end of Executable file formats

#
# Memory Management options
#
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
CONFIG_ARCH_KEEP_MEMBLOCK=y
CONFIG_MEMORY_ISOLATION=y
CONFIG_SPLIT_PTLOCK_CPUS=4
CONFIG_COMPACTION=y
CONFIG_MIGRATION=y
CONFIG_CONTIG_ALLOC=y
# CONFIG_KSM is not set
CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
# CONFIG_CLEANCACHE is not set
CONFIG_CMA=y
# CONFIG_CMA_DEBUG is not set
# CONFIG_CMA_DEBUGFS is not set
CONFIG_CMA_AREAS=7
# CONFIG_ZPOOL is not set
# CONFIG_ZBUD is not set
# CONFIG_ZSMALLOC is not set
CONFIG_GENERIC_EARLY_IOREMAP=y
# CONFIG_IDLE_PAGE_TRACKING is not set
CONFIG_FRAME_VECTOR=y
# CONFIG_PERCPU_STATS is not set
# CONFIG_GUP_BENCHMARK is not set
# end of Memory Management options

CONFIG_NET=y

#
# Networking options
#
CONFIG_PACKET=y
# CONFIG_PACKET_DIAG is not set
CONFIG_UNIX=y
CONFIG_UNIX_SCM=y
# CONFIG_UNIX_DIAG is not set
# CONFIG_TLS is not set
# CONFIG_XFRM_USER is not set
# CONFIG_NET_KEY is not set
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_ADVANCED_ROUTER=y
# CONFIG_IP_FIB_TRIE_STATS is not set
CONFIG_IP_MULTIPLE_TABLES=y
CONFIG_IP_ROUTE_MULTIPATH=y
CONFIG_IP_ROUTE_VERBOSE=y
# CONFIG_IP_PNP is not set
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE_DEMUX is not set
CONFIG_IP_MROUTE_COMMON=y
CONFIG_IP_MROUTE=y
CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
# CONFIG_IP_PIMSM_V1 is not set
# CONFIG_IP_PIMSM_V2 is not set
CONFIG_SYN_COOKIES=y
# CONFIG_NET_IPVTI is not set
# CONFIG_NET_FOU is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
# CONFIG_INET_DIAG is not set
CONFIG_TCP_CONG_ADVANCED=y
# CONFIG_TCP_CONG_BIC is not set
CONFIG_TCP_CONG_CUBIC=y
# CONFIG_TCP_CONG_WESTWOOD is not set
# CONFIG_TCP_CONG_HTCP is not set
# CONFIG_TCP_CONG_HSTCP is not set
# CONFIG_TCP_CONG_HYBLA is not set
# CONFIG_TCP_CONG_VEGAS is not set
# CONFIG_TCP_CONG_NV is not set
# CONFIG_TCP_CONG_SCALABLE is not set
# CONFIG_TCP_CONG_LP is not set
# CONFIG_TCP_CONG_VENO is not set
# CONFIG_TCP_CONG_YEAH is not set
# CONFIG_TCP_CONG_ILLINOIS is not set
# CONFIG_TCP_CONG_DCTCP is not set
# CONFIG_TCP_CONG_CDG is not set
# CONFIG_TCP_CONG_BBR is not set
CONFIG_DEFAULT_CUBIC=y
# CONFIG_DEFAULT_RENO is not set
CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_TCP_MD5SIG is not set
CONFIG_IPV6=y
# CONFIG_IPV6_ROUTER_PREF is not set
# CONFIG_IPV6_OPTIMISTIC_DAD is not set
# CONFIG_INET6_AH is not set
# CONFIG_INET6_ESP is not set
# CONFIG_INET6_IPCOMP is not set
# CONFIG_IPV6_MIP6 is not set
# CONFIG_IPV6_VTI is not set
# CONFIG_IPV6_SIT is not set
# CONFIG_IPV6_TUNNEL is not set
CONFIG_IPV6_MULTIPLE_TABLES=y
CONFIG_IPV6_SUBTREES=y
CONFIG_IPV6_MROUTE=y
# CONFIG_IPV6_MROUTE_MULTIPLE_TABLES is not set
# CONFIG_IPV6_PIMSM_V2 is not set
# CONFIG_IPV6_SEG6_LWTUNNEL is not set
# CONFIG_IPV6_SEG6_HMAC is not set
# CONFIG_NETWORK_SECMARK is not set
# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
# CONFIG_NETFILTER is not set
# CONFIG_BPFILTER is not set
# CONFIG_IP_DCCP is not set
# CONFIG_IP_SCTP is not set
# CONFIG_RDS is not set
# CONFIG_TIPC is not set
# CONFIG_ATM is not set
# CONFIG_L2TP is not set
CONFIG_STP=y
CONFIG_BRIDGE=y
CONFIG_BRIDGE_IGMP_SNOOPING=y
CONFIG_HAVE_NET_DSA=y
# CONFIG_NET_DSA is not set
# CONFIG_VLAN_8021Q is not set
# CONFIG_DECNET is not set
CONFIG_LLC=y
# CONFIG_LLC2 is not set
# CONFIG_ATALK is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_PHONET is not set
# CONFIG_6LOWPAN is not set
# CONFIG_IEEE802154 is not set
CONFIG_NET_SCHED=y

#
# Queueing/Scheduling
#
# CONFIG_NET_SCH_CBQ is not set
# CONFIG_NET_SCH_HTB is not set
# CONFIG_NET_SCH_HFSC is not set
# CONFIG_NET_SCH_PRIO is not set
# CONFIG_NET_SCH_MULTIQ is not set
# CONFIG_NET_SCH_RED is not set
# CONFIG_NET_SCH_SFB is not set
# CONFIG_NET_SCH_SFQ is not set
# CONFIG_NET_SCH_TEQL is not set
# CONFIG_NET_SCH_TBF is not set
# CONFIG_NET_SCH_CBS is not set
# CONFIG_NET_SCH_ETF is not set
# CONFIG_NET_SCH_TAPRIO is not set
# CONFIG_NET_SCH_GRED is not set
# CONFIG_NET_SCH_DSMARK is not set
# CONFIG_NET_SCH_NETEM is not set
# CONFIG_NET_SCH_DRR is not set
# CONFIG_NET_SCH_MQPRIO is not set
# CONFIG_NET_SCH_SKBPRIO is not set
# CONFIG_NET_SCH_CHOKE is not set
# CONFIG_NET_SCH_QFQ is not set
# CONFIG_NET_SCH_CODEL is not set
CONFIG_NET_SCH_FQ_CODEL=y
# CONFIG_NET_SCH_CAKE is not set
# CONFIG_NET_SCH_FQ is not set
# CONFIG_NET_SCH_HHF is not set
# CONFIG_NET_SCH_PIE is not set
# CONFIG_NET_SCH_PLUG is not set
# CONFIG_NET_SCH_DEFAULT is not set

#
# Classification
#
# CONFIG_NET_CLS_BASIC is not set
# CONFIG_NET_CLS_TCINDEX is not set
# CONFIG_NET_CLS_ROUTE4 is not set
# CONFIG_NET_CLS_FW is not set
# CONFIG_NET_CLS_U32 is not set
# CONFIG_NET_CLS_RSVP is not set
# CONFIG_NET_CLS_RSVP6 is not set
# CONFIG_NET_CLS_FLOW is not set
# CONFIG_NET_CLS_BPF is not set
# CONFIG_NET_CLS_FLOWER is not set
# CONFIG_NET_CLS_MATCHALL is not set
# CONFIG_NET_EMATCH is not set
# CONFIG_NET_CLS_ACT is not set
CONFIG_NET_SCH_FIFO=y
# CONFIG_DCB is not set
# CONFIG_DNS_RESOLVER is not set
# CONFIG_BATMAN_ADV is not set
# CONFIG_OPENVSWITCH is not set
# CONFIG_VSOCKETS is not set
# CONFIG_NETLINK_DIAG is not set
# CONFIG_MPLS is not set
# CONFIG_NET_NSH is not set
# CONFIG_HSR is not set
# CONFIG_NET_SWITCHDEV is not set
# CONFIG_NET_L3_MASTER_DEV is not set
# CONFIG_NET_NCSI is not set
CONFIG_RPS=y
CONFIG_RFS_ACCEL=y
CONFIG_XPS=y
CONFIG_NET_RX_BUSY_POLL=y
CONFIG_BQL=y
# CONFIG_BPF_JIT is not set
CONFIG_NET_FLOW_LIMIT=y

#
# Network testing
#
# CONFIG_NET_PKTGEN is not set
# end of Network testing
# end of Networking options

# CONFIG_HAMRADIO is not set
# CONFIG_CAN is not set
CONFIG_BT=y
CONFIG_BT_BREDR=y
CONFIG_BT_RFCOMM=y
CONFIG_BT_RFCOMM_TTY=y
# CONFIG_BT_BNEP is not set
# CONFIG_BT_HIDP is not set
# CONFIG_BT_HS is not set
# CONFIG_BT_LE is not set
# CONFIG_BT_LEDS is not set
# CONFIG_BT_SELFTEST is not set
CONFIG_BT_DEBUGFS=y

#
# Bluetooth device drivers
#
# CONFIG_BT_HCIBTUSB is not set
CONFIG_BT_HCIUART_RTL3WIRE=y
# CONFIG_BT_HCIBTSDIO is not set
CONFIG_BT_HCIUART=y
CONFIG_BT_HCIUART_H4=y
CONFIG_BT_HCIUART_BCSP=y
# CONFIG_BT_HCIUART_ATH3K is not set
# CONFIG_BT_HCIUART_INTEL is not set
# CONFIG_BT_HCIUART_AG6XX is not set
# CONFIG_BT_HCIBCM203X is not set
# CONFIG_BT_HCIBPA10X is not set
# CONFIG_BT_HCIBFUSB is not set
# CONFIG_BT_HCIVHCI is not set
# CONFIG_BCM_BT_LPM is not set
CONFIG_RTL_BT_LPM=y
# CONFIG_XR_BT_LPM is not set
# CONFIG_BT_MRVL is not set
# CONFIG_BT_MTKSDIO is not set
# end of Bluetooth device drivers

# CONFIG_AF_RXRPC is not set
# CONFIG_AF_KCM is not set
CONFIG_FIB_RULES=y
CONFIG_WIRELESS=y
CONFIG_CFG80211=y
# CONFIG_NL80211_TESTMODE is not set
# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
CONFIG_CFG80211_CERTIFICATION_ONUS=y
# CONFIG_CFG80211_REQUIRE_SIGNED_REGDB is not set
# CONFIG_CFG80211_REG_CELLULAR_HINTS is not set
# CONFIG_CFG80211_REG_RELAX_NO_IR is not set
CONFIG_CFG80211_DEFAULT_PS=y
# CONFIG_CFG80211_DEBUGFS is not set
CONFIG_CFG80211_CRDA_SUPPORT=y
# CONFIG_CFG80211_WEXT is not set
# CONFIG_MAC80211 is not set
CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
# CONFIG_WIMAX is not set
# CONFIG_RFKILL is not set
# CONFIG_NET_9P is not set
# CONFIG_CAIF is not set
# CONFIG_CEPH_LIB is not set
# CONFIG_NFC is not set
# CONFIG_PSAMPLE is not set
# CONFIG_NET_IFE is not set
# CONFIG_LWTUNNEL is not set
# CONFIG_FAILOVER is not set
CONFIG_HAVE_EBPF_JIT=y

#
# Device Drivers
#
CONFIG_HAVE_PCI=y
# CONFIG_PCI is not set
# CONFIG_PCCARD is not set

#
# Generic Driver Options
#
# CONFIG_UEVENT_HELPER is not set
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y

#
# Firmware loader
#
CONFIG_FW_LOADER=y
CONFIG_EXTRA_FIRMWARE=""
# CONFIG_FW_LOADER_USER_HELPER is not set
# CONFIG_FW_LOADER_COMPRESS is not set
CONFIG_FW_CACHE=y
# end of Firmware loader

CONFIG_ALLOW_DEV_COREDUMP=y
# CONFIG_DEBUG_DRIVER is not set
# CONFIG_DEBUG_DEVRES is not set
# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
CONFIG_REGMAP_SPI=y
CONFIG_REGMAP_MMIO=y
CONFIG_DMA_SHARED_BUFFER=y
# CONFIG_DMA_FENCE_TRACE is not set
CONFIG_GENERIC_ARCH_TOPOLOGY=y
# end of Generic Driver Options

#
# Bus devices
#
# CONFIG_BRCMSTB_GISB_ARB is not set
# CONFIG_MOXTET is not set
# CONFIG_SIMPLE_PM_BUS is not set
# CONFIG_SUN50I_DE2_BUS is not set
# CONFIG_SUNXI_RSB is not set
CONFIG_SUNXI_MBUS=y
# CONFIG_SUNXI_NSI is not set
# CONFIG_VEXPRESS_CONFIG is not set
# end of Bus devices

# CONFIG_CONNECTOR is not set
# CONFIG_GNSS is not set
CONFIG_MTD=y
# CONFIG_MTD_TESTS is not set
# CONFIG_MTD_REDBOOT_PARTS is not set
# CONFIG_MTD_CMDLINE_PARTS is not set
# CONFIG_MTD_AFS_PARTS is not set
CONFIG_MTD_OF_PARTS=y
# CONFIG_MTD_AR7_PARTS is not set
# CONFIG_MTD_SUNXI_PARTS is not set

#
# Partition parsers
#
# end of Partition parsers

#
# User Modules And Translation Layers
#
CONFIG_MTD_BLKDEVS=y
# CONFIG_MTD_CHAR is not set
CONFIG_MTD_BLOCK=y
# CONFIG_FTL is not set
# CONFIG_NFTL is not set
# CONFIG_INFTL is not set
# CONFIG_RFD_FTL is not set
# CONFIG_SSFDC is not set
# CONFIG_SM_FTL is not set
# CONFIG_MTD_OOPS is not set
# CONFIG_MTD_PARTITIONED_MASTER is not set

#
# RAM/ROM/Flash chip drivers
#
# CONFIG_MTD_CFI is not set
# CONFIG_MTD_JEDECPROBE is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set
# end of RAM/ROM/Flash chip drivers

#
# Mapping drivers for chip access
#
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
# CONFIG_MTD_PLATRAM is not set
# end of Mapping drivers for chip access

#
# Self-contained MTD device drivers
#
# CONFIG_MTD_DATAFLASH is not set
# CONFIG_MTD_MCHP23K256 is not set
# CONFIG_MTD_SST25L is not set
# CONFIG_MTD_SLRAM is not set
# CONFIG_MTD_PHRAM is not set
# CONFIG_MTD_MTDRAM is not set
# CONFIG_MTD_BLOCK2MTD is not set

#
# Disk-On-Chip Device Drivers
#
# CONFIG_MTD_DOCG3 is not set
# end of Self-contained MTD device drivers

# CONFIG_MTD_ONENAND is not set
# CONFIG_MTD_RAW_NAND is not set
# CONFIG_MTD_SPI_NAND is not set

#
# sunxi-nand
#
CONFIG_AW_MTD_SPINAND=y
# CONFIG_AW_MTD_RAWNAND is not set
CONFIG_AW_SPINAND_PHYSICAL_LAYER=y
CONFIG_AW_SPINAND_SECURE_STORAGE=y
# CONFIG_AW_SPINAND_PSTORE_MTD_PART is not set
# CONFIG_AW_SPINAND_ENABLE_PHY_CRC16 is not set
CONFIG_AW_SPINAND_SIMULATE_MULTIPLANE=y
# CONFIG_AW_MTD_SPINAND_OOB_RAW_SPARE is not set
# end of sunxi-nand

#
# LPDDR & LPDDR2 PCM memory drivers
#
# CONFIG_MTD_LPDDR is not set
# CONFIG_MTD_LPDDR2_NVM is not set
# end of LPDDR & LPDDR2 PCM memory drivers

# CONFIG_MTD_SPI_NOR is not set
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_MTD_UBI_BEB_LIMIT=40
# CONFIG_MTD_UBI_FASTMAP is not set
# CONFIG_MTD_UBI_GLUEBI is not set
CONFIG_MTD_UBI_BLOCK=y
CONFIG_MTD_UBI_BLOCK_MAX_ACTIVE_WORKS=4
# CONFIG_MTD_HYPERBUS is not set
CONFIG_DTC=y
CONFIG_OF=y
# CONFIG_OF_UNITTEST is not set
CONFIG_OF_FLATTREE=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_KOBJ=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_IRQ=y
CONFIG_OF_NET=y
CONFIG_OF_MDIO=y
CONFIG_OF_RESERVED_MEM=y
# CONFIG_OF_OVERLAY is not set
CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
# CONFIG_PARPORT is not set
CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_NULL_BLK is not set
# CONFIG_BLK_DEV_LOOP is not set
# CONFIG_BLK_DEV_DRBD is not set
# CONFIG_BLK_DEV_NBD is not set
# CONFIG_BLK_DEV_RAM is not set
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
# CONFIG_BLK_DEV_RBD is not set

#
# NVME Support
#
# CONFIG_NVME_FC is not set
# CONFIG_NVME_TARGET is not set
# end of NVME Support

#
# Misc devices
#
# CONFIG_AD525X_DPOT is not set
# CONFIG_DUMMY_IRQ is not set
# CONFIG_ICS932S401 is not set
# CONFIG_ENCLOSURE_SERVICES is not set
# CONFIG_APDS9802ALS is not set
# CONFIG_ISL29003 is not set
# CONFIG_ISL29020 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_SENSORS_BH1770 is not set
# CONFIG_SENSORS_APDS990X is not set
# CONFIG_HMC6352 is not set
# CONFIG_DS1682 is not set
# CONFIG_LATTICE_ECP3_CONFIG is not set
# CONFIG_SRAM is not set
# CONFIG_XILINX_SDFEC is not set
# CONFIG_PVPANIC is not set
# CONFIG_HISI_HIKEY_USB is not set
# CONFIG_SUNXI_DIRECT_GPIO is not set
# CONFIG_C2PORT is not set

#
# EEPROM support
#
# CONFIG_EEPROM_AT24 is not set
# CONFIG_EEPROM_AT25 is not set
# CONFIG_EEPROM_LEGACY is not set
# CONFIG_EEPROM_MAX6875 is not set
# CONFIG_EEPROM_93CX6 is not set
# CONFIG_EEPROM_93XX46 is not set
# CONFIG_EEPROM_IDT_89HPESX is not set
# CONFIG_EEPROM_EE1004 is not set
# end of EEPROM support

#
# Texas Instruments shared transport line discipline
#
# CONFIG_TI_ST is not set
# end of Texas Instruments shared transport line discipline

# CONFIG_SENSORS_LIS3_SPI is not set
# CONFIG_SENSORS_LIS3_I2C is not set
# CONFIG_ALTERA_STAPL is not set

#
# Intel MIC & related support
#

#
# Intel MIC Bus Driver
#

#
# SCIF Bus Driver
#

#
# VOP Bus Driver
#
# CONFIG_VOP_BUS is not set

#
# Intel MIC Host Driver
#

#
# Intel MIC Card Driver
#

#
# SCIF Driver
#

#
# Intel MIC Coprocessor State Management (COSM) Drivers
#

#
# VOP Driver
#
# end of Intel MIC & related support

# CONFIG_ECHO is not set
# CONFIG_MISC_RTSX_USB is not set
CONFIG_SUNXI_RFKILL=y
CONFIG_SUNXI_ADDR_MGT=y
# CONFIG_SUNXI_BOOTEVENT is not set

#
# sunxi Gorilla ESL platform
#
# CONFIG_SUNXI_GORILLA is not set
# end of sunxi Gorilla ESL platform

# CONFIG_SUNXI_MIPSLOADER is not set
# CONFIG_SUNXI_TVUTILS is not set
# end of Misc devices

#
# SCSI device support
#
CONFIG_SCSI_MOD=y
# CONFIG_RAID_ATTRS is not set
CONFIG_SCSI=y
CONFIG_SCSI_DMA=y
CONFIG_SCSI_PROC_FS=y

#
# SCSI support type (disk, tape, CD-ROM)
#
CONFIG_BLK_DEV_SD=y
# CONFIG_CHR_DEV_ST is not set
# CONFIG_BLK_DEV_SR is not set
# CONFIG_CHR_DEV_SG is not set
# CONFIG_CHR_DEV_SCH is not set
# CONFIG_SCSI_CONSTANTS is not set
# CONFIG_SCSI_LOGGING is not set
# CONFIG_SCSI_SCAN_ASYNC is not set

#
# SCSI Transports
#
# CONFIG_SCSI_SPI_ATTRS is not set
# CONFIG_SCSI_FC_ATTRS is not set
# CONFIG_SCSI_ISCSI_ATTRS is not set
# CONFIG_SCSI_SAS_ATTRS is not set
# CONFIG_SCSI_SAS_LIBSAS is not set
# CONFIG_SCSI_SRP_ATTRS is not set
# end of SCSI Transports

CONFIG_SCSI_LOWLEVEL=y
# CONFIG_ISCSI_TCP is not set
# CONFIG_ISCSI_BOOT_SYSFS is not set
# CONFIG_SCSI_UFSHCD is not set
# CONFIG_SCSI_DEBUG is not set
# CONFIG_SCSI_DH is not set
# end of SCSI device support

# CONFIG_ATA is not set
# CONFIG_MD is not set
# CONFIG_TARGET_CORE is not set
CONFIG_NETDEVICES=y
CONFIG_MII=m
CONFIG_NET_CORE=y
# CONFIG_BONDING is not set
# CONFIG_DUMMY is not set
# CONFIG_EQUALIZER is not set
# CONFIG_NET_TEAM is not set
# CONFIG_MACVLAN is not set
# CONFIG_IPVLAN is not set
# CONFIG_VXLAN is not set
# CONFIG_GENEVE is not set
# CONFIG_GTP is not set
# CONFIG_MACSEC is not set
# CONFIG_NETCONSOLE is not set
# CONFIG_TUN is not set
# CONFIG_TUN_VNET_CROSS_LE is not set
# CONFIG_VETH is not set
# CONFIG_NLMON is not set

#
# CAIF transport drivers
#

#
# Distributed Switch Architecture drivers
#
# end of Distributed Switch Architecture drivers

CONFIG_ETHERNET=y
# CONFIG_NET_VENDOR_ALACRITECH is not set
CONFIG_NET_VENDOR_ALLWINNER=y
# CONFIG_SUN4I_EMAC is not set
CONFIG_SUNXI_GMAC=m
CONFIG_SUNXI_EXT_PHY=y
# CONFIG_ALTERA_TSE is not set
# CONFIG_NET_VENDOR_AMAZON is not set
# CONFIG_NET_VENDOR_AQUANTIA is not set
# CONFIG_NET_VENDOR_ARC is not set
# CONFIG_NET_VENDOR_AURORA is not set
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_VENDOR_CADENCE is not set
# CONFIG_NET_VENDOR_CAVIUM is not set
# CONFIG_NET_VENDOR_CIRRUS is not set
# CONFIG_NET_VENDOR_CORTINA is not set
# CONFIG_DM9000 is not set
# CONFIG_DNET is not set
# CONFIG_NET_VENDOR_EZCHIP is not set
# CONFIG_NET_VENDOR_FARADAY is not set
# CONFIG_NET_VENDOR_GOOGLE is not set
# CONFIG_NET_VENDOR_HISILICON is not set
# CONFIG_NET_VENDOR_HUAWEI is not set
# CONFIG_NET_VENDOR_INTEL is not set
# CONFIG_NET_VENDOR_MARVELL is not set
# CONFIG_NET_VENDOR_MELLANOX is not set
# CONFIG_NET_VENDOR_MICREL is not set
# CONFIG_NET_VENDOR_MICROCHIP is not set
# CONFIG_NET_VENDOR_MICROSEMI is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
# CONFIG_NET_VENDOR_NETRONOME is not set
# CONFIG_NET_VENDOR_NI is not set
# CONFIG_ETHOC is not set
# CONFIG_NET_VENDOR_PENSANDO is not set
# CONFIG_NET_VENDOR_QUALCOMM is not set
# CONFIG_NET_VENDOR_RENESAS is not set
# CONFIG_NET_VENDOR_ROCKER is not set
# CONFIG_NET_VENDOR_SAMSUNG is not set
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SOLARFLARE is not set
# CONFIG_NET_VENDOR_SMSC is not set
# CONFIG_NET_VENDOR_SOCIONEXT is not set
# CONFIG_NET_VENDOR_STMICRO is not set
# CONFIG_NET_VENDOR_SYNOPSYS is not set
# CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set
# CONFIG_NET_VENDOR_XILINX is not set
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_BUS=y
# CONFIG_MDIO_BCM_UNIMAC is not set
# CONFIG_MDIO_BITBANG is not set
# CONFIG_MDIO_BUS_MUX_GPIO is not set
# CONFIG_MDIO_BUS_MUX_MMIOREG is not set
# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set
# CONFIG_MDIO_HISI_FEMAC is not set
# CONFIG_MDIO_MSCC_MIIM is not set
# CONFIG_MDIO_SUN4I is not set
CONFIG_PHYLIB=y
CONFIG_SWPHY=y
# CONFIG_LED_TRIGGER_PHY is not set

#
# MII PHY device drivers
#
# CONFIG_ADIN_PHY is not set
# CONFIG_AMD_PHY is not set
# CONFIG_AQUANTIA_PHY is not set
# CONFIG_AX88796B_PHY is not set
# CONFIG_AT803X_PHY is not set
# CONFIG_BCM7XXX_PHY is not set
# CONFIG_BCM87XX_PHY is not set
# CONFIG_BROADCOM_PHY is not set
# CONFIG_CICADA_PHY is not set
# CONFIG_CORTINA_PHY is not set
# CONFIG_DAVICOM_PHY is not set
# CONFIG_DP83822_PHY is not set
# CONFIG_DP83TC811_PHY is not set
# CONFIG_DP83848_PHY is not set
# CONFIG_DP83867_PHY is not set
CONFIG_FIXED_PHY=y
# CONFIG_ICPLUS_PHY is not set
# CONFIG_INTEL_XWAY_PHY is not set
# CONFIG_LSI_ET1011C_PHY is not set
# CONFIG_LXT_PHY is not set
# CONFIG_MARVELL_PHY is not set
# CONFIG_MARVELL_10G_PHY is not set
# CONFIG_MICREL_PHY is not set
# CONFIG_MICROCHIP_PHY is not set
# CONFIG_MICROCHIP_T1_PHY is not set
# CONFIG_MICROSEMI_PHY is not set
# CONFIG_NATIONAL_PHY is not set
# CONFIG_NXP_TJA11XX_PHY is not set
# CONFIG_QSEMI_PHY is not set
CONFIG_REALTEK_PHY=y
# CONFIG_RENESAS_PHY is not set
# CONFIG_ROCKCHIP_PHY is not set
# CONFIG_RTL8363_NB is not set
# CONFIG_SMSC_PHY is not set
# CONFIG_STE10XP is not set
# CONFIG_TERANETICS_PHY is not set
# CONFIG_VITESSE_PHY is not set
# CONFIG_XILINX_GMII2RGMII is not set
# CONFIG_MICREL_KS8995MA is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
# CONFIG_USB_NET_DRIVERS is not set
CONFIG_WLAN=y
# CONFIG_WIRELESS_WDS is not set
# CONFIG_WLAN_VENDOR_ADMTEK is not set
# CONFIG_WLAN_VENDOR_ATH is not set
# CONFIG_WLAN_VENDOR_ATMEL is not set
# CONFIG_WLAN_VENDOR_BROADCOM is not set
# CONFIG_WLAN_VENDOR_CISCO is not set
# CONFIG_WLAN_VENDOR_INTEL is not set
# CONFIG_WLAN_VENDOR_INTERSIL is not set
# CONFIG_WLAN_VENDOR_MARVELL is not set
# CONFIG_WLAN_VENDOR_MEDIATEK is not set
# CONFIG_WLAN_VENDOR_RALINK is not set
# CONFIG_WLAN_VENDOR_REALTEK is not set
# CONFIG_WLAN_VENDOR_RSI is not set
# CONFIG_WLAN_VENDOR_ST is not set
# CONFIG_WLAN_VENDOR_TI is not set
# CONFIG_WLAN_VENDOR_ZYDAS is not set
# CONFIG_WLAN_VENDOR_QUANTENNA is not set
# CONFIG_XR829_WLAN is not set
# CONFIG_XR819S_WLAN is not set
# CONFIG_SPARD_WLAN_SUPPORT is not set
# CONFIG_BCMDHD is not set
# CONFIG_AIC_WLAN_SUPPORT is not set
CONFIG_RTL8723DS=m
# CONFIG_USB_NET_RNDIS_WLAN is not set
# CONFIG_VIRT_WIFI is not set

#
# Enable WiMAX (Networking options) to see the WiMAX drivers
#
# CONFIG_WAN is not set
# CONFIG_NETDEVSIM is not set
# CONFIG_NET_FAILOVER is not set
# CONFIG_ISDN is not set
# CONFIG_NVM is not set

#
# Input device support
#
CONFIG_INPUT=y
# CONFIG_INPUT_LEDS is not set
# CONFIG_INPUT_FF_MEMLESS is not set
# CONFIG_INPUT_POLLDEV is not set
# CONFIG_INPUT_SPARSEKMAP is not set
# CONFIG_INPUT_MATRIXKMAP is not set

#
# Userland interfaces
#
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_JOYDEV is not set
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_EVBUG is not set
CONFIG_INPUT_SENSORINIT=y

#
# Input Device Drivers
#
CONFIG_INPUT_KEYBOARD=y
# CONFIG_KEYBOARD_ADP5588 is not set
# CONFIG_KEYBOARD_ADP5589 is not set
# CONFIG_KEYBOARD_ATKBD is not set
# CONFIG_KEYBOARD_QT1050 is not set
# CONFIG_KEYBOARD_QT1070 is not set
# CONFIG_KEYBOARD_QT2160 is not set
# CONFIG_KEYBOARD_DLINK_DIR685 is not set
# CONFIG_KEYBOARD_LKKBD is not set
# CONFIG_KEYBOARD_GPIO is not set
# CONFIG_KEYBOARD_GPIO_POLLED is not set
# CONFIG_KEYBOARD_TCA6416 is not set
# CONFIG_KEYBOARD_TCA8418 is not set
# CONFIG_KEYBOARD_MATRIX is not set
# CONFIG_KEYBOARD_LM8323 is not set
# CONFIG_KEYBOARD_LM8333 is not set
# CONFIG_KEYBOARD_MAX7359 is not set
# CONFIG_KEYBOARD_MCS is not set
# CONFIG_KEYBOARD_MPR121 is not set
# CONFIG_KEYBOARD_NEWTON is not set
# CONFIG_KEYBOARD_OPENCORES is not set
# CONFIG_KEYBOARD_SAMSUNG is not set
# CONFIG_KEYBOARD_STOWAWAY is not set
# CONFIG_KEYBOARD_SUNKBD is not set
# CONFIG_KEYBOARD_SUN4I_LRADC is not set
# CONFIG_KEYBOARD_OMAP4 is not set
# CONFIG_KEYBOARD_TM2_TOUCHKEY is not set
# CONFIG_KEYBOARD_XTKBD is not set
# CONFIG_KEYBOARD_CAP11XX is not set
# CONFIG_KEYBOARD_BCM is not set
# CONFIG_KEYBOARD_SUNXI is not set
# CONFIG_KEYBOARD_TPKEY is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TABLET is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_PROPERTIES=y
# CONFIG_TOUCHSCREEN_ADS7846 is not set
# CONFIG_TOUCHSCREEN_AD7877 is not set
# CONFIG_TOUCHSCREEN_AD7879 is not set
# CONFIG_TOUCHSCREEN_AR1021_I2C is not set
# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set
# CONFIG_TOUCHSCREEN_BU21013 is not set
# CONFIG_TOUCHSCREEN_BU21029 is not set
# CONFIG_TOUCHSCREEN_CHIPONE_ICN8318 is not set
# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set
# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set
# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set
# CONFIG_TOUCHSCREEN_DYNAPRO is not set
# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
# CONFIG_TOUCHSCREEN_EETI is not set
# CONFIG_TOUCHSCREEN_EGALAX is not set
# CONFIG_TOUCHSCREEN_EGALAX_SERIAL is not set
# CONFIG_TOUCHSCREEN_EXC3000 is not set
# CONFIG_TOUCHSCREEN_FUJITSU is not set
# CONFIG_TOUCHSCREEN_GOODIX is not set
# CONFIG_TOUCHSCREEN_HIDEEP is not set
# CONFIG_TOUCHSCREEN_ILI210X is not set
# CONFIG_TOUCHSCREEN_S6SY761 is not set
# CONFIG_TOUCHSCREEN_GUNZE is not set
# CONFIG_TOUCHSCREEN_EKTF2127 is not set
# CONFIG_TOUCHSCREEN_ELAN is not set
# CONFIG_TOUCHSCREEN_ELO is not set
# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
# CONFIG_TOUCHSCREEN_WACOM_I2C is not set
# CONFIG_TOUCHSCREEN_MAX11801 is not set
# CONFIG_TOUCHSCREEN_MCS5000 is not set
# CONFIG_TOUCHSCREEN_MMS114 is not set
# CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set
# CONFIG_TOUCHSCREEN_MTOUCH is not set
# CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set
# CONFIG_TOUCHSCREEN_INEXIO is not set
# CONFIG_TOUCHSCREEN_MK712 is not set
# CONFIG_TOUCHSCREEN_PENMOUNT is not set
# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set
# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
# CONFIG_TOUCHSCREEN_PIXCIR is not set
# CONFIG_TOUCHSCREEN_WDT87XX_I2C is not set
# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
# CONFIG_TOUCHSCREEN_TSC_SERIO is not set
# CONFIG_TOUCHSCREEN_TSC2004 is not set
# CONFIG_TOUCHSCREEN_TSC2005 is not set
# CONFIG_TOUCHSCREEN_TSC2007 is not set
# CONFIG_TOUCHSCREEN_RM_TS is not set
# CONFIG_TOUCHSCREEN_SILEAD is not set
# CONFIG_TOUCHSCREEN_SIS_I2C is not set
# CONFIG_TOUCHSCREEN_ST1232 is not set
# CONFIG_TOUCHSCREEN_STMFTS is not set
# CONFIG_TOUCHSCREEN_SUN4I is not set
# CONFIG_TOUCHSCREEN_SUNXI is not set
# CONFIG_TOUCHSCREEN_SUR40 is not set
# CONFIG_TOUCHSCREEN_SURFACE3_SPI is not set
# CONFIG_TOUCHSCREEN_SX8654 is not set
# CONFIG_TOUCHSCREEN_TPS6507X is not set
# CONFIG_TOUCHSCREEN_ZET6223 is not set
# CONFIG_TOUCHSCREEN_ZFORCE is not set
# CONFIG_TOUCHSCREEN_ROHM_BU21023 is not set
# CONFIG_TOUCHSCREEN_IQS5XX is not set
CONFIG_TOUCHSCREEN_GSLX680NEW=m
CONFIG_TOUCHSCREEN_GT9XXNEW_TS=m
# CONFIG_TOUCHSCREEN_GT9XXNEWDUP_TS is not set
CONFIG_TOUCHSCREEN_FTS=y
# CONFIG_INPUT_MISC is not set
# CONFIG_RMI4_CORE is not set
CONFIG_INPUT_SENSOR=y
# CONFIG_SENSORS_SC7A20 is not set
# CONFIG_SENSORS_MIR3DA is not set
# CONFIG_STK3X1X is not set
# CONFIG_SUNXI_TPADC is not set
CONFIG_SUNXI_GPADC=m

#
# Hardware I/O ports
#
# CONFIG_SERIO is not set
# CONFIG_GAMEPORT is not set
# end of Hardware I/O ports
# end of Input device support

#
# Character devices
#
CONFIG_TTY=y
# CONFIG_VT is not set
CONFIG_UNIX98_PTYS=y
# CONFIG_LEGACY_PTYS is not set
# CONFIG_SERIAL_NONSTANDARD is not set
# CONFIG_N_GSM is not set
# CONFIG_TRACE_SINK is not set
# CONFIG_NULL_TTY is not set
# CONFIG_LDISC_AUTOLOAD is not set
# CONFIG_DEVMEM is not set
# CONFIG_DEVKMEM is not set

#
# Serial drivers
#
# CONFIG_SERIAL_8250 is not set

#
# Non-8250 serial port support
#
# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set
# CONFIG_SERIAL_SAMSUNG is not set
# CONFIG_SERIAL_MAX3100 is not set
# CONFIG_SERIAL_MAX310X is not set
# CONFIG_SERIAL_UARTLITE is not set
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
# CONFIG_SERIAL_SIFIVE is not set
# CONFIG_SERIAL_SCCNXP is not set
# CONFIG_SERIAL_SC16IS7XX is not set
# CONFIG_SERIAL_BCM63XX is not set
# CONFIG_SERIAL_ALTERA_JTAGUART is not set
# CONFIG_SERIAL_ALTERA_UART is not set
# CONFIG_SERIAL_IFX6X60 is not set
# CONFIG_SERIAL_XILINX_PS_UART is not set
# CONFIG_SERIAL_ARC is not set
# CONFIG_SERIAL_FSL_LPUART is not set
# CONFIG_SERIAL_FSL_LINFLEXUART is not set
# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
# CONFIG_SERIAL_ST_ASC is not set
# CONFIG_SERIAL_SPRD is not set
CONFIG_SERIAL_SUNXI=y
# CONFIG_SERIAL_SUNXI_DMA is not set
CONFIG_SERIAL_SUNXI_CONSOLE=y
# CONFIG_SERIAL_SUNXI_EARLYCON is not set
# end of Serial drivers

# CONFIG_SERIAL_DEV_BUS is not set
# CONFIG_TTY_PRINTK is not set
# CONFIG_HVC_DCC is not set
# CONFIG_IPMI_HANDLER is not set
# CONFIG_IPMB_DEVICE_INTERFACE is not set
# CONFIG_HW_RANDOM is not set
# CONFIG_RAW_DRIVER is not set
# CONFIG_TCG_TPM is not set
# CONFIG_XILLYBUS is not set
# CONFIG_SUNXI_BS83B16C is not set
# end of Character devices

# CONFIG_RANDOM_TRUST_BOOTLOADER is not set
CONFIG_DUMP_REG=y
CONFIG_DUMP_REG_MISC=y
CONFIG_SUNXI_G2D=y
CONFIG_SUNXI_G2D_MIXER=y
CONFIG_SUNXI_G2D_ROTATE=y
CONFIG_SUNXI_SYNCFENCE=y
# CONFIG_SUNXI_DI is not set
# CONFIG_SUNXI_STANDBY_DEBUG is not set
# CONFIG_SUNXI_SYS_INFO is not set
# CONFIG_SUNXI_SMC is not set

#
# I2C support
#
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
# CONFIG_I2C_COMPAT is not set
CONFIG_I2C_CHARDEV=y
# CONFIG_I2C_MUX is not set
# CONFIG_I2C_HELPER_AUTO is not set
# CONFIG_I2C_SMBUS is not set

#
# I2C Algorithms
#
# CONFIG_I2C_ALGOBIT is not set
# CONFIG_I2C_ALGOPCF is not set
# CONFIG_I2C_ALGOPCA is not set
# end of I2C Algorithms

#
# I2C Hardware Bus support
#

#
# I2C system bus drivers (mostly embedded / system-on-chip)
#
# CONFIG_I2C_CBUS_GPIO is not set
# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
# CONFIG_I2C_EMEV2 is not set
# CONFIG_I2C_GPIO is not set
# CONFIG_I2C_MV64XXX is not set
# CONFIG_I2C_OCORES is not set
CONFIG_I2C_SUNXI=y
# CONFIG_I2C_PCA_PLATFORM is not set
# CONFIG_I2C_RK3X is not set
# CONFIG_I2C_SIMTEC is not set
# CONFIG_I2C_XILINX is not set

#
# External I2C/SMBus adapter drivers
#
# CONFIG_I2C_DIOLAN_U2C is not set
# CONFIG_I2C_PARPORT_LIGHT is not set
# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
# CONFIG_I2C_TAOS_EVM is not set
# CONFIG_I2C_TINY_USB is not set

#
# Other I2C/SMBus bus drivers
#
# end of I2C Hardware Bus support

# CONFIG_I2C_STUB is not set
CONFIG_I2C_SLAVE=y
# CONFIG_I2C_SLAVE_EEPROM is not set
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
# end of I2C support

# CONFIG_I3C is not set
CONFIG_SPI=y
# CONFIG_SPI_DEBUG is not set
CONFIG_SPI_MASTER=y
# CONFIG_SPI_MEM is not set

#
# SPI Master Controller Drivers
#
# CONFIG_SPI_ALTERA is not set
# CONFIG_SPI_AXI_SPI_ENGINE is not set
# CONFIG_SPI_BITBANG is not set
# CONFIG_SPI_CADENCE is not set
# CONFIG_SPI_DESIGNWARE is not set
# CONFIG_SPI_NXP_FLEXSPI is not set
# CONFIG_SPI_GPIO is not set
# CONFIG_SPI_FSL_SPI is not set
# CONFIG_SPI_OC_TINY is not set
# CONFIG_SPI_ROCKCHIP is not set
# CONFIG_SPI_SC18IS602 is not set
# CONFIG_SPI_SIFIVE is not set
# CONFIG_SPI_SUN4I is not set
# CONFIG_SPI_SUN6I is not set
# CONFIG_SPI_MXIC is not set
CONFIG_SPI_SUNXI=y
# CONFIG_SPI_XCOMM is not set
# CONFIG_SPI_XILINX is not set
# CONFIG_SPI_ZYNQMP_GQSPI is not set

#
# SPI Protocol Masters
#
CONFIG_SPI_SPIDEV=y
# CONFIG_SPI_LOOPBACK_TEST is not set
# CONFIG_SPI_TLE62X0 is not set
# CONFIG_SPI_SLAVE is not set
# CONFIG_SPMI is not set
# CONFIG_HSI is not set
# CONFIG_PPS is not set

#
# PTP clock support
#
# CONFIG_PTP_1588_CLOCK is not set

#
# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
#
# end of PTP clock support

CONFIG_PINCTRL=y
CONFIG_PINMUX=y
CONFIG_PINCONF=y
CONFIG_GENERIC_PINCONF=y
# CONFIG_DEBUG_PINCTRL is not set
# CONFIG_PINCTRL_AMD is not set
# CONFIG_PINCTRL_MCP23S08 is not set
# CONFIG_PINCTRL_SINGLE is not set
# CONFIG_PINCTRL_SX150X is not set
# CONFIG_PINCTRL_STMFX is not set
# CONFIG_PINCTRL_OCELOT is not set

#
# Allwinner SOC PINCTRL DRIVER
#
CONFIG_PINCTRL_SUNXI=y
# CONFIG_PINCTRL_SUNXI_DEBUGFS is not set
# CONFIG_PINCTRL_SUNXI_TEST is not set
# CONFIG_PINCTRL_SUN8IW15P1 is not set
# CONFIG_PINCTRL_SUN8IW15P1_R is not set
CONFIG_PINCTRL_SUN8IW20=y
# CONFIG_PINCTRL_SUN50IW9 is not set
# CONFIG_PINCTRL_SUN50IW9_R is not set
# CONFIG_PINCTRL_SUN50IW10P1 is not set
# CONFIG_PINCTRL_SUN50IW10P1_R is not set
# CONFIG_PINCTRL_SUN50IW12 is not set
# CONFIG_PINCTRL_SUN50IW12_R is not set
# CONFIG_PINCTRL_SUN55IW3 is not set
# CONFIG_PINCTRL_SUN55IW3_R is not set
# CONFIG_PINCTRL_SUN4I_A10 is not set
# CONFIG_PINCTRL_SUN5I is not set
# CONFIG_PINCTRL_SUN6I_A31 is not set
# CONFIG_PINCTRL_SUN6I_A31_R is not set
# CONFIG_PINCTRL_SUN8I_A23 is not set
# CONFIG_PINCTRL_SUN8I_A33 is not set
# CONFIG_PINCTRL_SUN8I_A83T is not set
# CONFIG_PINCTRL_SUN8I_A83T_R is not set
# CONFIG_PINCTRL_SUN8I_A23_R is not set
# CONFIG_PINCTRL_SUN8I_H3 is not set
# CONFIG_PINCTRL_SUN8I_H3_R is not set
# CONFIG_PINCTRL_SUN8I_V3S is not set
# CONFIG_PINCTRL_SUN9I_A80 is not set
# CONFIG_PINCTRL_SUN9I_A80_R is not set
# CONFIG_PINCTRL_SUN50I_A64 is not set
# CONFIG_PINCTRL_SUN50I_A64_R is not set
# CONFIG_PINCTRL_SUN50I_A100 is not set
# CONFIG_PINCTRL_SUN50I_A100_R is not set
# CONFIG_PINCTRL_SUN50I_H5 is not set
# CONFIG_PINCTRL_SUN50I_H6 is not set
# CONFIG_PINCTRL_SUN50I_H6_R is not set
# end of Allwinner SOC PINCTRL DRIVER

CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
CONFIG_GPIOLIB=y
CONFIG_GPIOLIB_FASTPATH_LIMIT=512
CONFIG_OF_GPIO=y
# CONFIG_DEBUG_GPIO is not set
CONFIG_GPIO_SYSFS=y

#
# Memory mapped GPIO drivers
#
# CONFIG_GPIO_74XX_MMIO is not set
# CONFIG_GPIO_ALTERA is not set
# CONFIG_GPIO_SUNXI is not set
# CONFIG_GPIO_CADENCE is not set
# CONFIG_GPIO_DWAPB is not set
# CONFIG_GPIO_FTGPIO010 is not set
# CONFIG_GPIO_GENERIC_PLATFORM is not set
# CONFIG_GPIO_GRGPIO is not set
# CONFIG_GPIO_HLWD is not set
# CONFIG_GPIO_MB86S7X is not set
# CONFIG_GPIO_MPC8XXX is not set
# CONFIG_GPIO_SAMA5D2_PIOBU is not set
# CONFIG_GPIO_SYSCON is not set
# CONFIG_GPIO_XILINX is not set
# CONFIG_GPIO_ZEVIO is not set
# CONFIG_GPIO_AMD_FCH is not set
# end of Memory mapped GPIO drivers

#
# I2C GPIO expanders
#
# CONFIG_GPIO_ADP5588 is not set
# CONFIG_GPIO_ADNP is not set
# CONFIG_GPIO_BS83B16C is not set
# CONFIG_GPIO_GW_PLD is not set
# CONFIG_GPIO_MAX7300 is not set
# CONFIG_GPIO_MAX732X is not set
# CONFIG_GPIO_PCA953X is not set
# CONFIG_GPIO_PCF857X is not set
# CONFIG_GPIO_TPIC2810 is not set
# end of I2C GPIO expanders

#
# MFD GPIO expanders
#
# CONFIG_HTC_EGPIO is not set
# end of MFD GPIO expanders

#
# SPI GPIO expanders
#
# CONFIG_GPIO_74X164 is not set
# CONFIG_GPIO_MAX3191X is not set
# CONFIG_GPIO_MAX7301 is not set
# CONFIG_GPIO_MC33880 is not set
# CONFIG_GPIO_PISOSR is not set
# CONFIG_GPIO_XRA1403 is not set
# end of SPI GPIO expanders

#
# USB GPIO expanders
#
# end of USB GPIO expanders

# CONFIG_GPIO_MOCKUP is not set
# CONFIG_W1 is not set
# CONFIG_POWER_AVS is not set
# CONFIG_POWER_RESET is not set
CONFIG_POWER_SUPPLY=y
# CONFIG_POWER_SUPPLY_DEBUG is not set
CONFIG_POWER_SUPPLY_HWMON=y
# CONFIG_PDA_POWER is not set
# CONFIG_TEST_POWER is not set
# CONFIG_CHARGER_ADP5061 is not set
# CONFIG_BATTERY_DS2780 is not set
# CONFIG_BATTERY_DS2781 is not set
# CONFIG_BATTERY_DS2782 is not set
# CONFIG_BATTERY_SBS is not set
# CONFIG_CHARGER_SBS is not set
# CONFIG_BATTERY_BQ27XXX is not set
# CONFIG_BATTERY_MAX17040 is not set
# CONFIG_BATTERY_MAX17042 is not set
# CONFIG_CHARGER_MAX8903 is not set
# CONFIG_CHARGER_LP8727 is not set
# CONFIG_CHARGER_GPIO is not set
# CONFIG_CHARGER_MANAGER is not set
# CONFIG_CHARGER_LT3651 is not set
# CONFIG_CHARGER_DETECTOR_MAX14656 is not set
# CONFIG_CHARGER_BQ2415X is not set
# CONFIG_CHARGER_BQ24257 is not set
# CONFIG_CHARGER_BQ24735 is not set
# CONFIG_CHARGER_BQ25890 is not set
# CONFIG_CHARGER_SMB347 is not set
# CONFIG_BATTERY_GAUGE_LTC2941 is not set
# CONFIG_CHARGER_RT9455 is not set
# CONFIG_CHARGER_UCS1002 is not set
CONFIG_HWMON=y
# CONFIG_HWMON_DEBUG_CHIP is not set

#
# Native drivers
#
# CONFIG_SENSORS_AD7314 is not set
# CONFIG_SENSORS_AD7414 is not set
# CONFIG_SENSORS_AD7418 is not set
# CONFIG_SENSORS_ADM1021 is not set
# CONFIG_SENSORS_ADM1025 is not set
# CONFIG_SENSORS_ADM1026 is not set
# CONFIG_SENSORS_ADM1029 is not set
# CONFIG_SENSORS_ADM1031 is not set
# CONFIG_SENSORS_ADM9240 is not set
# CONFIG_SENSORS_ADT7310 is not set
# CONFIG_SENSORS_ADT7410 is not set
# CONFIG_SENSORS_ADT7411 is not set
# CONFIG_SENSORS_ADT7462 is not set
# CONFIG_SENSORS_ADT7470 is not set
# CONFIG_SENSORS_ADT7475 is not set
# CONFIG_SENSORS_AS370 is not set
# CONFIG_SENSORS_ASC7621 is not set
# CONFIG_SENSORS_ASPEED is not set
# CONFIG_SENSORS_ATXP1 is not set
# CONFIG_SENSORS_DS620 is not set
# CONFIG_SENSORS_DS1621 is not set
# CONFIG_SENSORS_F71805F is not set
# CONFIG_SENSORS_F71882FG is not set
# CONFIG_SENSORS_F75375S is not set
# CONFIG_SENSORS_GL518SM is not set
# CONFIG_SENSORS_GL520SM is not set
# CONFIG_SENSORS_G760A is not set
# CONFIG_SENSORS_G762 is not set
# CONFIG_SENSORS_GPIO_FAN is not set
# CONFIG_SENSORS_HIH6130 is not set
# CONFIG_SENSORS_IT87 is not set
# CONFIG_SENSORS_JC42 is not set
# CONFIG_SENSORS_POWR1220 is not set
# CONFIG_SENSORS_LINEAGE is not set
# CONFIG_SENSORS_LTC2945 is not set
# CONFIG_SENSORS_LTC2990 is not set
# CONFIG_SENSORS_LTC4151 is not set
# CONFIG_SENSORS_LTC4215 is not set
# CONFIG_SENSORS_LTC4222 is not set
# CONFIG_SENSORS_LTC4245 is not set
# CONFIG_SENSORS_LTC4260 is not set
# CONFIG_SENSORS_LTC4261 is not set
# CONFIG_SENSORS_MAX1111 is not set
# CONFIG_SENSORS_MAX16065 is not set
# CONFIG_SENSORS_MAX1619 is not set
# CONFIG_SENSORS_MAX1668 is not set
# CONFIG_SENSORS_MAX197 is not set
# CONFIG_SENSORS_MAX31722 is not set
# CONFIG_SENSORS_MAX6621 is not set
# CONFIG_SENSORS_MAX6639 is not set
# CONFIG_SENSORS_MAX6642 is not set
# CONFIG_SENSORS_MAX6650 is not set
# CONFIG_SENSORS_MAX6697 is not set
# CONFIG_SENSORS_MAX31790 is not set
# CONFIG_SENSORS_MCP3021 is not set
# CONFIG_SENSORS_TC654 is not set
# CONFIG_SENSORS_ADCXX is not set
# CONFIG_SENSORS_LM63 is not set
# CONFIG_SENSORS_LM70 is not set
# CONFIG_SENSORS_LM73 is not set
# CONFIG_SENSORS_LM75 is not set
# CONFIG_SENSORS_LM77 is not set
# CONFIG_SENSORS_LM78 is not set
# CONFIG_SENSORS_LM80 is not set
# CONFIG_SENSORS_LM83 is not set
# CONFIG_SENSORS_LM85 is not set
# CONFIG_SENSORS_LM87 is not set
# CONFIG_SENSORS_LM90 is not set
# CONFIG_SENSORS_LM92 is not set
# CONFIG_SENSORS_LM93 is not set
# CONFIG_SENSORS_LM95234 is not set
# CONFIG_SENSORS_LM95241 is not set
# CONFIG_SENSORS_LM95245 is not set
# CONFIG_SENSORS_PC87360 is not set
# CONFIG_SENSORS_PC87427 is not set
# CONFIG_SENSORS_NTC_THERMISTOR is not set
# CONFIG_SENSORS_NCT6683 is not set
# CONFIG_SENSORS_NCT6775 is not set
# CONFIG_SENSORS_NCT7802 is not set
# CONFIG_SENSORS_NCT7904 is not set
# CONFIG_SENSORS_NPCM7XX is not set
# CONFIG_SENSORS_OCC_P8_I2C is not set
# CONFIG_SENSORS_PCF8591 is not set
# CONFIG_PMBUS is not set
# CONFIG_SENSORS_PWM_FAN is not set
# CONFIG_SENSORS_SHT15 is not set
# CONFIG_SENSORS_SHT21 is not set
# CONFIG_SENSORS_SHT3x is not set
# CONFIG_SENSORS_SHTC1 is not set
# CONFIG_SENSORS_DME1737 is not set
# CONFIG_SENSORS_EMC1403 is not set
# CONFIG_SENSORS_EMC2103 is not set
# CONFIG_SENSORS_EMC6W201 is not set
# CONFIG_SENSORS_SMSC47M1 is not set
# CONFIG_SENSORS_SMSC47M192 is not set
# CONFIG_SENSORS_SMSC47B397 is not set
# CONFIG_SENSORS_STTS751 is not set
# CONFIG_SENSORS_SMM665 is not set
# CONFIG_SENSORS_ADC128D818 is not set
# CONFIG_SENSORS_ADS7828 is not set
# CONFIG_SENSORS_ADS7871 is not set
# CONFIG_SENSORS_AMC6821 is not set
# CONFIG_SENSORS_INA209 is not set
# CONFIG_SENSORS_INA2XX is not set
# CONFIG_SENSORS_INA3221 is not set
# CONFIG_SENSORS_TC74 is not set
# CONFIG_SENSORS_THMC50 is not set
# CONFIG_SENSORS_TMP102 is not set
# CONFIG_SENSORS_TMP103 is not set
# CONFIG_SENSORS_TMP108 is not set
# CONFIG_SENSORS_TMP401 is not set
# CONFIG_SENSORS_TMP421 is not set
# CONFIG_SENSORS_VT1211 is not set
# CONFIG_SENSORS_W83773G is not set
# CONFIG_SENSORS_W83781D is not set
# CONFIG_SENSORS_W83791D is not set
# CONFIG_SENSORS_W83792D is not set
# CONFIG_SENSORS_W83793 is not set
# CONFIG_SENSORS_W83795 is not set
# CONFIG_SENSORS_W83L785TS is not set
# CONFIG_SENSORS_W83L786NG is not set
# CONFIG_SENSORS_W83627HF is not set
# CONFIG_SENSORS_W83627EHF is not set
# CONFIG_THERMAL is not set
# CONFIG_WATCHDOG is not set
CONFIG_SSB_POSSIBLE=y
# CONFIG_SSB is not set
CONFIG_BCMA_POSSIBLE=y
# CONFIG_BCMA is not set

#
# Multifunction device drivers
#
# CONFIG_MFD_ACX00 is not set
# CONFIG_MFD_ACT8945A is not set
# CONFIG_MFD_SUN4I_GPADC is not set
# CONFIG_MFD_AS3711 is not set
# CONFIG_MFD_AS3722 is not set
# CONFIG_PMIC_ADP5520 is not set
# CONFIG_MFD_AAT2870_CORE is not set
# CONFIG_MFD_ATMEL_FLEXCOM is not set
# CONFIG_MFD_ATMEL_HLCDC is not set
# CONFIG_MFD_BCM590XX is not set
# CONFIG_MFD_BD9571MWV is not set
# CONFIG_MFD_AXP2101_I2C is not set
# CONFIG_MFD_AXP20X_I2C is not set
# CONFIG_MFD_MADERA is not set
# CONFIG_MFD_ASIC3 is not set
# CONFIG_PMIC_DA903X is not set
# CONFIG_MFD_DA9052_SPI is not set
# CONFIG_MFD_DA9052_I2C is not set
# CONFIG_MFD_DA9055 is not set
# CONFIG_MFD_DA9062 is not set
# CONFIG_MFD_DA9063 is not set
# CONFIG_MFD_DA9150 is not set
# CONFIG_MFD_DLN2 is not set
# CONFIG_MFD_MC13XXX_SPI is not set
# CONFIG_MFD_MC13XXX_I2C is not set
# CONFIG_MFD_HI6421_PMIC is not set
# CONFIG_HTC_PASIC3 is not set
# CONFIG_HTC_I2CPLD is not set
# CONFIG_MFD_KEMPLD is not set
# CONFIG_MFD_88PM800 is not set
# CONFIG_MFD_88PM805 is not set
# CONFIG_MFD_88PM860X is not set
# CONFIG_MFD_MAX14577 is not set
# CONFIG_MFD_MAX77620 is not set
# CONFIG_MFD_MAX77650 is not set
# CONFIG_MFD_MAX77686 is not set
# CONFIG_MFD_MAX77693 is not set
# CONFIG_MFD_MAX77843 is not set
# CONFIG_MFD_MAX8907 is not set
# CONFIG_MFD_MAX8925 is not set
# CONFIG_MFD_MAX8997 is not set
# CONFIG_MFD_MAX8998 is not set
# CONFIG_MFD_MT6397 is not set
# CONFIG_MFD_MENF21BMC is not set
# CONFIG_EZX_PCAP is not set
# CONFIG_MFD_CPCAP is not set
# CONFIG_MFD_VIPERBOARD is not set
# CONFIG_MFD_RETU is not set
# CONFIG_MFD_PCF50633 is not set
# CONFIG_MFD_PM8XXX is not set
# CONFIG_MFD_RT5033 is not set
# CONFIG_MFD_RC5T583 is not set
# CONFIG_MFD_RK808 is not set
# CONFIG_MFD_RN5T618 is not set
# CONFIG_MFD_SEC_CORE is not set
# CONFIG_MFD_SI476X_CORE is not set
# CONFIG_MFD_SM501 is not set
# CONFIG_MFD_SKY81452 is not set
# CONFIG_MFD_SMSC is not set
# CONFIG_ABX500_CORE is not set
# CONFIG_MFD_STMPE is not set
# CONFIG_MFD_SUN6I_PRCM is not set
CONFIG_MFD_SYSCON=y
# CONFIG_MFD_TI_AM335X_TSCADC is not set
# CONFIG_MFD_LP3943 is not set
# CONFIG_MFD_LP8788 is not set
# CONFIG_MFD_TI_LMU is not set
# CONFIG_MFD_PALMAS is not set
# CONFIG_TPS6105X is not set
# CONFIG_TPS65010 is not set
# CONFIG_TPS6507X is not set
# CONFIG_MFD_TPS65086 is not set
# CONFIG_MFD_TPS65090 is not set
# CONFIG_MFD_TPS65217 is not set
# CONFIG_MFD_TI_LP873X is not set
# CONFIG_MFD_TI_LP87565 is not set
# CONFIG_MFD_TPS65218 is not set
# CONFIG_MFD_TPS6586X is not set
# CONFIG_MFD_TPS65910 is not set
# CONFIG_MFD_TPS65912_I2C is not set
# CONFIG_MFD_TPS65912_SPI is not set
# CONFIG_MFD_TPS80031 is not set
# CONFIG_TWL4030_CORE is not set
# CONFIG_TWL6040_CORE is not set
# CONFIG_MFD_WL1273_CORE is not set
# CONFIG_MFD_LM3533 is not set
# CONFIG_MFD_TC3589X is not set
# CONFIG_MFD_T7L66XB is not set
# CONFIG_MFD_TC6387XB is not set
# CONFIG_MFD_TC6393XB is not set
# CONFIG_MFD_TQMX86 is not set
# CONFIG_MFD_LOCHNAGAR is not set
# CONFIG_MFD_ARIZONA_I2C is not set
# CONFIG_MFD_ARIZONA_SPI is not set
# CONFIG_MFD_WM8400 is not set
# CONFIG_MFD_WM831X_I2C is not set
# CONFIG_MFD_WM831X_SPI is not set
# CONFIG_MFD_WM8350_I2C is not set
# CONFIG_MFD_WM8994 is not set
# CONFIG_MFD_ROHM_BD718XX is not set
# CONFIG_MFD_ROHM_BD70528 is not set
# CONFIG_MFD_STPMIC1 is not set
# CONFIG_MFD_STMFX is not set
# end of Multifunction device drivers

CONFIG_REGULATOR=y
# CONFIG_REGULATOR_DEBUG is not set
CONFIG_REGULATOR_FIXED_VOLTAGE=y
# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
# CONFIG_REGULATOR_88PG86X is not set
# CONFIG_REGULATOR_ACT8865 is not set
# CONFIG_REGULATOR_AD5398 is not set
# CONFIG_REGULATOR_ANATOP is not set
# CONFIG_SUNXI_REGULATOR_PWM is not set
# CONFIG_REGULATOR_DA9210 is not set
# CONFIG_REGULATOR_DA9211 is not set
# CONFIG_REGULATOR_FAN53555 is not set
# CONFIG_REGULATOR_GPIO is not set
# CONFIG_REGULATOR_ISL9305 is not set
# CONFIG_REGULATOR_ISL6271A is not set
# CONFIG_REGULATOR_LP3971 is not set
# CONFIG_REGULATOR_LP3972 is not set
# CONFIG_REGULATOR_LP872X is not set
# CONFIG_REGULATOR_LP8755 is not set
# CONFIG_REGULATOR_LTC3589 is not set
# CONFIG_REGULATOR_LTC3676 is not set
# CONFIG_REGULATOR_MAX1586 is not set
# CONFIG_REGULATOR_MAX8649 is not set
# CONFIG_REGULATOR_MAX8660 is not set
# CONFIG_REGULATOR_MAX8952 is not set
# CONFIG_REGULATOR_MCP16502 is not set
# CONFIG_REGULATOR_MT6311 is not set
# CONFIG_REGULATOR_PFUZE100 is not set
# CONFIG_REGULATOR_PV88060 is not set
# CONFIG_REGULATOR_PV88080 is not set
# CONFIG_REGULATOR_PV88090 is not set
# CONFIG_REGULATOR_PWM is not set
# CONFIG_REGULATOR_SLG51000 is not set
# CONFIG_REGULATOR_SY8106A is not set
# CONFIG_REGULATOR_SY8824X is not set
# CONFIG_REGULATOR_TPS51632 is not set
# CONFIG_REGULATOR_TPS62360 is not set
# CONFIG_REGULATOR_TPS65023 is not set
# CONFIG_REGULATOR_TPS6507X is not set
# CONFIG_REGULATOR_TPS65132 is not set
# CONFIG_REGULATOR_TPS6524X is not set
# CONFIG_REGULATOR_VCTRL is not set
CONFIG_RC_CORE=y
CONFIG_RC_MAP=y
CONFIG_LIRC=y
CONFIG_RC_DECODERS=y
# CONFIG_IR_NEC_DECODER is not set
# CONFIG_IR_RC5_DECODER is not set
# CONFIG_IR_RC6_DECODER is not set
# CONFIG_IR_JVC_DECODER is not set
# CONFIG_IR_SONY_DECODER is not set
# CONFIG_IR_SANYO_DECODER is not set
# CONFIG_IR_SHARP_DECODER is not set
# CONFIG_IR_MCE_KBD_DECODER is not set
# CONFIG_IR_XMP_DECODER is not set
# CONFIG_IR_IMON_DECODER is not set
# CONFIG_IR_RCMM_DECODER is not set
CONFIG_RC_DEVICES=y
# CONFIG_RC_ATI_REMOTE is not set
# CONFIG_IR_HIX5HD2 is not set
# CONFIG_IR_IMON is not set
# CONFIG_IR_IMON_RAW is not set
# CONFIG_IR_MCEUSB is not set
# CONFIG_IR_REDRAT3 is not set
# CONFIG_IR_SPI is not set
# CONFIG_IR_STREAMZAP is not set
# CONFIG_IR_IGORPLUGUSB is not set
# CONFIG_IR_IGUANA is not set
# CONFIG_IR_TTUSBIR is not set
# CONFIG_RC_LOOPBACK is not set
# CONFIG_IR_GPIO_CIR is not set
# CONFIG_IR_GPIO_TX is not set
# CONFIG_IR_PWM_TX is not set
# CONFIG_IR_SUNXI is not set
# CONFIG_IR_RX_SUNXI is not set
# CONFIG_IR_TX_SUNXI is not set
# CONFIG_IR_SERIAL is not set
# CONFIG_IR_SIR is not set
# CONFIG_RC_XBOX_DVD is not set
CONFIG_MEDIA_SUPPORT=y

#
# Multimedia core support
#
CONFIG_MEDIA_CAMERA_SUPPORT=y
# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set
# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set
# CONFIG_MEDIA_RADIO_SUPPORT is not set
# CONFIG_MEDIA_SDR_SUPPORT is not set
# CONFIG_MEDIA_CEC_SUPPORT is not set
CONFIG_MEDIA_CONTROLLER=y
CONFIG_VIDEO_DEV=y
CONFIG_VIDEO_V4L2_SUBDEV_API=y
CONFIG_VIDEO_V4L2=y
CONFIG_VIDEO_V4L2_I2C=y
# CONFIG_VIDEO_ADV_DEBUG is not set
# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
CONFIG_V4L2_MEM2MEM_DEV=m

#
# Media drivers
#
CONFIG_MEDIA_USB_SUPPORT=y

#
# Webcam devices
#
CONFIG_USB_VIDEO_CLASS=y
CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
# CONFIG_USB_GSPCA is not set
# CONFIG_USB_PWC is not set
# CONFIG_VIDEO_CPIA2 is not set
# CONFIG_USB_ZR364XX is not set
# CONFIG_USB_STKWEBCAM is not set
# CONFIG_USB_S2255 is not set
# CONFIG_VIDEO_USBTV is not set

#
# Webcam, TV (analog/digital) USB devices
#
# CONFIG_VIDEO_EM28XX is not set
CONFIG_V4L_PLATFORM_DRIVERS=y
# CONFIG_VIDEO_CADENCE is not set
# CONFIG_VIDEO_ASPEED is not set
# CONFIG_VIDEO_MUX is not set
# CONFIG_VIDEO_XILINX is not set
# CONFIG_VIDEO_SUN4I_CSI is not set
# CONFIG_VIDEO_SUN6I_CSI is not set
# CONFIG_VIDEO_SUNXI_TVD is not set
CONFIG_SUNXI_PLATFORM_DRIVERS=y
CONFIG_VIDEO_SUNXI_VIN=m
CONFIG_CSI_VIN=m
# CONFIG_ENABLE_SENSOR_FLIP_OPTION is not set
CONFIG_CSI_CCI=m
# CONFIG_CCI is not set
CONFIG_CCI_TO_TWI=y
# CONFIG_FLASH is not set
# CONFIG_ACTUATOR is not set
# CONFIG_SENSOR_LIST is not set
# CONFIG_BUF_AUTO_UPDATE is not set
# CONFIG_VIN_LOG is not set
# CONFIG_PIPELINE_RESET is not set
# CONFIG_MULTI_FRAME is not set
# CONFIG_SUPPORT_ISP_TDM is not set
# CONFIG_DISPPLAY_SYNC is not set
# CONFIG_VIN_IOMMU is not set
# CONFIG_D3D is not set
CONFIG_WDR=y
# CONFIG_WDR_COMPRESS_EN is not set
# CONFIG_SAME_I2C is not set

#
# sensor driver select
#
# CONFIG_SENSOR_RN6854M is not set
# CONFIG_SENSOR_NVP6158C is not set
# CONFIG_SENSOR_GC030A is not set
# CONFIG_SENSOR_GC2385 is not set
# CONFIG_SENSOR_GC5025 is not set
# CONFIG_SENSOR_IMX278 is not set
# CONFIG_SENSOR_IMX278_2LANE is not set
# CONFIG_SENSOR_IMX386 is not set
# CONFIG_SENSOR_IMX386_2LANE is not set
CONFIG_SENSOR_OV5640=m
# CONFIG_SENSOR_OV2775 is not set
# CONFIG_SENSOR_GC2145 is not set
# CONFIG_SENSOR_GC0310 is not set
# CONFIG_SENSOR_GC2355 is not set
# CONFIG_SENSOR_GC5024 is not set
# CONFIG_SENSOR_GC5035 is not set
# CONFIG_SENSOR_GC2590 is not set
# CONFIG_SENSOR_SP5409 is not set
# CONFIG_SENSOR_IMX214 is not set
# CONFIG_SENSOR_IMX219 is not set
# CONFIG_SENSOR_IMX274_SLVDS is not set
# CONFIG_SENSOR_IMX291_DVP is not set
# CONFIG_SENSOR_IMX291 is not set
# CONFIG_SENSOR_IMX317 is not set
# CONFIG_SENSOR_IMX335 is not set
# CONFIG_SENSOR_IMX326 is not set
# CONFIG_SENSOR_IMX477 is not set
# CONFIG_SENSOR_OV2710 is not set
# CONFIG_SENSOR_OV2718 is not set
# CONFIG_SENSOR_AR0238 is not set
# CONFIG_SENSOR_OV8858_R2A_4LANE is not set
# CONFIG_SENSOR_OV2680 is not set
# CONFIG_SENSOR_S5K3H5XA is not set
# CONFIG_SENSOR_AR0238_HISPI is not set
# CONFIG_SENSOR_NVP6134 is not set
# CONFIG_SENSOR_NVP6324 is not set
# CONFIG_SENSOR_TP9950 is not set
# CONFIG_SENSOR_SC2232 is not set
# CONFIG_SENSOR_GC02M2 is not set
# end of sensor driver select

# CONFIG_SENSOR_POWER is not set
CONFIG_V4L_MEM2MEM_DRIVERS=y
CONFIG_VIDEO_MEM2MEM_DEINTERLACE=m
CONFIG_VIDEO_SH_VEU=m
# CONFIG_V4L_TEST_DRIVERS is not set

#
# Supported MMC/SDIO adapters
#
# CONFIG_CYPRESS_FIRMWARE is not set
CONFIG_VIDEOBUF2_CORE=y
CONFIG_VIDEOBUF2_V4L2=y
CONFIG_VIDEOBUF2_MEMOPS=y
CONFIG_VIDEOBUF2_DMA_CONTIG=m
CONFIG_VIDEOBUF2_VMALLOC=y

#
# Media ancillary drivers (tuners, sensors, i2c, spi, frontends)
#
# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
# CONFIG_VIDEO_IR_I2C is not set

#
# I2C Encoders, decoders, sensors and other helper chips
#

#
# Audio decoders, processors and mixers
#
# CONFIG_VIDEO_TVAUDIO is not set
# CONFIG_VIDEO_TDA7432 is not set
# CONFIG_VIDEO_TDA9840 is not set
# CONFIG_VIDEO_TDA1997X is not set
# CONFIG_VIDEO_TEA6415C is not set
# CONFIG_VIDEO_TEA6420 is not set
# CONFIG_VIDEO_MSP3400 is not set
# CONFIG_VIDEO_CS3308 is not set
# CONFIG_VIDEO_CS5345 is not set
# CONFIG_VIDEO_CS53L32A is not set
# CONFIG_VIDEO_TLV320AIC23B is not set
# CONFIG_VIDEO_UDA1342 is not set
# CONFIG_VIDEO_WM8775 is not set
# CONFIG_VIDEO_WM8739 is not set
# CONFIG_VIDEO_VP27SMPX is not set
# CONFIG_VIDEO_SONY_BTF_MPX is not set

#
# RDS decoders
#
# CONFIG_VIDEO_SAA6588 is not set

#
# Video decoders
#
# CONFIG_VIDEO_ADV7180 is not set
# CONFIG_VIDEO_ADV7183 is not set
# CONFIG_VIDEO_ADV748X is not set
# CONFIG_VIDEO_ADV7604 is not set
# CONFIG_VIDEO_ADV7842 is not set
# CONFIG_VIDEO_BT819 is not set
# CONFIG_VIDEO_BT856 is not set
# CONFIG_VIDEO_BT866 is not set
# CONFIG_VIDEO_KS0127 is not set
# CONFIG_VIDEO_ML86V7667 is not set
# CONFIG_VIDEO_SAA7110 is not set
# CONFIG_VIDEO_SAA711X is not set
# CONFIG_VIDEO_TC358743 is not set
# CONFIG_VIDEO_TVP514X is not set
# CONFIG_VIDEO_TVP5150 is not set
# CONFIG_VIDEO_TVP7002 is not set
# CONFIG_VIDEO_TW2804 is not set
# CONFIG_VIDEO_TW9903 is not set
# CONFIG_VIDEO_TW9906 is not set
# CONFIG_VIDEO_TW9910 is not set
# CONFIG_VIDEO_VPX3220 is not set

#
# Video and audio decoders
#
# CONFIG_VIDEO_SAA717X is not set
# CONFIG_VIDEO_CX25840 is not set

#
# Video encoders
#
# CONFIG_VIDEO_SAA7127 is not set
# CONFIG_VIDEO_SAA7185 is not set
# CONFIG_VIDEO_ADV7170 is not set
# CONFIG_VIDEO_ADV7175 is not set
# CONFIG_VIDEO_ADV7343 is not set
# CONFIG_VIDEO_ADV7393 is not set
# CONFIG_VIDEO_ADV7511 is not set
# CONFIG_VIDEO_AD9389B is not set
# CONFIG_VIDEO_AK881X is not set
# CONFIG_VIDEO_THS8200 is not set

#
# Camera sensor devices
#
# CONFIG_VIDEO_IMX258 is not set
# CONFIG_VIDEO_IMX274 is not set
# CONFIG_VIDEO_IMX319 is not set
# CONFIG_VIDEO_IMX355 is not set
# CONFIG_VIDEO_OV2640 is not set
# CONFIG_VIDEO_OV2659 is not set
# CONFIG_VIDEO_OV2680 is not set
# CONFIG_VIDEO_OV2685 is not set
# CONFIG_VIDEO_OV5640 is not set
# CONFIG_VIDEO_OV5645 is not set
# CONFIG_VIDEO_OV5647 is not set
# CONFIG_VIDEO_OV6650 is not set
# CONFIG_VIDEO_OV5670 is not set
# CONFIG_VIDEO_OV5675 is not set
# CONFIG_VIDEO_OV5695 is not set
# CONFIG_VIDEO_OV7251 is not set
# CONFIG_VIDEO_OV772X is not set
# CONFIG_VIDEO_OV7640 is not set
# CONFIG_VIDEO_OV7670 is not set
# CONFIG_VIDEO_OV7740 is not set
# CONFIG_VIDEO_OV8856 is not set
# CONFIG_VIDEO_OV9640 is not set
# CONFIG_VIDEO_OV9650 is not set
# CONFIG_VIDEO_OV13858 is not set
# CONFIG_VIDEO_VS6624 is not set
# CONFIG_VIDEO_MT9M001 is not set
# CONFIG_VIDEO_MT9M032 is not set
# CONFIG_VIDEO_MT9M111 is not set
# CONFIG_VIDEO_MT9P031 is not set
# CONFIG_VIDEO_MT9T001 is not set
# CONFIG_VIDEO_MT9T112 is not set
# CONFIG_VIDEO_MT9V011 is not set
# CONFIG_VIDEO_MT9V032 is not set
# CONFIG_VIDEO_MT9V111 is not set
# CONFIG_VIDEO_SR030PC30 is not set
# CONFIG_VIDEO_NOON010PC30 is not set
# CONFIG_VIDEO_M5MOLS is not set
# CONFIG_VIDEO_RJ54N1 is not set
# CONFIG_VIDEO_S5K6AA is not set
# CONFIG_VIDEO_S5K6A3 is not set
# CONFIG_VIDEO_S5K4ECGX is not set
# CONFIG_VIDEO_S5K5BAF is not set
# CONFIG_VIDEO_SMIAPP is not set
# CONFIG_VIDEO_ET8EK8 is not set
# CONFIG_VIDEO_S5C73M3 is not set

#
# Lens drivers
#
# CONFIG_VIDEO_AD5820 is not set
# CONFIG_VIDEO_AK7375 is not set
# CONFIG_VIDEO_DW9714 is not set
# CONFIG_VIDEO_DW9807_VCM is not set

#
# Flash devices
#
# CONFIG_VIDEO_ADP1653 is not set
# CONFIG_VIDEO_LM3560 is not set
# CONFIG_VIDEO_LM3646 is not set

#
# Video improvement chips
#
# CONFIG_VIDEO_UPD64031A is not set
# CONFIG_VIDEO_UPD64083 is not set

#
# Audio/Video compression chips
#
# CONFIG_VIDEO_SAA6752HS is not set

#
# SDR tuner chips
#

#
# Miscellaneous helper chips
#
# CONFIG_VIDEO_THS7303 is not set
# CONFIG_VIDEO_M52790 is not set
# CONFIG_VIDEO_I2C is not set
# CONFIG_VIDEO_ST_MIPID02 is not set
# end of I2C Encoders, decoders, sensors and other helper chips

#
# SPI helper chips
#
# CONFIG_VIDEO_GS1662 is not set
# end of SPI helper chips

#
# Media SPI Adapters
#
# end of Media SPI Adapters

#
# Customise DVB Frontends
#

#
# Tools to develop new frontends
#
# end of Customise DVB Frontends

CONFIG_VIDEO_ENCODER_DECODER_SUNXI=y
# CONFIG_VIDEO_GOOGLE_DECODER_SUNXI is not set

#
# Graphics support
#
# CONFIG_IMX_IPUV3_CORE is not set
# CONFIG_DRM is not set
# CONFIG_DRM_DP_CEC is not set

#
# ARM devices
#
# end of ARM devices

#
# ACP (Audio CoProcessor) Configuration
#
# end of ACP (Audio CoProcessor) Configuration

#
# Frame buffer Devices
#
CONFIG_FB_CMDLINE=y
CONFIG_FB=y
# CONFIG_FIRMWARE_EDID is not set
# CONFIG_FB_FOREIGN_ENDIAN is not set
# CONFIG_FB_MODE_HELPERS is not set
# CONFIG_FB_TILEBLITTING is not set

#
# Frame buffer hardware drivers
#
# CONFIG_FB_OPENCORES is not set
# CONFIG_FB_S1D13XXX is not set
# CONFIG_FB_SMSCUFX is not set
# CONFIG_FB_UDL is not set
# CONFIG_FB_IBM_GXT4500 is not set
# CONFIG_FB_VIRTUAL is not set
# CONFIG_FB_METRONOME is not set
# CONFIG_FB_SIMPLE is not set
# CONFIG_FB_SSD1307 is not set

#
# Video support for sunxi
#
# CONFIG_FB_CONSOLE_SUNXI is not set
CONFIG_DISP2_SUNXI=y
CONFIG_SUNXI_DISP2_FB_DISABLE_ROTATE=y
# CONFIG_SUNXI_DISP2_FB_ROTATION_SUPPORT is not set
# CONFIG_SUNXI_DISP2_FB_HW_ROTATION_SUPPORT is not set
# CONFIG_SUNXI_DISP2_FB_DECOMPRESS_LZMA is not set
# CONFIG_HDMI_DISP2_SUNXI is not set
# CONFIG_HDMI2_DISP2_SUNXI is not set
# CONFIG_HDMI_EP952_DISP2_SUNXI is not set
# CONFIG_TV_DISP2_SUNXI is not set
# CONFIG_VDPO_DISP2_SUNXI is not set
# CONFIG_EDP_DISP2_SUNXI is not set
# CONFIG_DISP2_SUNXI_BOOT_COLORBAR is not set
# CONFIG_DISP2_SUNXI_DEBUG is not set
# CONFIG_DISP2_SUNXI_COMPOSER is not set
# CONFIG_DISP2_LCD_ESD_DETECT is not set
# CONFIG_LCD_FB is not set
# CONFIG_LCD_FB_ENABLE_DEFERRED_IO is not set

#
# LCD panels select
#
# CONFIG_LCD_SUPPORT_GG1P4062UTSW is not set
# CONFIG_LCD_SUPPORT_DX0960BE40A1 is not set
# CONFIG_LCD_SUPPORT_TFT720X1280 is not set
# CONFIG_LCD_SUPPORT_FD055HD003S is not set
# CONFIG_LCD_SUPPORT_HE0801A068 is not set
# CONFIG_LCD_SUPPORT_ILI9341 is not set
# CONFIG_LCD_SUPPORT_LH219WQ1 is not set
# CONFIG_LCD_SUPPORT_LS029B3SX02 is not set
# CONFIG_LCD_SUPPORT_LT070ME05000 is not set
# CONFIG_LCD_SUPPORT_S6D7AA0X01 is not set
# CONFIG_LCD_SUPPORT_T27P06 is not set
# CONFIG_LCD_SUPPORT_TFT720x1280 is not set
# CONFIG_LCD_SUPPORT_WTQ05027D01 is not set
# CONFIG_LCD_SUPPORT_H245QBN02 is not set
# CONFIG_LCD_SUPPORT_ST7789V is not set
# CONFIG_LCD_SUPPORT_ST7796S is not set
# CONFIG_LCD_SUPPORT_ST7701S is not set
# CONFIG_LCD_SUPPORT_T30P106 is not set
# CONFIG_LCD_SUPPORT_TO20T20000 is not set
# CONFIG_LCD_SUPPORT_FRD450H40014 is not set
# CONFIG_LCD_SUPPORT_S2003T46G is not set
# CONFIG_LCD_SUPPORT_WILLIAMLCD is not set
# CONFIG_LCD_SUPPORT_LQ101R1SX03 is not set
# CONFIG_LCD_SUPPORT_INET_DSI_PANEL is not set
# CONFIG_LCD_SUPPORT_WTL096601G03 is not set
# CONFIG_LCD_SUPPORT_RT13QV005D is not set
# CONFIG_LCD_SUPPORT_ST7789V_CPU is not set
# CONFIG_LCD_SUPPORT_CC08021801_310_800X1280 is not set
# CONFIG_LCD_SUPPORT_JD9366AB_3 is not set
# CONFIG_LCD_SUPPORT_TFT08006 is not set
CONFIG_LCD_SUPPORT_BP101WX1_206=y
CONFIG_LCD_SUPPORT_FX070=y
CONFIG_LCD_SUPPORT_K101IM2QA04=y
CONFIG_LCD_SUPPORT_K101_IM2BYL02_L_800X1280=y
CONFIG_LCD_SUPPORT_K080_IM2HYL802R_800X1280=y
# CONFIG_LCD_SUPPORT_NT35510_MIPI is not set
# CONFIG_LCD_SUPPORT_ST7701S_3SPI is not set
# CONFIG_LCD_SUPPORT_D395T9375V0 is not set
# end of LCD panels select

#
# Display engine feature select
#
CONFIG_DISP2_SUNXI_SUPPORT_SMBL=y
CONFIG_DISP2_SUNXI_SUPPORT_ENAHNCE=y
CONFIG_DISP2_SUNXI_DEVICE_OFF_ON_RELEASE=y
# end of Display engine feature select
# end of Video support for sunxi
# end of Frame buffer Devices

#
# Backlight & LCD device support
#
# CONFIG_LCD_CLASS_DEVICE is not set
# CONFIG_BACKLIGHT_CLASS_DEVICE is not set
# end of Backlight & LCD device support

# CONFIG_LOGO is not set
# end of Graphics support

CONFIG_SOUND=y
CONFIG_SND=y
CONFIG_SND_TIMER=y
CONFIG_SND_PCM=y
CONFIG_SND_DMAENGINE_PCM=y
CONFIG_SND_JACK=y
CONFIG_SND_JACK_INPUT_DEV=y
# CONFIG_SND_MIXER_OSS is not set
CONFIG_SND_PCM_TIMER=y
# CONFIG_SND_HRTIMER is not set
# CONFIG_SND_DYNAMIC_MINORS is not set
# CONFIG_SND_SUPPORT_OLD_API is not set
# CONFIG_SND_PROC_FS is not set
# CONFIG_SND_VERBOSE_PRINTK is not set
# CONFIG_SND_DEBUG is not set
# CONFIG_SND_SEQUENCER is not set
CONFIG_SND_DRIVERS=y
# CONFIG_SND_DUMMY is not set
# CONFIG_SND_ALOOP is not set
# CONFIG_SND_MTPAV is not set
# CONFIG_SND_SERIAL_U16550 is not set
# CONFIG_SND_MPU401 is not set

#
# HD-Audio
#
# end of HD-Audio

CONFIG_SND_HDA_PREALLOC_SIZE=64
# CONFIG_SND_ARM is not set
# CONFIG_SND_SPI is not set
CONFIG_SND_USB=y
# CONFIG_SND_USB_AUDIO is not set
# CONFIG_SND_USB_UA101 is not set
# CONFIG_SND_USB_CAIAQ is not set
# CONFIG_SND_USB_6FIRE is not set
# CONFIG_SND_USB_HIFACE is not set
# CONFIG_SND_BCD2000 is not set
# CONFIG_SND_USB_POD is not set
# CONFIG_SND_USB_PODHD is not set
# CONFIG_SND_USB_TONEPORT is not set
# CONFIG_SND_USB_VARIAX is not set
CONFIG_SND_SOC=y
CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
# CONFIG_SND_SOC_AMD_ACP is not set
# CONFIG_SND_ATMEL_SOC is not set
# CONFIG_SND_DESIGNWARE_I2S is not set

#
# SoC Audio for Freescale CPUs
#

#
# Common SoC Audio options for Freescale CPUs:
#
# CONFIG_SND_SOC_FSL_ASRC is not set
# CONFIG_SND_SOC_FSL_SAI is not set
# CONFIG_SND_SOC_FSL_AUDMIX is not set
# CONFIG_SND_SOC_FSL_SSI is not set
# CONFIG_SND_SOC_FSL_SPDIF is not set
# CONFIG_SND_SOC_FSL_ESAI is not set
# CONFIG_SND_SOC_FSL_MICFIL is not set
# CONFIG_SND_SOC_IMX_AUDMUX is not set
# end of SoC Audio for Freescale CPUs

# CONFIG_SND_I2S_HI6210_I2S is not set
# CONFIG_SND_I2S_HI3660_I2S is not set
# CONFIG_SND_SOC_IMG is not set
# CONFIG_SND_SOC_MTK_BTCVSD is not set
# CONFIG_SND_SOC_SOF_TOPLEVEL is not set

#
# STMicroelectronics STM32 SOC audio support
#
# end of STMicroelectronics STM32 SOC audio support

CONFIG_SND_SUNXI_SOC=y
CONFIG_SND_SUNXI_SOC_CPUDAI=y
CONFIG_SND_SUN8IW20_CODEC=y

#
# Allwinner SoC Audio support
#
CONFIG_SND_SUNXI_SOC_SUN8IW20_CODEC=y
CONFIG_SND_SUNXI_SOC_SIMPLE_CARD=y
CONFIG_SND_SUNXI_SOC_DAUDIO=y
# CONFIG_SND_SUNXI_SOC_DAUDIO_ASRC is not set
# CONFIG_SND_SUNXI_SOC_SUNXI_HDMIAUDIO is not set
CONFIG_SND_SUNXI_SOC_SPDIF=y
# CONFIG_SND_SUNXI_SOC_SPDIF_RX_IEC61937 is not set
CONFIG_SND_SUNXI_SOC_DMIC=y
# CONFIG_SUNXI_AUDIO_DEBUG is not set
# CONFIG_SUNXI_RX_SYNC is not set
# end of Allwinner SoC Audio support

# CONFIG_SND_SUNXI_RPAF is not set

#
# Allwinner SoC Audio support V2
#
# CONFIG_SND_SOC_SUNXI_SPDIF is not set
# CONFIG_SND_SOC_SUNXI_DMIC is not set
# CONFIG_SND_SOC_SUNXI_DAUDIO is not set
# CONFIG_SND_SOC_SUNXI_COMPONENTS is not set
# end of Allwinner SoC Audio support V2

# CONFIG_SND_SOC_XILINX_I2S is not set
# CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set
# CONFIG_SND_SOC_XILINX_SPDIF is not set
# CONFIG_SND_SOC_XTFPGA_I2S is not set
# CONFIG_ZX_TDM is not set
CONFIG_SND_SOC_I2C_AND_SPI=y

#
# CODEC drivers
#
# CONFIG_SND_SOC_AC97_CODEC is not set
# CONFIG_SND_SOC_ADAU1701 is not set
# CONFIG_SND_SOC_ADAU1761_I2C is not set
# CONFIG_SND_SOC_ADAU1761_SPI is not set
# CONFIG_SND_SOC_ADAU7002 is not set
# CONFIG_SND_SOC_AK4104 is not set
# CONFIG_SND_SOC_AK4118 is not set
# CONFIG_SND_SOC_AK4458 is not set
# CONFIG_SND_SOC_AK4554 is not set
# CONFIG_SND_SOC_AK4613 is not set
# CONFIG_SND_SOC_AK4642 is not set
# CONFIG_SND_SOC_AK5386 is not set
# CONFIG_SND_SOC_AK5558 is not set
# CONFIG_SND_SOC_ALC5623 is not set
# CONFIG_SND_SOC_BD28623 is not set
# CONFIG_SND_SOC_BT_SCO is not set
# CONFIG_SND_SOC_CS35L32 is not set
# CONFIG_SND_SOC_CS35L33 is not set
# CONFIG_SND_SOC_CS35L34 is not set
# CONFIG_SND_SOC_CS35L35 is not set
# CONFIG_SND_SOC_CS35L36 is not set
# CONFIG_SND_SOC_CS42L42 is not set
# CONFIG_SND_SOC_CS42L51_I2C is not set
# CONFIG_SND_SOC_CS42L52 is not set
# CONFIG_SND_SOC_CS42L56 is not set
# CONFIG_SND_SOC_CS42L73 is not set
# CONFIG_SND_SOC_CS4265 is not set
# CONFIG_SND_SOC_CS4270 is not set
# CONFIG_SND_SOC_CS4271_I2C is not set
# CONFIG_SND_SOC_CS4271_SPI is not set
# CONFIG_SND_SOC_CS42XX8_I2C is not set
# CONFIG_SND_SOC_CS43130 is not set
# CONFIG_SND_SOC_CS4341 is not set
# CONFIG_SND_SOC_CS4349 is not set
# CONFIG_SND_SOC_CS53L30 is not set
# CONFIG_SND_SOC_CX2072X is not set
CONFIG_SND_SOC_DMIC=y
# CONFIG_SND_SOC_ES7134 is not set
# CONFIG_SND_SOC_ES7241 is not set
# CONFIG_SND_SOC_ES8316 is not set
# CONFIG_SND_SOC_ES8328_I2C is not set
# CONFIG_SND_SOC_ES8328_SPI is not set
# CONFIG_SND_SOC_GTM601 is not set
# CONFIG_SND_SOC_INNO_RK3036 is not set
# CONFIG_SND_SOC_MAX98088 is not set
# CONFIG_SND_SOC_MAX98357A is not set
# CONFIG_SND_SOC_MAX98504 is not set
# CONFIG_SND_SOC_MAX9867 is not set
# CONFIG_SND_SOC_MAX98927 is not set
# CONFIG_SND_SOC_MAX98373 is not set
# CONFIG_SND_SOC_MAX9860 is not set
# CONFIG_SND_SOC_MSM8916_WCD_DIGITAL is not set
# CONFIG_SND_SOC_PCM1681 is not set
# CONFIG_SND_SOC_PCM1789_I2C is not set
# CONFIG_SND_SOC_PCM179X_I2C is not set
# CONFIG_SND_SOC_PCM179X_SPI is not set
# CONFIG_SND_SOC_PCM186X_I2C is not set
# CONFIG_SND_SOC_PCM186X_SPI is not set
# CONFIG_SND_SOC_PCM3060_I2C is not set
# CONFIG_SND_SOC_PCM3060_SPI is not set
# CONFIG_SND_SOC_PCM3168A_I2C is not set
# CONFIG_SND_SOC_PCM3168A_SPI is not set
# CONFIG_SND_SOC_PCM512x_I2C is not set
# CONFIG_SND_SOC_PCM512x_SPI is not set
# CONFIG_SND_SOC_RK3328 is not set
# CONFIG_SND_SOC_RT5616 is not set
# CONFIG_SND_SOC_RT5631 is not set
# CONFIG_SND_SOC_SGTL5000 is not set
# CONFIG_SND_SOC_SIMPLE_AMPLIFIER is not set
# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set
# CONFIG_SND_SOC_SPDIF is not set
# CONFIG_SND_SOC_SSM2305 is not set
# CONFIG_SND_SOC_SSM2602_SPI is not set
# CONFIG_SND_SOC_SSM2602_I2C is not set
# CONFIG_SND_SOC_SSM4567 is not set
# CONFIG_SND_SOC_STA32X is not set
# CONFIG_SND_SOC_STA350 is not set
# CONFIG_SND_SOC_STI_SAS is not set
# CONFIG_SND_SOC_TAS2552 is not set
# CONFIG_SND_SOC_TAS5086 is not set
# CONFIG_SND_SOC_TAS571X is not set
# CONFIG_SND_SOC_TAS5720 is not set
# CONFIG_SND_SOC_TAS6424 is not set
# CONFIG_SND_SOC_TDA7419 is not set
# CONFIG_SND_SOC_TFA9879 is not set
# CONFIG_SND_SOC_TLV320AIC23_I2C is not set
# CONFIG_SND_SOC_TLV320AIC23_SPI is not set
# CONFIG_SND_SOC_TLV320AIC31XX is not set
# CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set
# CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set
# CONFIG_SND_SOC_TLV320AIC3X is not set
# CONFIG_SND_SOC_TS3A227E is not set
# CONFIG_SND_SOC_TSCS42XX is not set
# CONFIG_SND_SOC_TSCS454 is not set
# CONFIG_SND_SOC_UDA1334 is not set
# CONFIG_SND_SOC_WM8510 is not set
# CONFIG_SND_SOC_WM8523 is not set
# CONFIG_SND_SOC_WM8524 is not set
# CONFIG_SND_SOC_WM8580 is not set
# CONFIG_SND_SOC_WM8711 is not set
# CONFIG_SND_SOC_WM8728 is not set
# CONFIG_SND_SOC_WM8731 is not set
# CONFIG_SND_SOC_WM8737 is not set
# CONFIG_SND_SOC_WM8741 is not set
# CONFIG_SND_SOC_WM8750 is not set
# CONFIG_SND_SOC_WM8753 is not set
# CONFIG_SND_SOC_WM8770 is not set
# CONFIG_SND_SOC_WM8776 is not set
# CONFIG_SND_SOC_WM8782 is not set
# CONFIG_SND_SOC_WM8804_I2C is not set
# CONFIG_SND_SOC_WM8804_SPI is not set
# CONFIG_SND_SOC_WM8903 is not set
# CONFIG_SND_SOC_WM8904 is not set
# CONFIG_SND_SOC_WM8960 is not set
# CONFIG_SND_SOC_WM8962 is not set
# CONFIG_SND_SOC_WM8974 is not set
# CONFIG_SND_SOC_WM8978 is not set
# CONFIG_SND_SOC_WM8985 is not set
# CONFIG_SND_SOC_ZX_AUD96P22 is not set
# CONFIG_SND_SOC_MAX9759 is not set
# CONFIG_SND_SOC_MT6351 is not set
# CONFIG_SND_SOC_MT6358 is not set
# CONFIG_SND_SOC_NAU8540 is not set
# CONFIG_SND_SOC_NAU8810 is not set
# CONFIG_SND_SOC_NAU8822 is not set
# CONFIG_SND_SOC_NAU8824 is not set
# CONFIG_SND_SOC_TPA6130A2 is not set
# CONFIG_SND_SOC_AC107 is not set
# CONFIG_SND_SOC_AC108 is not set
# CONFIG_SND_SOC_TD100 is not set
# end of CODEC drivers

CONFIG_SND_SIMPLE_CARD_UTILS=y
# CONFIG_SND_SIMPLE_CARD is not set
# CONFIG_SND_AUDIO_GRAPH_CARD is not set

#
# HID support
#
# CONFIG_HID is not set

#
# USB HID support
#
# CONFIG_USB_HID is not set
# CONFIG_HID_PID is not set

#
# USB HID Boot Protocol drivers
#
# CONFIG_USB_KBD is not set
# CONFIG_USB_MOUSE is not set
# end of USB HID Boot Protocol drivers
# end of USB HID support

#
# I2C HID support
#
# CONFIG_I2C_HID is not set
# end of I2C HID support
# end of HID support

CONFIG_USB_OHCI_LITTLE_ENDIAN=y
CONFIG_USB_SUPPORT=y
CONFIG_USB_COMMON=y
# CONFIG_USB_LED_TRIG is not set
# CONFIG_USB_ULPI_BUS is not set
# CONFIG_USB_CONN_GPIO is not set
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB=y
# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set

#
# Miscellaneous USB options
#
CONFIG_USB_DEFAULT_PERSIST=y
# CONFIG_USB_DYNAMIC_MINORS is not set
# CONFIG_USB_OTG is not set
# CONFIG_USB_OTG_WHITELIST is not set
# CONFIG_USB_OTG_BLACKLIST_HUB is not set
# CONFIG_USB_LEDS_TRIGGER_USBPORT is not set
CONFIG_USB_AUTOSUSPEND_DELAY=2
# CONFIG_USB_MON is not set

#
# USB Host Controller Drivers
#
# CONFIG_USB_C67X00_HCD is not set
# CONFIG_USB_XHCI_HCD is not set
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_ROOT_HUB_TT=y
CONFIG_USB_EHCI_TT_NEWSCHED=y
# CONFIG_USB_EHCI_FSL is not set
CONFIG_USB_EHCI_HCD_SUNXI=y
# CONFIG_USB_EHCI_HCD_PLATFORM is not set
# CONFIG_USB_OXU210HP_HCD is not set
# CONFIG_USB_ISP116X_HCD is not set
# CONFIG_USB_FOTG210_HCD is not set
# CONFIG_USB_MAX3421_HCD is not set
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_HCD_SUNXI=y
# CONFIG_USB_OHCI_HCD_PLATFORM is not set
# CONFIG_USB_SL811_HCD is not set
# CONFIG_USB_R8A66597_HCD is not set
# CONFIG_USB_HCD_TEST_MODE is not set
CONFIG_USB_SUNXI_HCD=y
CONFIG_USB_SUNXI_HCI=y
CONFIG_USB_SUNXI_EHCI0=y
CONFIG_USB_SUNXI_EHCI1=y
CONFIG_USB_SUNXI_OHCI0=y
CONFIG_USB_SUNXI_OHCI1=y

#
# USB Device Class drivers
#
# CONFIG_USB_ACM is not set
# CONFIG_USB_PRINTER is not set
# CONFIG_USB_WDM is not set
# CONFIG_USB_TMC is not set

#
# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
#

#
# also be needed; see USB_STORAGE Help for more info
#
CONFIG_USB_STORAGE=m
# CONFIG_USB_STORAGE_DEBUG is not set
# CONFIG_USB_STORAGE_REALTEK is not set
# CONFIG_USB_STORAGE_DATAFAB is not set
# CONFIG_USB_STORAGE_FREECOM is not set
# CONFIG_USB_STORAGE_ISD200 is not set
# CONFIG_USB_STORAGE_USBAT is not set
# CONFIG_USB_STORAGE_SDDR09 is not set
# CONFIG_USB_STORAGE_SDDR55 is not set
# CONFIG_USB_STORAGE_JUMPSHOT is not set
# CONFIG_USB_STORAGE_ALAUDA is not set
# CONFIG_USB_STORAGE_ONETOUCH is not set
# CONFIG_USB_STORAGE_KARMA is not set
# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
# CONFIG_USB_STORAGE_ENE_UB6250 is not set
# CONFIG_USB_UAS is not set

#
# USB Imaging devices
#
# CONFIG_USB_MDC800 is not set
# CONFIG_USB_MICROTEK is not set
# CONFIG_USBIP_CORE is not set
# CONFIG_USB_CDNS3 is not set
# CONFIG_USB_MUSB_HDRC is not set
# CONFIG_USB_DWC3 is not set
# CONFIG_USB_DWC2 is not set
# CONFIG_USB_CHIPIDEA is not set
# CONFIG_USB_ISP1760 is not set

#
# USB port drivers
#
# CONFIG_USB_SERIAL is not set

#
# USB Miscellaneous drivers
#
# CONFIG_USB_EMI62 is not set
# CONFIG_USB_EMI26 is not set
# CONFIG_USB_ADUTUX is not set
# CONFIG_USB_SEVSEG is not set
# CONFIG_USB_LEGOTOWER is not set
# CONFIG_USB_LCD is not set
# CONFIG_USB_CYPRESS_CY7C63 is not set
# CONFIG_USB_CYTHERM is not set
# CONFIG_USB_IDMOUSE is not set
# CONFIG_USB_FTDI_ELAN is not set
# CONFIG_USB_APPLEDISPLAY is not set
# CONFIG_USB_SISUSBVGA is not set
# CONFIG_USB_LD is not set
# CONFIG_USB_TRANCEVIBRATOR is not set
# CONFIG_USB_IOWARRIOR is not set
# CONFIG_USB_TEST is not set
# CONFIG_USB_EHSET_TEST_FIXTURE is not set
# CONFIG_USB_ISIGHTFW is not set
# CONFIG_USB_YUREX is not set
# CONFIG_USB_EZUSB_FX2 is not set
# CONFIG_USB_HUB_USB251XB is not set
# CONFIG_USB_HSIC_USB3503 is not set
# CONFIG_USB_HSIC_USB4604 is not set
# CONFIG_USB_LINK_LAYER_TEST is not set

#
# USB Physical Layer drivers
#
# CONFIG_NOP_USB_XCEIV is not set
# CONFIG_USB_GPIO_VBUS is not set
# CONFIG_USB_ISP1301 is not set
# CONFIG_USB_ULPI is not set
# end of USB Physical Layer drivers

CONFIG_USB_GADGET=y
# CONFIG_USB_GADGET_DEBUG is not set
# CONFIG_USB_GADGET_DEBUG_FILES is not set
# CONFIG_USB_GADGET_DEBUG_FS is not set
CONFIG_USB_GADGET_VBUS_DRAW=2
CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
# CONFIG_U_SERIAL_CONSOLE is not set

#
# USB Peripheral Controller
#
# CONFIG_USB_FUSB300 is not set
# CONFIG_USB_FOTG210_UDC is not set
# CONFIG_USB_GR_UDC is not set
# CONFIG_USB_R8A66597 is not set
# CONFIG_USB_PXA27X is not set
# CONFIG_USB_MV_UDC is not set
# CONFIG_USB_MV_U3D is not set
# CONFIG_USB_SNP_UDC_PLAT is not set
# CONFIG_USB_M66592 is not set
# CONFIG_USB_BDC_UDC is not set
# CONFIG_USB_NET2272 is not set
CONFIG_USB_SUNXI_UDC0=y
# CONFIG_USB_GADGET_XILINX is not set
# CONFIG_USB_DUMMY_HCD is not set
# end of USB Peripheral Controller

CONFIG_USB_LIBCOMPOSITE=y
CONFIG_USB_U_SERIAL=y
CONFIG_USB_F_SERIAL=y
CONFIG_USB_F_FS=y
CONFIG_USB_CONFIGFS=y
CONFIG_USB_CONFIGFS_UEVENT=y
CONFIG_USB_CONFIGFS_SERIAL=y
# CONFIG_USB_CONFIGFS_ACM is not set
# CONFIG_USB_CONFIGFS_OBEX is not set
# CONFIG_USB_CONFIGFS_NCM is not set
# CONFIG_USB_CONFIGFS_ECM is not set
# CONFIG_USB_CONFIGFS_ECM_SUBSET is not set
# CONFIG_USB_CONFIGFS_RNDIS is not set
# CONFIG_USB_CONFIGFS_EEM is not set
# CONFIG_USB_CONFIGFS_MASS_STORAGE is not set
# CONFIG_USB_CONFIGFS_F_LB_SS is not set
CONFIG_USB_CONFIGFS_F_FS=y
# CONFIG_USB_CONFIGFS_F_AUDIO_SRC is not set
# CONFIG_USB_CONFIGFS_F_UAC1 is not set
# CONFIG_USB_CONFIGFS_F_UAC1_LEGACY is not set
# CONFIG_USB_CONFIGFS_F_UAC2 is not set
# CONFIG_USB_CONFIGFS_F_MIDI is not set
# CONFIG_USB_CONFIGFS_F_HID is not set
# CONFIG_USB_CONFIGFS_F_UVC is not set
# CONFIG_USB_CONFIGFS_F_PRINTER is not set
CONFIG_USB_SUNXI_USB=y
CONFIG_USB_SUNXI_USB_MANAGER=y
# CONFIG_USB_SUNXI_USB_DEBUG is not set
CONFIG_USB_SUNXI_USB_ADB=y
CONFIG_TYPEC=y
# CONFIG_TYPEC_TCPM is not set
# CONFIG_TYPEC_UCSI is not set
# CONFIG_TYPEC_TPS6598X is not set

#
# USB Type-C Multiplexer/DeMultiplexer Switch support
#
# CONFIG_TYPEC_MUX_PI3USB30532 is not set
# end of USB Type-C Multiplexer/DeMultiplexer Switch support

#
# USB Type-C Alternate Mode drivers
#
# CONFIG_TYPEC_DP_ALTMODE is not set
# end of USB Type-C Alternate Mode drivers

CONFIG_USB_ROLE_SWITCH=y
CONFIG_MMC=y
CONFIG_PWRSEQ_EMMC=y
CONFIG_PWRSEQ_SIMPLE=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_BLOCK_MINORS=8
# CONFIG_SDIO_UART is not set
# CONFIG_MMC_TEST is not set

#
# MMC/SD/SDIO Host Controller Drivers
#
# CONFIG_MMC_DEBUG is not set
# CONFIG_MMC_SDHCI is not set
# CONFIG_MMC_SPI is not set
# CONFIG_MMC_DW is not set
# CONFIG_MMC_VUB300 is not set
# CONFIG_MMC_USHC is not set
# CONFIG_MMC_USDHI6ROL0 is not set
CONFIG_MMC_SUNXI=y
CONFIG_MMC_SUNXI_V4P1X=y
CONFIG_MMC_SUNXI_V4P00X=y
CONFIG_MMC_SUNXI_V4P10X=y
CONFIG_MMC_SUNXI_V4P5X=y
CONFIG_MMC_SUNXI_V5P3X=y
# CONFIG_MMC_CQHCI is not set
# CONFIG_MMC_HSQ is not set
# CONFIG_MMC_MTK is not set
# CONFIG_MEMSTICK is not set
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
# CONFIG_LEDS_CLASS_FLASH is not set
# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set

#
# LED drivers
#
# CONFIG_LEDS_AN30259A is not set
# CONFIG_LEDS_BCM6328 is not set
# CONFIG_LEDS_BCM6358 is not set
# CONFIG_LEDS_CR0014114 is not set
# CONFIG_LEDS_LM3530 is not set
# CONFIG_LEDS_LM3532 is not set
# CONFIG_LEDS_LM3642 is not set
# CONFIG_LEDS_LM3692X is not set
# CONFIG_LEDS_PCA9532 is not set
# CONFIG_LEDS_GPIO is not set
# CONFIG_LEDS_LP3944 is not set
# CONFIG_LEDS_LP3952 is not set
# CONFIG_LEDS_LP5521 is not set
# CONFIG_LEDS_LP5523 is not set
# CONFIG_LEDS_LP5562 is not set
# CONFIG_LEDS_LP8501 is not set
# CONFIG_LEDS_LP8860 is not set
# CONFIG_LEDS_PCA955X is not set
# CONFIG_LEDS_PCA963X is not set
# CONFIG_LEDS_DAC124S085 is not set
# CONFIG_LEDS_PWM is not set
# CONFIG_LEDS_REGULATOR is not set
# CONFIG_LEDS_BD2802 is not set
# CONFIG_LEDS_LT3593 is not set
# CONFIG_LEDS_TCA6507 is not set
# CONFIG_LEDS_TLC591XX is not set
# CONFIG_LEDS_LM355x is not set
# CONFIG_LEDS_IS31FL319X is not set
# CONFIG_LEDS_IS31FL32XX is not set

#
# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM)
#
# CONFIG_LEDS_BLINKM is not set
# CONFIG_LEDS_SYSCON is not set
# CONFIG_LEDS_MLXREG is not set
# CONFIG_LEDS_USER is not set
# CONFIG_LEDS_SPI_BYTE is not set
# CONFIG_LEDS_TI_LMU_COMMON is not set
CONFIG_LEDS_SUNXI=y
# CONFIG_MATRIX_LEDS_SUNXI is not set

#
# LED Triggers
#
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=y
# CONFIG_LEDS_TRIGGER_ONESHOT is not set
# CONFIG_LEDS_TRIGGER_MTD is not set
# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set
# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
# CONFIG_LEDS_TRIGGER_CPU is not set
# CONFIG_LEDS_TRIGGER_ACTIVITY is not set
# CONFIG_LEDS_TRIGGER_GPIO is not set
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y

#
# iptables trigger is under Netfilter config (LED target)
#
# CONFIG_LEDS_TRIGGER_TRANSIENT is not set
# CONFIG_LEDS_TRIGGER_CAMERA is not set
# CONFIG_LEDS_TRIGGER_PANIC is not set
CONFIG_LEDS_TRIGGER_NETDEV=y
# CONFIG_LEDS_TRIGGER_PATTERN is not set
# CONFIG_LEDS_TRIGGER_AUDIO is not set
# CONFIG_ACCESSIBILITY is not set
# CONFIG_INFINIBAND is not set
CONFIG_EDAC_ATOMIC_SCRUB=y
CONFIG_EDAC_SUPPORT=y
CONFIG_RTC_LIB=y
# CONFIG_RTC_CLASS is not set
CONFIG_DMADEVICES=y
# CONFIG_DMADEVICES_DEBUG is not set

#
# DMA Devices
#
CONFIG_DMA_ENGINE=y
CONFIG_DMA_VIRTUAL_CHANNELS=y
CONFIG_DMA_OF=y
# CONFIG_ALTERA_MSGDMA is not set
CONFIG_DMA_SUN6I=y
# CONFIG_DW_AXI_DMAC is not set
# CONFIG_FSL_EDMA is not set
# CONFIG_FSL_QDMA is not set
# CONFIG_INTEL_IDMA64 is not set
# CONFIG_NBPFAXI_DMA is not set
# CONFIG_QCOM_HIDMA_MGMT is not set
# CONFIG_QCOM_HIDMA is not set
# CONFIG_DW_DMAC is not set

#
# DMA Clients
#
# CONFIG_ASYNC_TX_DMA is not set
# CONFIG_DMATEST is not set

#
# DMABUF options
#
CONFIG_SYNC_FILE=y
CONFIG_SW_SYNC=y
CONFIG_UDMABUF=y
CONFIG_DMABUF_SELFTESTS=y
# end of DMABUF options

# CONFIG_AUXDISPLAY is not set
# CONFIG_UIO is not set
# CONFIG_VFIO is not set
# CONFIG_VIRT_DRIVERS is not set
# CONFIG_VIRTIO_MENU is not set

#
# Microsoft Hyper-V guest support
#
# end of Microsoft Hyper-V guest support

# CONFIG_GREYBUS is not set
CONFIG_STAGING=y
# CONFIG_PRISM2_USB is not set
# CONFIG_COMEDI is not set
# CONFIG_RTLLIB is not set
# CONFIG_RTL8723BS is not set
# CONFIG_R8712U is not set
# CONFIG_R8188EU is not set

#
# Speakup console speech
#
# end of Speakup console speech

# CONFIG_STAGING_MEDIA is not set

#
# Android
#
# CONFIG_ASHMEM is not set
# CONFIG_ANDROID_TIMED_OUTPUT is not set
CONFIG_ION=y
CONFIG_ION_SYSTEM_HEAP=y
CONFIG_ION_CMA_HEAP=y
# end of Android

# CONFIG_STAGING_BOARD is not set
# CONFIG_LTE_GDM724X is not set
# CONFIG_GS_FPGABOOT is not set
# CONFIG_UNISYSSPAR is not set
# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set
# CONFIG_FB_TFT is not set
# CONFIG_WILC1000_SDIO is not set
# CONFIG_WILC1000_SPI is not set
# CONFIG_MOST is not set
# CONFIG_KS7010 is not set
# CONFIG_PI433 is not set

#
# Gasket devices
#
# end of Gasket devices

# CONFIG_XIL_AXIS_FIFO is not set
# CONFIG_FIELDBUS_DEV is not set
# CONFIG_USB_WUSB_CBAF is not set
# CONFIG_UWB is not set
CONFIG_EXFAT_FS=y
CONFIG_EXFAT_DONT_MOUNT_VFAT=y
CONFIG_EXFAT_DISCARD=y
CONFIG_EXFAT_DELAYED_SYNC=y
CONFIG_EXFAT_KERNEL_DEBUG=y
CONFIG_EXFAT_DEBUG_MSG=y
CONFIG_EXFAT_DEFAULT_CODEPAGE=437
CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
# CONFIG_GOLDFISH is not set
# CONFIG_MFD_CROS_EC is not set
# CONFIG_CHROME_PLATFORMS is not set
# CONFIG_MELLANOX_PLATFORM is not set
CONFIG_CLKDEV_LOOKUP=y
CONFIG_HAVE_CLK_PREPARE=y
CONFIG_COMMON_CLK=y

#
# Common Clock Framework
#
# CONFIG_COMMON_CLK_DEBUG is not set
# CONFIG_CLK_HSDK is not set
# CONFIG_COMMON_CLK_MAX9485 is not set
# CONFIG_COMMON_CLK_SI5341 is not set
# CONFIG_COMMON_CLK_SI5351 is not set
# CONFIG_COMMON_CLK_SI514 is not set
# CONFIG_COMMON_CLK_SI544 is not set
# CONFIG_COMMON_CLK_SI570 is not set
# CONFIG_COMMON_CLK_CDCE706 is not set
# CONFIG_COMMON_CLK_CDCE925 is not set
# CONFIG_COMMON_CLK_CS2000_CP is not set
# CONFIG_CLK_QORIQ is not set
# CONFIG_COMMON_CLK_PWM is not set
# CONFIG_COMMON_CLK_VC5 is not set
# CONFIG_COMMON_CLK_FIXED_MMIO is not set
CONFIG_CLK_SUNXI=y
# CONFIG_CLK_SUNXI_CLOCKS is not set
# CONFIG_CLK_SUNXI_DDR is not set
# CONFIG_CLK_SUNXI_PRCM_SUN6I is not set
# CONFIG_CLK_SUNXI_PRCM_SUN8I is not set
# CONFIG_CLK_SUNXI_PRCM_SUN9I is not set
CONFIG_SUNXI_CCU=y
CONFIG_SUN8IW20_CCU=y
CONFIG_SUN8IW20_R_CCU=y
# CONFIG_SUN8I_A83T_CCU is not set
# CONFIG_SUN8I_DE2_CCU is not set
# CONFIG_SUN8I_R_CCU is not set
CONFIG_SUNXI_RTC_CCU=y
# end of Common Clock Framework

# CONFIG_HWSPINLOCK is not set
# CONFIG_HWSPINLOCK_SUNXI is not set

#
# Clock Source drivers
#
CONFIG_TIMER_OF=y
CONFIG_TIMER_PROBE=y
CONFIG_CLKSRC_MMIO=y
CONFIG_SUN4I_TIMER=y
# CONFIG_SUN50I_TIMER is not set
# CONFIG_SUNXI_TIMER is not set
# CONFIG_SUNXI_TIMER_TEST is not set
CONFIG_ARM_ARCH_TIMER=y
# CONFIG_ARM_ARCH_TIMER_EVTSTREAM is not set
# CONFIG_MTK_TIMER is not set
# end of Clock Source drivers

# CONFIG_MAILBOX is not set
CONFIG_IOMMU_IOVA=y
CONFIG_IOMMU_API=y
# CONFIG_IOMMU_LIMIT_IOVA_ALIGNMENT is not set
CONFIG_IOMMU_SUPPORT=y

#
# Generic IOMMU Pagetable Support
#
# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
# end of Generic IOMMU Pagetable Support

# CONFIG_IOMMU_DEBUGFS is not set
# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
CONFIG_OF_IOMMU=y
CONFIG_IOMMU_DMA=y
# CONFIG_ARM_SMMU is not set
CONFIG_SUNXI_IOMMU=y
CONFIG_SUNXI_IOMMU_DEBUG=y
CONFIG_SUNXI_IOMMU_TESTS=y

#
# Remoteproc drivers
#
# CONFIG_REMOTEPROC is not set
# end of Remoteproc drivers

#
# Rpmsg drivers
#
# CONFIG_RPMSG_SUNXI_AMP is not set
# CONFIG_RPMSG_DSP_STANDBY is not set
# CONFIG_RPMSG_VIRTIO is not set
# CONFIG_RPMSG_SUNXI_TTY is not set
# CONFIG_RPMSG_SUNXI_CLIENT_SAMPLE is not set
# end of Rpmsg drivers

#
# Rpbuf drivers
#
# CONFIG_RPBUF_DEV is not set

#
# Service
#
# CONFIG_RPBUF_SERVICE_RPMSG is not set

#
# Controller
#
# CONFIG_RPBUF_CONTROLLER_SUNXI is not set

#
# Sample
#
# CONFIG_RPBUF_SAMPLE_SUNXI is not set
# end of Rpbuf drivers

# CONFIG_SOUNDWIRE is not set

#
# SOC (System On Chip) specific Drivers
#

#
# Amlogic SoC drivers
#
# end of Amlogic SoC drivers

#
# Aspeed SoC drivers
#
# end of Aspeed SoC drivers

#
# Broadcom SoC drivers
#
# CONFIG_SOC_BRCMSTB is not set
# end of Broadcom SoC drivers

#
# NXP/Freescale QorIQ SoC drivers
#
# end of NXP/Freescale QorIQ SoC drivers

#
# i.MX SoC drivers
#
# end of i.MX SoC drivers

#
# Qualcomm SoC drivers
#
# end of Qualcomm SoC drivers

# CONFIG_SUNXI_SRAM is not set
CONFIG_SUNXI_PM_DOMAINS=y
# CONFIG_SUNXI_POWER_DOMAIN_TEST is not set
CONFIG_SUNXI_SID=y
# CONFIG_SUNXI_RISCV_SUSPEND is not set
# CONFIG_PM_TRACE_NVMEM is not set
# CONFIG_SOC_TI is not set

#
# Xilinx SoC drivers
#
# CONFIG_XILINX_VCU is not set
# end of Xilinx SoC drivers
# end of SOC (System On Chip) specific Drivers

# CONFIG_PM_DEVFREQ is not set
# CONFIG_EXTCON is not set
# CONFIG_MEMORY is not set
# CONFIG_IIO is not set
CONFIG_PWM=y
CONFIG_PWM_SYSFS=y
# CONFIG_PWM_FSL_FTM is not set
# CONFIG_PWM_PCA9685 is not set
# CONFIG_PWM_SUN4I is not set
CONFIG_PWM_SUNXI_GROUP=y
# CONFIG_DSP_DEBUG is not set

#
# IRQ chip support
#
CONFIG_IRQCHIP=y
CONFIG_ARM_GIC=y
CONFIG_ARM_GIC_MAX_NR=1
# CONFIG_AL_FIC is not set
# CONFIG_SUNXI_WAKEUPGEN is not set
# CONFIG_SUN8I_NMI is not set
# end of IRQ chip support

# CONFIG_IPACK_BUS is not set
CONFIG_ARCH_HAS_RESET_CONTROLLER=y
CONFIG_RESET_CONTROLLER=y
CONFIG_RESET_SIMPLE=y
CONFIG_RESET_SUNXI=y
# CONFIG_RESET_TI_SYSCON is not set

#
# PHY Subsystem
#
# CONFIG_GENERIC_PHY is not set
# CONFIG_PHY_SUN6I_MIPI_DPHY is not set
# CONFIG_PHY_SUN9I_USB is not set
# CONFIG_BCM_KONA_USB2_PHY is not set
# CONFIG_PHY_CADENCE_DP is not set
# CONFIG_PHY_CADENCE_DPHY is not set
# CONFIG_PHY_CADENCE_SIERRA is not set
# CONFIG_PHY_FSL_IMX8MQ_USB is not set
# CONFIG_PHY_MIXEL_MIPI_DPHY is not set
# CONFIG_PHY_PXA_28NM_HSIC is not set
# CONFIG_PHY_PXA_28NM_USB2 is not set
# CONFIG_PHY_MAPPHONE_MDM6600 is not set
# CONFIG_PHY_OCELOT_SERDES is not set
# end of PHY Subsystem

# CONFIG_POWERCAP is not set
# CONFIG_MCB is not set

#
# Performance monitor support
#
# CONFIG_ARM_CCI_PMU is not set
# CONFIG_ARM_CCN is not set
# CONFIG_ARM_PMU is not set
# end of Performance monitor support

# CONFIG_RAS is not set

#
# Android
#
CONFIG_ANDROID=y
# CONFIG_ANDROID_BINDER_IPC is not set
# end of Android

# CONFIG_DAX is not set
CONFIG_NVMEM=y
CONFIG_NVMEM_SYSFS=y
# CONFIG_NVMEM_SUNXI_SID is not set

#
# HW tracing support
#
# CONFIG_STM is not set
# CONFIG_INTEL_TH is not set
# end of HW tracing support

# CONFIG_FPGA is not set
# CONFIG_FSI is not set
# CONFIG_TEE is not set
CONFIG_PM_OPP=y
# CONFIG_SIOX is not set
# CONFIG_SLIMBUS is not set
# CONFIG_INTERCONNECT is not set
# CONFIG_COUNTER is not set
# end of Device Drivers

#
# File systems
#
CONFIG_DCACHE_WORD_ACCESS=y
# CONFIG_VALIDATE_FS_PARSER is not set
# CONFIG_EXT2_FS is not set
# CONFIG_EXT3_FS is not set
# CONFIG_EXT4_FS is not set
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
# CONFIG_XFS_FS is not set
# CONFIG_GFS2_FS is not set
# CONFIG_OCFS2_FS is not set
# CONFIG_BTRFS_FS is not set
# CONFIG_NILFS2_FS is not set
# CONFIG_F2FS_FS is not set
CONFIG_FS_POSIX_ACL=y
CONFIG_EXPORTFS=y
# CONFIG_EXPORTFS_BLOCK_OPS is not set
CONFIG_FILE_LOCKING=y
CONFIG_MANDATORY_FILE_LOCKING=y
# CONFIG_FS_ENCRYPTION is not set
# CONFIG_FS_VERITY is not set
CONFIG_FSNOTIFY=y
CONFIG_DNOTIFY=y
CONFIG_INOTIFY_USER=y
# CONFIG_FANOTIFY is not set
# CONFIG_QUOTA is not set
# CONFIG_AUTOFS4_FS is not set
# CONFIG_AUTOFS_FS is not set
# CONFIG_FUSE_FS is not set
CONFIG_OVERLAY_FS=y
# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set
CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y
# CONFIG_OVERLAY_FS_INDEX is not set
# CONFIG_OVERLAY_FS_XINO_AUTO is not set
# CONFIG_OVERLAY_FS_METACOPY is not set
# CONFIG_INCREMENTAL_FS is not set

#
# Caches
#
# CONFIG_FSCACHE is not set
# end of Caches

#
# CD-ROM/DVD Filesystems
#
# CONFIG_ISO9660_FS is not set
# CONFIG_UDF_FS is not set
# end of CD-ROM/DVD Filesystems

#
# DOS/FAT/NT Filesystems
#
CONFIG_FAT_FS=y
# CONFIG_MSDOS_FS is not set
CONFIG_VFAT_FS=y
CONFIG_FAT_DEFAULT_CODEPAGE=437
CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
CONFIG_FAT_DEFAULT_UTF8=y
CONFIG_NTFS_FS=y
# CONFIG_NTFS_DEBUG is not set
CONFIG_NTFS_RW=y
# end of DOS/FAT/NT Filesystems

#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_PROC_SYSCTL=y
# CONFIG_PROC_PAGE_MONITOR is not set
# CONFIG_PROC_CHILDREN is not set
CONFIG_KERNFS=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_TMPFS_XATTR=y
CONFIG_MEMFD_CREATE=y
CONFIG_CONFIGFS_FS=y
# end of Pseudo filesystems

CONFIG_MISC_FILESYSTEMS=y
# CONFIG_ORANGEFS_FS is not set
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
# CONFIG_ECRYPT_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_HFSPLUS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
# CONFIG_JFFS2_FS is not set
CONFIG_UBIFS_FS=y
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
# CONFIG_UBIFS_FS_LZO is not set
# CONFIG_UBIFS_FS_ZLIB is not set
# CONFIG_UBIFS_FS_ZSTD is not set
# CONFIG_UBIFS_ATIME_SUPPORT is not set
CONFIG_UBIFS_FS_XATTR=y
CONFIG_UBIFS_FS_SECURITY=y
# CONFIG_UBIFS_FS_AUTHENTICATION is not set
# CONFIG_CRAMFS is not set
CONFIG_SQUASHFS=y
# CONFIG_SQUASHFS_FILE_CACHE is not set
CONFIG_SQUASHFS_FILE_DIRECT=y
# CONFIG_SQUASHFS_DECOMP_SINGLE is not set
# CONFIG_SQUASHFS_DECOMP_MULTI is not set
CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
# CONFIG_SQUASHFS_XATTR is not set
CONFIG_SQUASHFS_ZLIB=y
# CONFIG_SQUASHFS_LZ4 is not set
# CONFIG_SQUASHFS_LZO is not set
# CONFIG_SQUASHFS_XZ is not set
# CONFIG_SQUASHFS_ZSTD is not set
# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set
# CONFIG_SQUASHFS_EMBEDDED is not set
CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
# CONFIG_VXFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_OMFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_QNX6FS_FS is not set
# CONFIG_ROMFS_FS is not set
# CONFIG_PSTORE is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
# CONFIG_EROFS_FS is not set
# CONFIG_NETWORK_FILESYSTEMS is not set
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="iso8859-1"
CONFIG_NLS_CODEPAGE_437=y
# CONFIG_NLS_CODEPAGE_737 is not set
# CONFIG_NLS_CODEPAGE_775 is not set
# CONFIG_NLS_CODEPAGE_850 is not set
# CONFIG_NLS_CODEPAGE_852 is not set
# CONFIG_NLS_CODEPAGE_855 is not set
# CONFIG_NLS_CODEPAGE_857 is not set
# CONFIG_NLS_CODEPAGE_860 is not set
# CONFIG_NLS_CODEPAGE_861 is not set
# CONFIG_NLS_CODEPAGE_862 is not set
# CONFIG_NLS_CODEPAGE_863 is not set
# CONFIG_NLS_CODEPAGE_864 is not set
# CONFIG_NLS_CODEPAGE_865 is not set
# CONFIG_NLS_CODEPAGE_866 is not set
# CONFIG_NLS_CODEPAGE_869 is not set
# CONFIG_NLS_CODEPAGE_936 is not set
# CONFIG_NLS_CODEPAGE_950 is not set
# CONFIG_NLS_CODEPAGE_932 is not set
# CONFIG_NLS_CODEPAGE_949 is not set
# CONFIG_NLS_CODEPAGE_874 is not set
# CONFIG_NLS_ISO8859_8 is not set
# CONFIG_NLS_CODEPAGE_1250 is not set
# CONFIG_NLS_CODEPAGE_1251 is not set
# CONFIG_NLS_ASCII is not set
CONFIG_NLS_ISO8859_1=y
# CONFIG_NLS_ISO8859_2 is not set
# CONFIG_NLS_ISO8859_3 is not set
# CONFIG_NLS_ISO8859_4 is not set
# CONFIG_NLS_ISO8859_5 is not set
# CONFIG_NLS_ISO8859_6 is not set
# CONFIG_NLS_ISO8859_7 is not set
# CONFIG_NLS_ISO8859_9 is not set
# CONFIG_NLS_ISO8859_13 is not set
# CONFIG_NLS_ISO8859_14 is not set
# CONFIG_NLS_ISO8859_15 is not set
# CONFIG_NLS_KOI8_R is not set
# CONFIG_NLS_KOI8_U is not set
# CONFIG_NLS_MAC_ROMAN is not set
# CONFIG_NLS_MAC_CELTIC is not set
# CONFIG_NLS_MAC_CENTEURO is not set
# CONFIG_NLS_MAC_CROATIAN is not set
# CONFIG_NLS_MAC_CYRILLIC is not set
# CONFIG_NLS_MAC_GAELIC is not set
# CONFIG_NLS_MAC_GREEK is not set
# CONFIG_NLS_MAC_ICELAND is not set
# CONFIG_NLS_MAC_INUIT is not set
# CONFIG_NLS_MAC_ROMANIAN is not set
# CONFIG_NLS_MAC_TURKISH is not set
# CONFIG_NLS_UTF8 is not set
# CONFIG_DLM is not set
# CONFIG_UNICODE is not set
# end of File systems

#
# Security options
#
CONFIG_KEYS=y
# CONFIG_KEYS_REQUEST_CACHE is not set
# CONFIG_PERSISTENT_KEYRINGS is not set
# CONFIG_BIG_KEYS is not set
# CONFIG_ENCRYPTED_KEYS is not set
# CONFIG_KEY_DH_OPERATIONS is not set
# CONFIG_SECURITY_DMESG_RESTRICT is not set
# CONFIG_SECURITY is not set
# CONFIG_SECURITYFS is not set
CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
# CONFIG_HARDENED_USERCOPY is not set
# CONFIG_FORTIFY_SOURCE is not set
# CONFIG_STATIC_USERMODEHELPER is not set
CONFIG_DEFAULT_SECURITY_DAC=y
CONFIG_LSM="lockdown,yama,loadpin,safesetid,integrity"

#
# Kernel hardening options
#

#
# Memory initialization
#
CONFIG_INIT_STACK_NONE=y
# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set
# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set
# end of Memory initialization
# end of Kernel hardening options
# end of Security options

CONFIG_CRYPTO=y

#
# Crypto core or helper
#
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_ALGAPI2=y
CONFIG_CRYPTO_AEAD=y
CONFIG_CRYPTO_AEAD2=y
CONFIG_CRYPTO_BLKCIPHER=y
CONFIG_CRYPTO_BLKCIPHER2=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_RNG_DEFAULT=y
CONFIG_CRYPTO_AKCIPHER2=y
CONFIG_CRYPTO_AKCIPHER=y
CONFIG_CRYPTO_KPP2=y
CONFIG_CRYPTO_KPP=y
CONFIG_CRYPTO_ACOMP2=y
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_MANAGER2=y
# CONFIG_CRYPTO_USER is not set
CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
CONFIG_CRYPTO_NULL=y
CONFIG_CRYPTO_NULL2=y
# CONFIG_CRYPTO_PCRYPT is not set
# CONFIG_CRYPTO_CRYPTD is not set
# CONFIG_CRYPTO_AUTHENC is not set
# CONFIG_CRYPTO_TEST is not set

#
# Public-key cryptography
#
CONFIG_CRYPTO_RSA=y
# CONFIG_CRYPTO_DH is not set
CONFIG_CRYPTO_ECC=y
CONFIG_CRYPTO_ECDH=y
# CONFIG_CRYPTO_ECRDSA is not set

#
# Authenticated Encryption with Associated Data
#
CONFIG_CRYPTO_CCM=y
# CONFIG_CRYPTO_GCM is not set
# CONFIG_CRYPTO_CHACHA20POLY1305 is not set
# CONFIG_CRYPTO_AEGIS128 is not set
CONFIG_CRYPTO_SEQIV=y
# CONFIG_CRYPTO_ECHAINIV is not set

#
# Block modes
#
# CONFIG_CRYPTO_CBC is not set
# CONFIG_CRYPTO_CFB is not set
CONFIG_CRYPTO_CTR=y
# CONFIG_CRYPTO_CTS is not set
CONFIG_CRYPTO_ECB=y
# CONFIG_CRYPTO_LRW is not set
# CONFIG_CRYPTO_OFB is not set
# CONFIG_CRYPTO_PCBC is not set
# CONFIG_CRYPTO_XTS is not set
# CONFIG_CRYPTO_KEYWRAP is not set
# CONFIG_CRYPTO_ADIANTUM is not set
# CONFIG_CRYPTO_ESSIV is not set

#
# Hash modes
#
CONFIG_CRYPTO_CMAC=y
CONFIG_CRYPTO_HMAC=y
# CONFIG_CRYPTO_XCBC is not set
# CONFIG_CRYPTO_VMAC is not set

#
# Digest
#
CONFIG_CRYPTO_CRC32C=y
# CONFIG_CRYPTO_CRC32 is not set
# CONFIG_CRYPTO_XXHASH is not set
# CONFIG_CRYPTO_CRCT10DIF is not set
# CONFIG_CRYPTO_GHASH is not set
# CONFIG_CRYPTO_POLY1305 is not set
# CONFIG_CRYPTO_MD4 is not set
# CONFIG_CRYPTO_MD5 is not set
# CONFIG_CRYPTO_MICHAEL_MIC is not set
# CONFIG_CRYPTO_RMD128 is not set
# CONFIG_CRYPTO_RMD160 is not set
# CONFIG_CRYPTO_RMD256 is not set
# CONFIG_CRYPTO_RMD320 is not set
# CONFIG_CRYPTO_SHA1 is not set
CONFIG_CRYPTO_LIB_SHA256=y
CONFIG_CRYPTO_SHA256=y
# CONFIG_CRYPTO_SHA512 is not set
# CONFIG_CRYPTO_SHA3 is not set
# CONFIG_CRYPTO_SM3 is not set
# CONFIG_CRYPTO_STREEBOG is not set
# CONFIG_CRYPTO_TGR192 is not set
# CONFIG_CRYPTO_WP512 is not set

#
# Ciphers
#
CONFIG_CRYPTO_LIB_AES=y
CONFIG_CRYPTO_AES=y
# CONFIG_CRYPTO_AES_TI is not set
# CONFIG_CRYPTO_ANUBIS is not set
CONFIG_CRYPTO_LIB_ARC4=y
CONFIG_CRYPTO_ARC4=y
# CONFIG_CRYPTO_BLOWFISH is not set
# CONFIG_CRYPTO_CAMELLIA is not set
# CONFIG_CRYPTO_CAST5 is not set
# CONFIG_CRYPTO_CAST6 is not set
# CONFIG_CRYPTO_DES is not set
# CONFIG_CRYPTO_FCRYPT is not set
# CONFIG_CRYPTO_KHAZAD is not set
# CONFIG_CRYPTO_SALSA20 is not set
# CONFIG_CRYPTO_CHACHA20 is not set
# CONFIG_CRYPTO_SEED is not set
# CONFIG_CRYPTO_SERPENT is not set
# CONFIG_CRYPTO_SM4 is not set
# CONFIG_CRYPTO_TEA is not set
# CONFIG_CRYPTO_TWOFISH is not set

#
# Compression
#
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_LZO=y
# CONFIG_CRYPTO_842 is not set
# CONFIG_CRYPTO_LZ4 is not set
# CONFIG_CRYPTO_LZ4HC is not set
# CONFIG_CRYPTO_ZSTD is not set

#
# Random Number Generation
#
# CONFIG_CRYPTO_ANSI_CPRNG is not set
CONFIG_CRYPTO_DRBG_MENU=y
CONFIG_CRYPTO_DRBG_HMAC=y
# CONFIG_CRYPTO_DRBG_HASH is not set
# CONFIG_CRYPTO_DRBG_CTR is not set
CONFIG_CRYPTO_DRBG=y
CONFIG_CRYPTO_JITTERENTROPY=y
# CONFIG_CRYPTO_USER_API_HASH is not set
# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
# CONFIG_CRYPTO_USER_API_RNG is not set
# CONFIG_CRYPTO_USER_API_AEAD is not set
CONFIG_CRYPTO_HASH_INFO=y
CONFIG_CRYPTO_HW=y
# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set
# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set
# CONFIG_CRYPTO_DEV_SAFEXCEL is not set
# CONFIG_CRYPTO_DEV_CCREE is not set

#
# Support for Allwinner Sunxi CryptoEngine
#

#
# Choose one according to the actual usage
#
# CONFIG_CRYPTO_DEV_SUNXI is not set
# CONFIG_CRYPTO_DEV_SUNXI_IOCTL is not set
# end of Support for Allwinner Sunxi CryptoEngine

# CONFIG_ASYMMETRIC_KEY_TYPE is not set

#
# Certificates for signature checking
#
# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set
# end of Certificates for signature checking

#
# Library routines
#
# CONFIG_PACKING is not set
CONFIG_BITREVERSE=y
CONFIG_HAVE_ARCH_BITREVERSE=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_NET_UTILS=y
# CONFIG_CORDIC is not set
CONFIG_RATIONAL=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
# CONFIG_CRC_CCITT is not set
CONFIG_CRC16=y
# CONFIG_CRC_T10DIF is not set
# CONFIG_CRC_ITU_T is not set
CONFIG_CRC32=y
# CONFIG_CRC32_SELFTEST is not set
# CONFIG_CRC32_SLICEBY8 is not set
# CONFIG_CRC32_SLICEBY4 is not set
CONFIG_CRC32_SARWATE=y
# CONFIG_CRC32_BIT is not set
# CONFIG_CRC64 is not set
# CONFIG_CRC4 is not set
# CONFIG_CRC7 is not set
# CONFIG_LIBCRC32C is not set
# CONFIG_CRC8 is not set
# CONFIG_RANDOM32_SELFTEST is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
# CONFIG_XZ_DEC is not set
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_ASSOCIATIVE_ARRAY=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HAS_DMA=y
CONFIG_NEED_SG_DMA_LENGTH=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_DMA_DECLARE_COHERENT=y
CONFIG_ARCH_HAS_SETUP_DMA_OPS=y
CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y
CONFIG_DMA_REMAP=y
CONFIG_DMA_CMA=y

#
# Default contiguous memory area size:
#
CONFIG_CMA_SIZE_MBYTES=16
CONFIG_CMA_SIZE_SEL_MBYTES=y
# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
# CONFIG_CMA_SIZE_SEL_MIN is not set
# CONFIG_CMA_SIZE_SEL_MAX is not set
CONFIG_CMA_ALIGNMENT=8
# CONFIG_DMA_API_DEBUG is not set
CONFIG_SGL_ALLOC=y
CONFIG_CPU_RMAP=y
CONFIG_DQL=y
CONFIG_NLATTR=y
CONFIG_CLZ_TAB=y
# CONFIG_IRQ_POLL is not set
CONFIG_MPILIB=y
CONFIG_LIBFDT=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_SG_POOL=y
CONFIG_SBITMAP=y
# CONFIG_STRING_SELFTEST is not set
# end of Library routines

#
# Kernel hacking
#

#
# printk and dmesg options
#
CONFIG_PRINTK_TIME=y
# CONFIG_PRINTK_CALLER is not set
CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7
CONFIG_CONSOLE_LOGLEVEL_QUIET=4
CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
# CONFIG_BOOT_PRINTK_DELAY is not set
# CONFIG_DYNAMIC_DEBUG is not set
# CONFIG_DYNAMIC_DEBUG_CORE is not set
# end of printk and dmesg options

#
# Compile-time checks and compiler options
#
# CONFIG_DEBUG_INFO is not set
CONFIG_ENABLE_MUST_CHECK=y
CONFIG_FRAME_WARN=2048
# CONFIG_STRIP_ASM_SYMS is not set
# CONFIG_READABLE_ASM is not set
CONFIG_DEBUG_FS=y
# CONFIG_HEADERS_INSTALL is not set
CONFIG_OPTIMIZE_INLINING=y
# CONFIG_DEBUG_SECTION_MISMATCH is not set
CONFIG_SECTION_MISMATCH_WARN_ONLY=y
# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
# end of Compile-time checks and compiler options

# CONFIG_MAGIC_SYSRQ is not set
CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_MISC=y

#
# Memory Debugging
#
# CONFIG_PAGE_EXTENSION is not set
# CONFIG_DEBUG_PAGEALLOC is not set
# CONFIG_PAGE_OWNER is not set
# CONFIG_PAGE_POISONING is not set
# CONFIG_DEBUG_RODATA_TEST is not set
# CONFIG_DEBUG_OBJECTS is not set
# CONFIG_SLUB_STATS is not set
CONFIG_HAVE_DEBUG_KMEMLEAK=y
# CONFIG_DEBUG_KMEMLEAK is not set
# CONFIG_DEBUG_STACK_USAGE is not set
# CONFIG_DEBUG_VM is not set
CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
# CONFIG_DEBUG_VIRTUAL is not set
# CONFIG_DEBUG_MEMORY_INIT is not set
# CONFIG_DEBUG_PER_CPU_MAPS is not set
CONFIG_CC_HAS_KASAN_GENERIC=y
CONFIG_KASAN_STACK=1
# end of Memory Debugging

CONFIG_ARCH_HAS_KCOV=y
CONFIG_CC_HAS_SANCOV_TRACE_PC=y
# CONFIG_KCOV is not set
# CONFIG_DEBUG_SHIRQ is not set

#
# Debug Lockups and Hangs
#
# CONFIG_SOFTLOCKUP_DETECTOR is not set
# CONFIG_DETECT_HUNG_TASK is not set
# CONFIG_WQ_WATCHDOG is not set
# end of Debug Lockups and Hangs

# CONFIG_PANIC_ON_OOPS is not set
CONFIG_PANIC_ON_OOPS_VALUE=0
CONFIG_PANIC_TIMEOUT=0
# CONFIG_SCHED_DEBUG is not set
# CONFIG_SCHEDSTATS is not set
# CONFIG_SCHED_STACK_END_CHECK is not set
# CONFIG_DEBUG_TIMEKEEPING is not set
# CONFIG_DEBUG_PREEMPT is not set

#
# Lock Debugging (spinlocks, mutexes, etc...)
#
CONFIG_LOCK_DEBUGGING_SUPPORT=y
# CONFIG_PROVE_LOCKING is not set
# CONFIG_LOCK_STAT is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_DEBUG_SPINLOCK is not set
CONFIG_DEBUG_MUTEXES=y
# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
# CONFIG_DEBUG_RWSEMS is not set
# CONFIG_DEBUG_LOCK_ALLOC is not set
# CONFIG_DEBUG_ATOMIC_SLEEP is not set
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
# CONFIG_LOCK_TORTURE_TEST is not set
# CONFIG_WW_MUTEX_SELFTEST is not set
# end of Lock Debugging (spinlocks, mutexes, etc...)

# CONFIG_STACKTRACE is not set
# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set
# CONFIG_DEBUG_KOBJECT is not set
# CONFIG_DEBUG_BUGVERBOSE is not set
# CONFIG_DEBUG_LIST is not set
# CONFIG_DEBUG_PLIST is not set
# CONFIG_DEBUG_SG is not set
# CONFIG_DEBUG_NOTIFIERS is not set
# CONFIG_DEBUG_CREDENTIALS is not set

#
# RCU Debugging
#
# CONFIG_RCU_PERF_TEST is not set
# CONFIG_RCU_TORTURE_TEST is not set
CONFIG_RCU_CPU_STALL_TIMEOUT=20
# CONFIG_RCU_TRACE is not set
# CONFIG_RCU_EQS_DEBUG is not set
# end of RCU Debugging

# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
# CONFIG_NOTIFIER_ERROR_INJECTION is not set
# CONFIG_FAULT_INJECTION is not set
# CONFIG_LATENCYTOP is not set
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
CONFIG_HAVE_C_RECORDMCOUNT=y
CONFIG_TRACING_SUPPORT=y
# CONFIG_FTRACE is not set
# CONFIG_RUNTIME_TESTING_MENU is not set
# CONFIG_MEMTEST is not set
# CONFIG_BUG_ON_DATA_CORRUPTION is not set
# CONFIG_SAMPLES is not set
CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_KGDB is not set
# CONFIG_UBSAN is not set
CONFIG_UBSAN_ALIGNMENT=y
CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y
# CONFIG_ARM_PTDUMP_DEBUGFS is not set
# CONFIG_DEBUG_WX is not set
# CONFIG_UNWINDER_FRAME_POINTER is not set
CONFIG_UNWINDER_ARM=y
CONFIG_ARM_UNWIND=y
# CONFIG_DEBUG_USER is not set
CONFIG_DEBUG_LL=y
# CONFIG_DEBUG_SUNXI_UART0 is not set
# CONFIG_DEBUG_SUNXI_UART1 is not set
# CONFIG_DEBUG_SUNXI_UART2 is not set
# CONFIG_DEBUG_ICEDCC is not set
# CONFIG_DEBUG_SEMIHOSTING is not set
CONFIG_DEBUG_LL_UART_8250=y
# CONFIG_DEBUG_LL_UART_PL01X is not set
CONFIG_DEBUG_LL_INCLUDE="debug/8250.S"
CONFIG_DEBUG_UART_PHYS=0x02500C00
CONFIG_DEBUG_UART_VIRT=0xf2500C00
CONFIG_DEBUG_UART_8250_SHIFT=2
# CONFIG_DEBUG_UART_8250_WORD is not set
# CONFIG_DEBUG_UART_8250_PALMCHIP is not set
# CONFIG_DEBUG_UART_8250_FLOW_CONTROL is not set
# CONFIG_DEBUG_UNCOMPRESS is not set
CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
CONFIG_EARLY_PRINTK=y
# CONFIG_PID_IN_CONTEXTIDR is not set
# CONFIG_SUNXI_DUMP is not set
# CONFIG_CORESIGHT is not set
# end of Kernel hacking

加载顺序：

insmod videobuf2-memops.ko
insmod videobuf2-dma-contig.ko
insmod videobuf2-vmalloc.ko
insmod vin_io.ko
insmod ov5640.ko
insmod vin_v4l2.ko

错误日志（能识别到ov5640）：

shz18877605430

@whycanservice 我用的是sensor0，只有一个ov5640摄像头，现在是[VIN_ERR]media_entity_find_link null 有问题，大佬这么怎么搞呢？

shz18877605430

@whycanservice 当前出现了这个问题。

shz18877605430

@whycanservice 已解决

shz18877605430

T113 ov5640加载vin_v4l2.ko报错，sun8iw20-pinctrl 2000000.pinctrl: pin PE8 already requested by 5801000.csi; cannot claim for 2000000.pinctrl:136

有大佬指点指点吗？

shz18877605430

T113 ov5640加载驱动报错，PE11申请不到，被占用了。

board.dts

/*
 * Allwinner Technology CO., Ltd. sun8iw20p1 platform
 *
 * modify base on juno.dts
 */
 /* optee used 7MB: SHM 2M: OS: 1M: TA:4M*/
/memreserve/ 0x41B00000 0x00100000;

#include <dt-bindings/clock/sun8iw20-ccu.h>
#include <dt-bindings/clock/sun8iw20-r-ccu.h>
#include <dt-bindings/clock/sun8iw20-rtc.h>
#include <dt-bindings/reset/sun8iw20-ccu.h>
#include <dt-bindings/reset/sun8iw20-r-ccu.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/gpio/sun4i-gpio.h>
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/power/r528-power.h>

/ {
	model = "sun8iw20";
	compatible = "allwinner,sun8iw20p1";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		serial3 = &uart3;
		serial4 = &uart4;
		serial5 = &uart5;
		spi0 = &spi0;
		spi1 = &spi1;
		twi0 = &twi0;
		twi1 = &twi1;
		twi2 = &twi2;
		twi3 = &twi3;
		mmc0 = &sdc0;
		mmc2 = &sdc2;
		pwm = &pwm;
		pwm0 = &pwm0;
		pwm1 = &pwm1;
		pwm2 = &pwm2;
		pwm3 = &pwm3;
		pwm4 = &pwm4;
		pwm5 = &pwm5;
		pwm6 = &pwm6;
		pwm7 = &pwm7;
		ir0 = &s_cir0;
		ve0 = &ve;
		tv0 = &tv0;
		tvd = &tvd;
		tvd0 = &tvd0;
		share_space0 = &share_space0;
	};

	chosen {
		bootargs = "earlyprintk=sunxi-uart,0x2500000 loglevel=8 initcall_debug=0 console=ttyS0 init=/init";
		//bootargs = "loglevel=8 initcall_debug=0 console=ttyS0 init=/init";
		linux,initrd-start = <0x0 0x0>;
		linux,initrd-end = <0x0 0x0>;
	};

	firmware {
		optee {
			compatible = "linaro,optee-tz";
			method = "smc";
		};
	};

	cpus {
		enable-method = "allwinner,sun8iw20p1";
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7","arm,armv7";
			reg = <0x0>;
			enable-method = "psci";
			clocks = <&ccu CLK_CPUX>;
			dynamic-power-coefficient = <156>;
			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
			operating-points-v2 = <&cpu_opp_table>;
			#cooling-cells = <2>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a7","arm,armv7";
			reg = <0x1>;
			enable-method = "psci";
			clocks = <&ccu CLK_CPUX>;
			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
			operating-points-v2 = <&cpu_opp_table>;
			#cooling-cells = <2>;
		};

		idle-states {
			entry-method = "arm,psci";

			CPU_SLEEP: cpu-sleep {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x0010000>;
				entry-latency-us = <46>;
				exit-latency-us = <59>;
				min-residency-us = <3570>;
				local-timer-stop;
			};

			CLUSTER_SLEEP: cluster-sleep {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x1010000>;
				entry-latency-us = <47>;
				exit-latency-us = <74>;
				min-residency-us = <5000>;
				local-timer-stop;
			};
		};

	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	dump_reg: dump_reg@20000 {
		compatible = "allwinner,sunxi-dump-reg";
		reg = <0x0 0x00020000 0x0 0x0004>;
		/* 0x00020000: dump_reg test addr, 0x0004: dump_reg test size */
	};

	cpu_opp_table: cpu-opp-table {
		compatible = "allwinner,sun50i-operating-points";
		nvmem-cells = <&speedbin_efuse>, <&cpubin_efuse>;
		nvmem-cell-names = "speed", "bin";
		opp-shared;

		opp@480000000 {
			opp-hz = /bits/ 64 <480000000>;
			clock-latency-ns = <244144>; /* 8 32k periods */
			opp-microvolt-a0 = <900000>;
			opp-microvolt-a1 = <900000>;
			opp-microvolt-a2 = <900000>;

			opp-microvolt-b0 = <950000>;
			opp-supported-hw = <0x3>;
		};

		opp@720000000 {
			opp-hz = /bits/ 64 <720000000>;
			clock-latency-ns = <244144>; /* 8 32k periods */
			opp-microvolt-a0 = <900000>;
			opp-microvolt-a1 = <900000>;
			opp-microvolt-a2 = <900000>;

			opp-microvolt-b0 = <950000>;
			opp-supported-hw = <0x3>;
		};

		opp@912000000 {
			opp-hz = /bits/ 64 <912000000>;
			clock-latency-ns = <244144>; /* 8 32k periods */
			opp-microvolt-a0 = <950000>;
			opp-microvolt-a1 = <900000>;
			opp-microvolt-a2 = <900000>;

			opp-microvolt-b0 = <950000>;
			opp-supported-hw = <0x3>;
		};

		opp@1008000000 {
			opp-hz = /bits/ 64 <1008000000>;
			clock-latency-ns = <244144>; /* 8 32k periods */
			opp-microvolt-a0 = <1000000>;
			opp-microvolt-a1 = <900000>;
			opp-microvolt-a2 = <900000>;

			opp-microvolt-b0 = <950000>;
			opp-supported-hw = <0x3>;
		};

		opp@1104000000 {
			opp-hz = /bits/ 64 <1104000000>;
			clock-latency-ns = <244144>; /* 8 32k periods */
			opp-microvolt-a0 = <1050000>;
			opp-microvolt-a1 = <950000>;
			opp-microvolt-a2 = <950000>;

			opp-microvolt-b0 = <950000>;
			opp-supported-hw = <0x3>;
		};

		opp@1200000000 {
			opp-hz = /bits/ 64 <1200000000>;
			clock-latency-ns = <244144>; /* 8 32k periods */
			opp-microvolt-a0 = <1100000>;
			opp-microvolt-a1 = <1000000>;
			opp-microvolt-a2 = <1000000>;

			opp-supported-hw = <0x1>;
		};
	};


	dcxo24M: dcxo24M_clk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <24000000>;
		clock-output-names = "dcxo24M";
	};

	rc_16m: rc16m_clk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <16000000>;
		clock-accuracy = <300000000>;
		clock-output-names = "rc-16m";
	};

	ext_32k: ext32k_clk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <32768>;
		clock-output-names = "ext-32k";
	};

	dram: dram {
		compatible = "allwinner,dram";
		clocks = <&ccu CLK_PLL_DDR0>;
		clock-names = "pll_ddr";
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0x00000000 0x40000000 0x00000000 0x20000000>;
	};

	share_space0: share_space@42100000 {
		#address-cells = <1>;
		#size-cells = <1>;
		deice_tpye = "share_space0";
		/* dsp write addr and len */
		/* arm write addr and len */
		/* dsp log addr and len */
		/* reserve */
		reg = <	0x42100000 0x00001000
			0x42101000 0x00001000
			0x42102000 0x0000E000
			0x00000000 0x00000000>;
	};

	gic: interrupt-controller@3020000 {
		compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
		#interrupt-cells = <3>;
		#address-cells = <0>;
		device_type = "gic";
		interrupt-controller;
		reg = <0x0 0x03021000 0 0x1000>, /* GIC Dist */
		      <0x0 0x03022000 0 0x2000>, /* GIC CPU */
		      <0x0 0x03024000 0 0x2000>, /* GIC VCPU Control */
		      <0x0 0x03026000 0 0x2000>; /* GIC VCPU */
		interrupts = <GIC_PPI 9 0xf04>; /* GIC Maintenence IRQ */
	};

	timer_arch {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
		clock-frequency = <24000000>;
		arm,cpu-registers-not-fw-configured;
		interrupt-parent = <&gic>;
		arm,no-tick-in-suspend;
	};

	pmu {
		compatible = "arm,cortex-a7-pmu";
		interrupts = <GIC_SPI 172 4>,
			     <GIC_SPI 173 4>;
	};

	power: power-management@ff000000 {
		compatible = "allwinner,r528-pmu", "syscon", "simple-mfd";
		reg = <0x0 0x07001000 0x0 0x400>;

		pd: power-controller {
			compatible = "allwinner,r528-power-controller";
			clocks = <&r_ccu CLK_R_PPU>;
			clock-names = "ppu";
			resets = <&r_ccu RST_R_PPU>;
			reset-names = "ppu_rst";
			#power-domain-cells = <1>;
			#address-cells = <1>;
			#size-cells = <0>;

			/* These power domains are grouped by VD_SYS */
			pd_ve@R528_PD_VE {
				reg = <R528_PD_VE>;
			};
		};
	};

	mmu_aw: iommu@2010000 {
		compatible = "allwinner,sunxi-iommu";
		reg = <0x0 0x02010000 0x0 0x1000>;
		interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "iommu-irq";
		clocks = <&ccu CLK_BUS_IOMMU>;
		clock-names = "iommu";
		#iommu-cells = <2>;
		status = "okay";
	};

	reg_pio1_8: pio-18 {
		compatible = "regulator-fixed";
		regulator-name = "pio-18";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
	};

	reg_pio3_3: pio-33 {
		compatible = "regulator-fixed";
		regulator-name = "pio-33";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	thermal-zones {
		cpu_thermal_zone: cpu_thermal_zone {
			polling-delay-passive = <500>;
			polling-delay = <1000>;
			thermal-sensors = <&ths 0>;
			sustainable-power = <589>;

			cpu_trips: trips {
				cpu_threshold: trip-point@0 {
					temperature = <70000>;
					type = "passive";
					hysteresis = <0>;
				};
				cpu_target: trip-point@1 {
					temperature = <90000>;
					type = "passive";
					hysteresis = <0>;
				};
				cpu_crit: cpu_crit@0 {
					temperature = <110000>;
					type = "critical";
					hysteresis = <0>;
				};
			};

			cooling-maps {
				map0 {
					trip = <&cpu_target>;
					cooling-device = <&cpu0
					THERMAL_NO_LIMIT
					THERMAL_NO_LIMIT>;
					contribution = <1024>;
				};
			};
		};
	};

	soc: soc@3000000 {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		device_type = "soc";

		sram_ctrl: sram_ctrl@3000000 {
			compatible = "allwinner,sram_ctrl";
			reg = <0x0 0x3000000 0 0x16C>;
			soc_ver {
				offset = <0x24>;
				mask = <0x7>;
				shift = <0>;
				ver_a = <0x18590000>;
				ver_b = <0x18590002>;
				ver_d = <0x18590003>;
			};

			soc_id {
				offset = <0x200>;
				mask = <0x1>;
				shift = <22>;
			};

			soc_bin {
				offset = <0x0>;
				mask = <0x3ff>;
				shift = <0x0>;
			};

		};

		rtc_ccu: rtc_ccu@7090000 {
			compatible = "allwinner,sun8iw20-rtc-ccu";
			device_type = "rtc-ccu";
			reg = <0x0 0x07090000 0x0 0x320>;  /* The same as rtc */
			#clock-cells = <1>;
		};

		ccu: ccu@2001000 {
			compatible = "allwinner,sun8iw20-ccu";
			reg = <0x0 0x02001000 0x0 0x1000>;
			clocks = <&dcxo24M>, <&rtc_ccu CLK_OSC32K>, <&rtc_ccu CLK_IOSC>;
			clock-names = "hosc", "losc", "iosc";
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		r_ccu: r_ccu@7010000 {
			compatible = "allwinner,sun8iw20-r-ccu";
			reg = <0x0 0x07010000 0x0 0x240>;
			clocks = <&dcxo24M>, <&rtc_ccu CLK_OSC32K>, <&rtc_ccu CLK_IOSC>,
				 <&ccu CLK_PLL_PERIPH0>;
			clock-names = "hosc", "losc", "iosc", "pll-periph0";
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		rtc: rtc@7090000 {
			compatible = "allwinner,sun8iw20-rtc";
			device_type = "rtc";
			wakeup-source;
			reg = <0x0 0x07090000 0x0 0x320>;
			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&r_ccu CLK_R_AHB_BUS_RTC>, <&rtc_ccu CLK_RTC_1K>, <&rtc_ccu CLK_RTC_SPI>;
			clock-names = "r-ahb-rtc", "rtc-1k", "rtc-spi";
			resets = <&r_ccu RST_R_AHB_BUS_RTC>;
			gpr_cur_pos = <6>;
		};

		dma:dma-controller@3002000 {
			compatible = "allwinner,sun8iw20-dma";
			reg = <0x0 0x03002000 0x0 0x1000>;
			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
			clock-names = "bus", "mbus";
			dma-channels = <8>;
			dma-requests = <48>;
			resets = <&ccu RST_BUS_DMA>;
			#dma-cells = <1>;
		};

		soc_timer0: timer@2050000 {
			compatible = "allwinner,sun4i-a10-timer";
			device_type = "soc_timer";
			reg = <0x0 0x02050000 0x0 0xA0>;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&dcxo24M>;
		};

		wdt: watchdog@20500A0 {
			compatible = "allwinner,sun6i-a31-wdt";
			reg = <0x0 0x020500A0 0x0 0x20>;  /* In Timers Spec */
			interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;  /* In GIC Spec */
		};

		mbus0: mbus-controller@3102000 {
			compatible = "allwinner,sun8i-mbus";
			reg = <0x0 0x03102000 0x0 0x1000>;  /* In SDRAM Controller Spec: DRAMC Common Register */
			#mbus-cells = <1>;
		};

		pio: pinctrl@2000000 {
			compatible = "allwinner,sun8iw20-pinctrl";
			reg = <0x0 0x02000000 0x0 0x500>;
			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,  /* AW1859_GIC_Spec: GPIOB: 101-32=69 */
				     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
			device_type = "pio";
			clocks = <&ccu CLK_APB0>, <&dcxo24M>, <&rtc_ccu CLK_OSC32K>;
			clock-names = "apb", "hosc", "losc";
			gpio-controller;
			#gpio-cells = <3>;
			interrupt-controller;
			#interrupt-cells = <3>;
			#size-cells = <0>;
			vcc-pf-supply = <&reg_pio1_8>;
			vcc-pfo-supply = <&reg_pio3_3>;

			test_pins_a: test_pins@0 {
				allwinner,pins = "PB0", "PB1";
				allwinner,function = "test";
				allwinner,muxsel = <0x9>;
				allwinner,drive = <1>;
				allwinner,pull = <1>;
			};
			test_pins_b: test_pins@1 {
				pins = "PB0", "PB1";
				function = "io_disabled";
				allwinner,muxsel = <0xF>;
				allwinner,drive = <1>;
				allwinner,pull = <1>;
			};

			csi_mclk0_pins_a: csi_mclk0@0 {
				pins = "PE3";
				function = "csi0";
				drive-strength = <10>;
			};
			csi_mclk0_pins_b: csi_mclk0@1 {
				pins = "PE3";
				function = "gpio_in";
			};
			csi0_pins_a: csi0@0 {
				pins = "PE2", "PE0", "PE1", "PE4", "PE5",
						 "PE6", "PE7", "PE8", "PE9", "PE10", "PE11";
				function = "ncsi0";
				drive-strength = <10>;
			};
			csi0_pins_b: csi0@1 {
				pins = "PE2", "PE0", "PE1", "PE4", "PE5",
						 "PE6", "PE7", "PE8", "PE9", "PE10", "PE11";
				function = "io_disabled";
				drive-strength = <10>;
			};

			lvds0_pins_a: lvds0@0 {
				pins  = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9";
				function = "lvds0";
				drive-strength = <30>;
				bias-disable;
			};

			lvds0_pins_b: lvds0@1 {
				pins  = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9";
				function = "io_disabled";
				drive-strength = <30>;
				bias-disable;
			};

			rgb24_pins_a: rgb24@0 {
				pins = "PB2", "PB3", "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", \
					"PB4", "PB5", "PD6", "PD7", "PD8", "PD9", "PD10", "PD11", \
					"PB6", "PB7", "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", \
					"PD18", "PD19", "PD20", "PD21";
				function = "lcd0";
				drive-strength = <30>;
				bias-disable;
			};

			rgb24_pins_b: rgb24@1 {
				pins = "PB2", "PB3", "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", \
					"PB4", "PB5", "PD6", "PD7", "PD8", "PD9", "PD10", "PD11", \
					"PB6", "PB7", "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", \
					"PD18", "PD19", "PD20", "PD21";
				function = "io_disabled";
				bias-disable;
			};

			rgb18_pins_a: rgb18@0 {
				pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", \
					"PD6", "PD7", "PD8", "PD9", "PD10", "PD11", \
					"PD12", "PD13", "PD14", "PD15", "PD16", "PD17", \
					"PD18", "PD19", "PD20", "PD21";
				function = "lcd0";
				drive-strength = <30>;
				bias-disable;
			};

			rgb18_pins_b: rgb18@1 {
				pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", \
					"PD6", "PD7", "PD8", "PD9", "PD10", "PD11", \
					"PD12", "PD13", "PD14", "PD15", "PD16", "PD17", \
					"PD18", "PD19", "PD20", "PD21";
				function = "io_disabled";
				bias-disable;
			};

			dsi2lane_pins_a: dsi2lane@0 {
				pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5";
				function = "dsi";
				drive-strength = <30>;
				bias-disable;
			};

			dsi2lane_pins_b: dsi2lane@1 {
				pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5";
				function = "io_disabled";
				bias-disable;
			};

			dsi4lane_pins_a: dsi4lane@0 {
				pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9";
				function = "dsi";
				drive-strength = <30>;
				bias-disable;
			};

			dsi4lane_pins_b: dsi4lane@1 {
				pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9";
				function = "io_disabled";
				bias-disable;
			};

		};

		pinctrl_test: pinctrl_test@0 {
			reg = <0x0 0x0 0x0 0x0>;
			compatible = "allwinner,sunxi-pinctrl-test";
			device_type = "pinctrl-test";
			/* For pin state selecting test */
			pinctrl-0 = <&test_pins_a>;
			pinctrl-1 = <&test_pins_b>;
			pinctrl-names = "default", "sleep";
			/* For pin basic_function/irq test */
			test-gpios = <&pio PB 0 GPIO_ACTIVE_LOW>;
			interrupt-parent = <&pio>;
			interrupts = <PB 1 IRQ_TYPE_LEVEL_HIGH>;
		};

		uart0: uart@2500000 {
			compatible = "allwinner,sun8i-uart";
			device_type = "uart0";
			reg = <0x0 0x02500000 0x0 0x400>;
			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
			sunxi,uart-fifosize = <64>;
			clocks = <&ccu CLK_BUS_UART0>;
			clock-names = "uart0";
			resets = <&ccu RST_BUS_UART0>;
			uart0_port = <0>;
			uart0_type = <2>;
			status = "disabled";
		};

		uart1: uart@2500400 {
			compatible = "allwinner,sun8i-uart";
			device_type = "uart1";
			reg = <0x0 0x02500400 0x0 0x400>;
			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
			sunxi,uart-fifosize = <256>;
			clocks = <&ccu CLK_BUS_UART1>;
			clock-names = "uart1";
			resets = <&ccu RST_BUS_UART1>;
			uart1_port = <1>;
			uart1_type = <4>;
			status = "okay";
		};

		uart2: uart@2500800 {
			compatible = "allwinner,sun8i-uart";
			device_type = "uart2";
			reg = <0x0 0x02500800 0x0 0x400>;
			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
			sunxi,uart-fifosize = <256>;
			clocks = <&ccu CLK_BUS_UART2>;
			clock-names = "uart2";
			resets = <&ccu RST_BUS_UART2>;
			uart2_port = <2>;
			uart2_type = <4>;
			status = "disabled";
		};

		uart3: uart@2500c00 {
			compatible = "allwinner,sun8i-uart";
			device_type = "uart3";
			reg = <0x0 0x02500c00 0x0 0x400>;
			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
			sunxi,uart-fifosize = <256>;
			clocks = <&ccu CLK_BUS_UART3>;
			clock-names = "uart3";
			resets = <&ccu RST_BUS_UART3>;
			uart3_port = <3>;
			uart3_type = <4>;
			status = "disabled";
		};

		uart4: uart@2501000 {
			compatible = "allwinner,sun8i-uart";
			device_type = "uart4";
			reg = <0x0 0x02501000 0x0 0x400>;
			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
			sunxi,uart-fifosize = <256>;
			clocks = <&ccu CLK_BUS_UART4>;
			clock-names = "uart4";
			resets = <&ccu RST_BUS_UART4>;
			uart4_port = <4>;
			uart4_type = <2>;
			status = "disabled";
		};

		uart5: uart@2501400 {
			compatible = "allwinner,sun8i-uart";
			device_type = "uart5";
			reg = <0x0 0x02501400 0x0 0x400>;
			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
			sunxi,uart-fifosize = <256>;
			clocks = <&ccu CLK_BUS_UART5>;
			clock-names = "uart5";
			resets = <&ccu RST_BUS_UART5>;
			uart5_port = <5>;
			uart5_type = <2>;
			status = "disabled";
		};
		cryptoengine: ce@03040000 {
			compatible = "allwinner,sunxi-ce";
			device_name = "ce";
			reg = <0x0 0x03040000 0x0 0xa0>, /* non-secure space */
			      <0x0 0x03040800 0x0 0xa0>; /* secure space */
			interrupts = <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>, /*non-secure*/
				   <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>; /* secure*/
			clock-frequency = <400000000>; /* 400MHz */
			clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>, <&ccu CLK_MBUS_CE>,
					<&ccu CLK_PLL_PERIPH0_2X>;
			clock-names = "bus_ce", "ce_clk", "mbus_ce", "pll_periph0_2x";
			resets = <&ccu RST_BUS_CE>;
			status = "okay";
		};

		gmac0: eth@4500000 {
			compatible = "allwinner,sunxi-gmac";
			reg = <0x0 0x04500000 0x0 0x10000>,
			      <0x0 0x03000030 0x0 0x4>;
			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "gmacirq";
			clocks = <&ccu CLK_BUS_EMAC0>, <&ccu CLK_EMAC0_25M>;
			clock-names = "gmac", "ephy";
			resets = <&ccu RST_BUS_EMAC0>;
			device_type = "gmac0";
			gmac-power0;
			gmac-power1;
			gmac-power2;
			status = "disabled";
		};

		sdc2: sdmmc@4022000 {
			compatible = "allwinner,sunxi-mmc-v4p6x";
			device_type = "sdc2";
			reg = <0x0 0x04022000 0x0 0x1000>;
			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&dcxo24M>,
				 <&ccu CLK_PLL_PERIPH0_2X>,
				 <&ccu CLK_MMC2>,
				 <&ccu CLK_BUS_MMC2>;
			clock-names = "osc24m","pll_periph","mmc","ahb";
			resets = <&ccu RST_BUS_MMC2>;
			reset-names = "rst";
			pinctrl-names = "default","sleep";
			pinctrl-0 = <&sdc2_pins_a>;
			pinctrl-1 = <&sdc2_pins_b>;
			bus-width = <4>;
			req-page-count = <2>;
			cap-mmc-highspeed;
			cap-cmd23;
			mmc-cache-ctrl;
			non-removable;
			/*max-frequency = <200000000>;*/
			max-frequency = <50000000>;
			cap-erase;
			mmc-high-capacity-erase-size;
			no-sdio;
			no-sd;
			/*-- speed mode --*/
			/*sm0: DS26_SDR12*/
			/*sm1: HSSDR52_SDR25*/
			/*sm2: HSDDR52_DDR50*/
			/*sm3: HS200_SDR104*/
			/*sm4: HS400*/
			/*-- frequency point --*/
			/*f0: CLK_400K*/
			/*f1: CLK_25M*/
			/*f2: CLK_50M*/
			/*f3: CLK_100M*/
			/*f4: CLK_150M*/
			/*f5: CLK_200M*/

			sdc_tm4_sm0_freq0 = <0>;
			sdc_tm4_sm0_freq1 = <0>;
			sdc_tm4_sm1_freq0 = <0x00000000>;
			sdc_tm4_sm1_freq1 = <0>;
			sdc_tm4_sm2_freq0 = <0x00000000>;
			sdc_tm4_sm2_freq1 = <0>;
			sdc_tm4_sm3_freq0 = <0x05000000>;
			sdc_tm4_sm3_freq1 = <0x00000005>;
			sdc_tm4_sm4_freq0 = <0x00050000>;
			sdc_tm4_sm4_freq1 = <0x00000004>;
			sdc_tm4_sm4_freq0_cmd = <0>;
			sdc_tm4_sm4_freq1_cmd = <0>;

			/*vmmc-supply = <&reg_3p3v>;*/
			/*vqmc-supply = <&reg_3p3v>;*/
			/*vdmc-supply = <&reg_3p3v>;*/
			/*vmmc = "vcc-card";*/
			/*vqmc = "";*/
			/*vdmc = "";*/
			/*sunxi-power-save-mode;*/
		};

		sdc0: sdmmc@4020000 {
			compatible = "allwinner,sunxi-mmc-v5p3x";
			device_type = "sdc0";
			reg = <0x0 0x04020000 0x0 0x1000>;
			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&dcxo24M>,
				 <&ccu CLK_PLL_PERIPH0_2X>,
				 <&ccu CLK_MMC0>,
				 <&ccu CLK_BUS_MMC0>;
			clock-names = "osc24m","pll_periph","mmc","ahb";
			resets = <&ccu RST_BUS_MMC0>;
			reset-names = "rst";
			pinctrl-names = "default","mmc_1v8","sleep","uart_jtag";
			pinctrl-0 = <&sdc0_pins_a>;
			pinctrl-1 = <&sdc0_pins_b>;
			pinctrl-2 = <&sdc0_pins_c>;
			pinctrl-3 = <&sdc0_pins_d &sdc0_pins_e>;
			max-frequency = <50000000>;
			bus-width = <4>;
			req-page-count = <2>;
			/*non-removable;*/
			/*broken-cd;*/
			/*cd-inverted*/
			/*cd-gpios = <&pio PF 6 GPIO_ACTIVE_LOW>;*/
			/* vmmc-supply = <&reg_3p3v>;*/
			/* vqmc-supply = <&reg_3p3v>;*/
			/* vdmc-supply = <&reg_3p3v>;*/
			/*vmmc = "vcc-card";*/
			/*vqmc = "";*/
			/*vdmc = "";*/
			cap-sd-highspeed;
			cap-wait-while-busy;
			no-sdio;
			no-mmc;
			/*sd-uhs-sdr50;*/
			/*sd-uhs-ddr50;*/
			/*cap-sdio-irq;*/
			/*keep-power-in-suspend;*/
			/*ignore-pm-notify;*/
			/*sunxi-power-save-mode;*/
			/*sunxi-dly-400k = <1 0 0 0>; */
			/*sunxi-dly-26M  = <1 0 0 0>;*/
			/*sunxi-dly-52M  = <1 0 0 0>;*/
			/*sunxi-dly-52M-ddr4  = <1 0 0 0>;*/
			/*sunxi-dly-52M-ddr8  = <1 0 0 0>;*/
			/*sunxi-dly-104M  = <1 0 0 0>;*/
			/*sunxi-dly-208M  = <1 0 0 0>;*/
			/*sunxi-dly-104M-ddr  = <1 0 0 0>;*/
			/*sunxi-dly-208M-ddr  = <1 0 0 0>;*/
		};

		sdc1: sdmmc@4021000 {
			compatible = "allwinner,sunxi-mmc-v5p3x";
			device_type = "sdc1";
			reg = <0x0 0x04021000 0x0 0x1000>;
			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&dcxo24M>,
				 <&ccu CLK_PLL_PERIPH0_2X>,
				 <&ccu CLK_MMC1>,
				 <&ccu CLK_BUS_MMC1>;
			clock-names = "osc24m","pll_periph","mmc","ahb";
			resets = <&ccu RST_BUS_MMC1>;
			reset-names = "rst";
			pinctrl-names = "default","sleep";
			pinctrl-0 = <&sdc1_pins_a>;
			pinctrl-1 = <&sdc1_pins_b>;
			max-frequency = <50000000>;
			bus-width = <4>;
			/*broken-cd;*/
			/*cd-inverted*/
			/*cd-gpios = <&pio PG 6 6 1 2 0>;*/
			/* vmmc-supply = <&reg_3p3v>;*/
			/* vqmc-supply = <&reg_3p3v>;*/
			/* vdmc-supply = <&reg_3p3v>;*/
			/*vmmc = "vcc-card";*/
			/*vqmc = "";*/
			/*vdmc = "";*/
			cap-sd-highspeed;
			no-mmc;
			/*sd-uhs-sdr50;*/
			/*sd-uhs-ddr50;*/
			/*sd-uhs-sdr104;*/
			/*cap-sdio-irq;*/
			keep-power-in-suspend;
			/*ignore-pm-notify;*/
			/*sunxi-power-save-mode;*/
			/*sunxi-dly-400k = <1 0 0 0 0>; */
			/*sunxi-dly-26M  = <1 0 0 0 0>;*/
			/*sunxi-dly-52M  = <1 0 0 0 0>;*/
			sunxi-dly-52M-ddr4  = <1 0 0 0 2>;
			/*sunxi-dly-52M-ddr8  = <1 0 0 0 0>;*/
			sunxi-dly-104M  = <1 0 0 0 1>;
			/*sunxi-dly-208M  = <1 1 0 0 0>;*/
			sunxi-dly-208M  = <1 0 0 0 1>;
			/*sunxi-dly-104M-ddr  = <1 0 0 0 0>;*/
			/*sunxi-dly-208M-ddr  = <1 0 0 0 0>;*/

			status = "okay";
		};

		tpadc: tpadc@2009c00 {
			compatible = "allwinner,tp_key";
			reg = <0x0 0x02009c00 0x0 0x400>;
			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_TPADC>, <&ccu CLK_BUS_TPADC>;
			clock-names = "mod", "bus";
			clock-frequency = <1000000>;
			resets = <&ccu RST_BUS_TPADC>;
			status = "disabled";
		};

		rtp:rtp@2009c00 {
			compatible = "allwinner,sun8i-ts";
			reg = <0x0 0x02009c00 0x0 0x400>;
			clocks = <&ccu CLK_TPADC>, <&ccu CLK_BUS_TPADC>;
			clock-names = "mod", "bus";
			clock-frequency = <1000000>;
			resets = <&ccu RST_BUS_TPADC>;
			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
		};

		spi0: spi@4025000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sun8i-spi";
			device_type = "spi0";
			reg = <0x0 0x04025000 0x0 0x1000>;
			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_PLL_PERIPH0>, <&ccu CLK_SPI0>, <&ccu CLK_BUS_SPI0>;
			clock-names = "pll", "mod", "bus";
			resets = <&ccu RST_BUS_SPI0>;
			clock-frequency = <100000000>;
			spi0_cs_number = <1>;
			spi0_cs_bitmap = <1>;
			dmas = <&dma 22>, <&dma 22>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		spi1: spi@4026000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sun8i-spi";
			device_type = "spi1";
			reg = <0x0 0x04026000 0x0 0x1000>;
			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_PLL_PERIPH0>, <&ccu CLK_SPI1>, <&ccu CLK_BUS_SPI1>;
			clock-names = "pll", "mod", "bus";
			resets = <&ccu RST_BUS_SPI1>;
			clock-frequency = <100000000>;
			spi1_cs_number = <1>;
			spi1_cs_bitmap = <1>;
			dmas = <&dma 23>, <&dma 23>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		ve: ve@1c0e000 {
			    compatible = "allwinner,sunxi-cedar-ve";
			    reg = <0x0 0x01c0e000 0x0 0x1000>,
				<0x0 0x03000000 0x0 0x10>,
				<0x0 0x03001000 0x0 0x1000>;
			    interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
			    clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, <&ccu CLK_MBUS_VE>;
			    clock-names = "bus_ve", "ve", "mbus_ve";
			    resets = <&ccu RST_BUS_VE>;
			    power-domains = <&pd R528_PD_VE>;
			    iommus = <&mmu_aw 0 1>;
			    status = "okay";
		};

		twi0: twi@2502000{
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sun8i-twi";
			device_type = "twi0";
			reg = <0x0 0x02502000 0x0 0x400>;
			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_I2C0>;
			resets = <&ccu RST_BUS_I2C0>;
			clock-names = "bus";
			clock-frequency = <400000>;
			status = "disabled";
		};

		twi1: twi@2502400{
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sun8i-twi";
			device_type = "twi1";
			reg = <0x0 0x02502400 0x0 0x400>;
			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_I2C1>;
			resets = <&ccu RST_BUS_I2C1>;
			clock-names = "bus";
			clock-frequency = <200000>;
			status = "disabled";
		};

		twi2: twi@2502800{
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sun8i-twi";
			device_type = "twi2";
			reg = <0x0 0x02502800 0x0 0x400>;
			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_I2C2>;
			resets = <&ccu RST_BUS_I2C2>;
			clock-names = "bus";
			clock-frequency = <100000>;
			status = "disabled";
		};

		twi3: twi@2502c00{
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sun8i-twi";
			device_type = "twi3";
			reg = <0x0 0x02502c00 0x0 0x400>;
			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_I2C3>;
			resets = <&ccu RST_BUS_I2C3>;
			clock-names = "bus";
			clock-frequency = <100000>;
			status = "disabled";
		};

		ledc: ledc@2008000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sunxi-leds";
			reg = <0x0 0x02008000 0x0 0x400>;
			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "ledcirq";
			clocks = <&ccu CLK_LEDC>, <&ccu CLK_BUS_LEDC>;
			clock-names = "clk_ledc", "clk_cpuapb";
			dmas = <&dma 42>, <&dma 42>;
			dma-names = "rx", "tx";
			resets = <&ccu RST_BUS_LEDC>;
			reset-names = "ledc_reset";
			status = "disable";
		};

		pwm: pwm@2000c00 {
			#pwm-cells = <0x3>;
			compatible = "allwinner,sunxi-pwm";
			reg = <0x0 0x02000c00 0x0 0x400>;
			clocks = <&ccu CLK_BUS_PWM>;
			resets = <&ccu RST_BUS_PWM>;
			pwm-number = <8>;
			pwm-base = <0x0>;
			sunxi-pwms = <&pwm0>, <&pwm1>, <&pwm2>, <&pwm3>, <&pwm4>,
				<&pwm5>, <&pwm6>, <&pwm7>;
		};

		pwm0: pwm0@2000c10 {
			compatible = "allwinner,sunxi-pwm0";
			pinctrl-names = "active", "sleep";
			reg = <0x0 0x02000c10 0x0 0x4>;
			reg_base = <0x02000c00>;
		};

		pwm1: pwm1@2000c11 {
			compatible = "allwinner,sunxi-pwm1";
			pinctrl-names = "active", "sleep";
			reg = <0x0 0x02000c11 0x0 0x4>;
			reg_base = <0x02000c00>;
		};

		pwm2: pwm2@2000c12 {
			compatible = "allwinner,sunxi-pwm2";
			pinctrl-names = "active", "sleep";
			reg = <0x0 0x02000c12 0x0 0x4>;
			reg_base = <0x02000c00>;
		};

		pwm3: pwm3@2000c13 {
			compatible = "allwinner,sunxi-pwm3";
			pinctrl-names = "active", "sleep";
			reg = <0x0 0x02000c13 0x0 0x4>;
			reg_base = <0x02000c00>;
		};

		pwm4: pwm4@2000c14 {
			compatible = "allwinner,sunxi-pwm4";
			pinctrl-names = "active", "sleep";
			reg = <0x0 0x02000c14 0x0 0x4>;
			reg_base = <0x02000c00>;
		};

		pwm5: pwm5@2000c15 {
			compatible = "allwinner,sunxi-pwm5";
			pinctrl-names = "active", "sleep";
			reg = <0x0 0x02000c15 0x0 0x4>;
			reg_base = <0x02000c00>;
		};

		pwm6: pwm6@2000c16 {
			compatible = "allwinner,sunxi-pwm6";
			pinctrl-names = "active", "sleep";
			reg = <0x0 0x02000c16 0x0 0x4>;
			reg_base = <0x02000c00>;
		};

		pwm7: pwm7@2000c17 {
			compatible = "allwinner,sunxi-pwm7";
			pinctrl-names = "active", "sleep";
			reg = <0x0 0x02000c17 0x0 0x4>;
			reg_base = <0x02000c00>;
		};

		lcd_fb0: lcd_fb0@0 {
			compatible = "allwinner,sunxi-lcd_fb0";
			pinctrl-names = "active","sleep";

			status = "okay";
		};

		keyboard0: keyboard@2009800 {
			compatible = "allwinner,keyboard_1350mv";
			reg = <0x0 0x02009800 0x0 0x400>;
			interrupts = <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>;
			clocks = <&ccu CLK_BUS_LRADC>;
			clock-names = "mclk";
			resets = <&ccu RST_BUS_LRADC>;
			key_cnt = <5>;
			key0 = <210 115>;
			key1 = <410 114>;
			key2 = <590 139>;
			key3 = <750 28>;
			key4 = <880 172>;
			wakeup-source;
			status = "okay";
		};

		sid@3006000 {
			compatible = "allwinner,sun8iw20p1-sid", "allwinner,sunxi-sid";
			reg = <0x0 0x03006000 0 0x1000>;
			#address-cells = <1>;
			#size-cells = <1>;

			secure_status {
				reg = <0x0 0>;
				offset = <0xa0>;
				size = <0x4>;
			};

			chipid {
				reg = <0x0 0>;
				offset = <0x200>;
				size = <0x10>;
			};

			rotpk {
				reg = <0x0 0>;
				offset = <0x140>;
				size = <0x4>;
			};

			speedbin_efuse: speedbin@00 {
				reg = <0x00 4>;
			};

			cpubin_efuse: cpubin@28 {
				reg = <0x28 4>;
			};

			ths_calib: calib@14 {
				reg = <0x14 8>;
			};
		};

		gpadc: gpadc@2009000 {
			compatible = "allwinner,sunxi-gpadc";
			reg = <0x0 0x02009000 0x0 0x400>;
			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_GPADC>;
			clock-names = "bus";
			resets = <&ccu RST_BUS_GPADC>;
			status = "okay";
		};

		vind0: vind@5800800 {
			compatible = "allwinner,sunxi-vin-media", "simple-bus";
			#address-cells = <2>;
			#size-cells = <2>;
			ranges;
			device_id = <0>;
			csi_top = <336000000>;
			csi_isp = <327000000>;
			reg = <0x0 0x05800800 0x0 0x200>,
				<0x0 0x05800000 0x0 0x800>;
			clocks = <&ccu CLK_CSI_TOP>, <&ccu CLK_PLL_VIDEO1_2X>,
				<&ccu CLK_CSI0_MCLK>, <&dcxo24M>, <&ccu CLK_PLL_VIDEO1>,
				<&ccu CLK_BUS_CSI>, <&ccu CLK_MBUS_CSI>;
			clock-names = "csi_top", "csi_top_src",
					"csi_mclk0", "csi_mclk0_24m", "csi_mclk0_pll",
					"csi_bus", "csi_mbus";
			resets = <&ccu RST_BUS_CSI>;
			reset-names = "csi_ret";
			pinctrl-names = "mclk0-default", "mclk0-sleep";
			pinctrl-0 = <&csi_mclk0_pins_a>;
			pinctrl-1 = <&csi_mclk0_pins_b>;
			status = "okay";

			csi0: csi@5801000{
				compatible = "allwinner,sunxi-csi";
				reg = <0x0 0x05801000 0x0 0x1000>;
				interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
				pinctrl-names = "default","sleep";
				pinctrl-0 = <&csi0_pins_a>;
				pinctrl-1 = <&csi0_pins_b>;
				device_id = <0>;
				iommus = <&mmu_aw 1 1>;
				status = "okay";
			};
			isp0: isp@5809410 {
				compatible = "allwinner,sunxi-isp";
				reg = <0x0 0x05809410 0x0 0x10>;
				device_id = <0xfe>;

				status = "okay";
			};
			isp1: isp@5809420 {
				compatible = "allwinner,sunxi-isp";
				reg = <0x0 0x05809420 0x0 0x10>;
				device_id = <0xff>;
				status = "okay";
			};
			scaler0: scaler@5809430 {
				compatible = "allwinner,sunxi-scaler";
				reg = <0x0 0x05809430 0x0 0x10>;
				device_id = <0xfe>;
				status = "okay";
			};
			scaler1: scaler@5809440 {
				compatible = "allwinner,sunxi-scaler";
				reg = <0x0 0x05809440 0x0 0x10>;
				device_id = <0xff>;
				status = "okay";
			};
			actuator0: actuator@5809450 {
				compatible = "allwinner,sunxi-actuator";
				device_type = "actuator0";
				reg = <0x0 0x05809450 0x0 0x10>;
				actuator0_name = "ad5820_act";
				actuator0_slave = <0x18>;
				actuator0_af_pwdn = <>;
				actuator0_afvdd = "afvcc-csi";
				actuator0_afvdd_vol = <2800000>;
				status = "disabled";
			};
			flash0: flash@5809460 {
				device_type = "flash0";
				compatible = "allwinner,sunxi-flash";
				reg = <0x0 0x05809460 0x0 0x10>;
				flash0_type = <2>;
				flash0_en = <>;
				flash0_mode = <>;
				flash0_flvdd = "";
				flash0_flvdd_vol = <>;
				device_id = <0>;
				status = "disabled";
			};
			sensor0: sensor@5809470 {
				reg = <0x0 0x05809470 0x0 0x10>;
				device_type = "sensor0";
				compatible = "allwinner,sunxi-sensor";
				sensor0_mname = "ov5640";
				sensor0_twi_cci_id = <2>;
				sensor0_twi_addr = <0x78>;
				sensor0_mclk_id = <0>;
				sensor0_pos = "rear";
				sensor0_isp_used = <0>;
				sensor0_fmt = <0>;
				sensor0_stby_mode = <0>;
				sensor0_vflip = <0>;
				sensor0_hflip = <0>;
				sensor0_iovdd-supply = <>;
				sensor0_iovdd_vol = <>;
				sensor0_avdd-supply = <>;
				sensor0_avdd_vol = <>;
				sensor0_dvdd-supply = <>;
				sensor0_dvdd_vol = <>;
				sensor0_power_en = <>;
				sensor0_reset = <&pio PE 9 GPIO_ACTIVE_LOW>;
				sensor0_pwdn = <&pio PE 8 GPIO_ACTIVE_LOW>;
				sensor0_sm_vs = <>;
				flash_handle = <&flash0>;
				act_handle = <&actuator0>;
				device_id = <0>;
				status	= "okay";
			};
			sensor1: sensor@5809480 {
				reg = <0x0 0x05809480 0x0 0x10>;
				device_type = "sensor1";
				compatible = "allwinner,sunxi-sensor";
				sensor1_mname = "ov5647";
				sensor1_twi_cci_id = <3>;
				sensor1_twi_addr = <0x6c>;
				sensor1_mclk_id = <1>;
				sensor1_pos = "front";
				sensor1_isp_used = <0>;
				sensor1_fmt = <0>;
				sensor1_stby_mode = <0>;
				sensor1_vflip = <0>;
				sensor1_hflip = <0>;
				sensor1_iovdd-supply = <>;
				sensor1_iovdd_vol = <>;
				sensor1_avdd-supply = <>;
				sensor1_avdd_vol = <>;
				sensor1_dvdd-supply = <>;
				sensor1_dvdd_vol = <>;
				sensor1_power_en = <>;
				sensor1_reset = <&pio PE 7 GPIO_ACTIVE_LOW>;
				sensor1_pwdn = <&pio PE 6 GPIO_ACTIVE_LOW>;
				sensor1_sm_vs = <>;
				flash_handle = <>;
				act_handle = <>;
				device_id = <1>;
				status	= "okay";
			};
			vinc0: vinc@5809000 {
				compatible = "allwinner,sunxi-vin-core";
				device_type = "vinc0";
				reg = <0x0 0x05809000 0x0 0x200>;
				interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
				vinc0_csi_sel = <0>;
				vinc0_mipi_sel = <0xff>;
				vinc0_isp_sel = <0>;
				vinc0_tdm_rx_sel = <0xff>;
				vinc0_rear_sensor_sel = <0>;
				vinc0_front_sensor_sel = <0>;
				vinc0_sensor_list = <0>;
				device_id = <0>;
				iommus = <&mmu_aw 1 1>;
				status = "okay";
			};
			vinc1: vinc@5809200 {
				device_type = "vinc1";
				compatible = "allwinner,sunxi-vin-core";
				reg = <0x0 0x05809200 0x0 0x200>;
				interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
				vinc1_csi_sel = <0>;
				vinc1_mipi_sel = <0xff>;
				vinc1_isp_sel = <1>;
				vinc1_tdm_rx_sel = <0xff>;
				vinc1_rear_sensor_sel = <0>;
				vinc1_front_sensor_sel = <0>;
				vinc1_sensor_list = <0>;
				device_id = <1>;
				iommus = <&mmu_aw 1 1>;
				status = "okay";
			};

		};
		s_cir0: s_cir@7040000 {
			compatible = "allwinner,s_cir";
			reg = <0x0 0x07040000 0x0 0x400>;
			interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&r_ccu CLK_R_APB0_BUS_IRRX>, <&dcxo24M>, <&r_ccu CLK_R_APB0_IRRX>;
			clock-names = "bus", "pclk", "mclk";
			resets = <&r_ccu RST_R_APB0_BUS_IRRX>;
			status = "disabled";
		};

		ir1: ir@2003000 {
			compatible = "allwinner,irtx";
			reg = <0x0 0x02003000 0x0 0x400>;
			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_IR_TX>, <&dcxo24M>, <&ccu CLK_IR_TX>;
			clock-names = "bus", "pclk", "mclk";
			resets = <&ccu RST_BUS_IR_TX>;
			status = "disabled";
		};

		di: deinterlace@5400000 {
			compatible = "allwinner,sunxi-deinterlace";
			reg = <0x0 0x05400000 0x0 0x0000ffff>;
			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_DI>,
				 <&ccu CLK_BUS_DI>,
				 <&ccu CLK_PLL_PERIPH0_2X>;
			clock-names = "clk_di",
				      "pll_periph",
				      "clk_bus_di";
			resets = <&ccu RST_BUS_DI>;
			reset-names = "rst_bus_di";

			assigned-clocks = <&ccu CLK_DI>;
			assigned-clock-parents = <&ccu CLK_PLL_PERIPH0_2X>;
			assigned-clock-rates = <300000000>;

			iommus = <&mmu_aw 4 1>;
			status = "okay";
		};

		g2d: g2d@5410000 {
			compatible = "allwinner,sunxi-g2d";
			reg = <0x0 0x05410000 0x0 0x3ffff>;
			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_G2D>, <&ccu CLK_G2D>, <&ccu CLK_MBUS_G2D>;
			clock-names = "bus", "g2d", "mbus_g2d";
			resets = <&ccu RST_BUS_G2D>;
			iommus = <&mmu_aw 3 1>;
			status = "okay";
		};

		disp: disp@5000000 {
			compatible = "allwinner,sunxi-disp";
			reg = <0x0 0x05000000 0x0 0x3fffff>,	/* de0 */
			      <0x0 0x05460000 0x0 0xfff>,	/*display_if_top*/
			      <0x0 0x05461000 0x0 0xfff>,	/* tcon-lcd0 */
			      <0x0 0x05470000 0x0 0xfff>,	/* tcon-tv */
			      <0x0 0x05450000 0x0 0x1fff>;	/* dsi0*/
			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,/*tcon-lcd0*/
				     <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,/*tcon-tv */
				     <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;/*dsi*/
			clocks = <&ccu CLK_DE0>,
				 <&ccu CLK_DE0>,
				 <&ccu CLK_BUS_DE0>,
				 <&ccu CLK_BUS_DE0>,
				 <&ccu CLK_BUS_DPSS_TOP0>,
				 <&ccu CLK_BUS_DPSS_TOP0>,
				 <&ccu CLK_MIPI_DSI>,
				 <&ccu CLK_BUS_MIPI_DSI>,
				 <&ccu CLK_TCON_LCD0>,
				 <&ccu CLK_TCON_TV>,
				 <&ccu CLK_BUS_TCON_LCD0>,
				 <&ccu CLK_BUS_TCON_TV>,
				 <&ccu CLK_MIPI_DSI>,
				 <&ccu CLK_BUS_MIPI_DSI>;
			clock-names = "clk_de0",
					"clk_de1",
					"clk_bus_de0",
					"clk_bus_de1",
					"clk_bus_dpss_top0",
					"clk_bus_dpss_top1",
					"clk_mipi_dsi0",
					"clk_bus_mipi_dsi0",
					"clk_tcon0",
					"clk_tcon1",/*tcon-tv actually*/
					"clk_bus_tcon0",
					"clk_bus_tcon1",/*tcon-tv actually*/
					"clk_mipi_dsi0",
					"clk_bus_mipi_dsi0";
			resets = <&ccu RST_BUS_DE0>,
				 <&ccu RST_BUS_DE0>,
				 <&ccu RST_BUS_DPSS_TOP0>,
				 <&ccu RST_BUS_DPSS_TOP0>,
				 <&ccu RST_BUS_MIPI_DSI>,
				 <&ccu RST_BUS_TCON_LCD0>,
				 <&ccu RST_BUS_TCON_TV>,
				 <&ccu RST_BUS_LVDS0>;
			reset-names = "rst_bus_de0",
					"rst_bus_de1",
					"rst_bus_dpss_top0",
					"rst_bus_dpss_top1",
					"rst_bus_mipi_dsi0",
					"rst_bus_tcon0",
					"rst_bus_tcon1",
					"rst_bus_lvds0";

			assigned-clocks = <&ccu CLK_DE0>,
			<&ccu CLK_MIPI_DSI>,
			<&ccu CLK_TCON_LCD0>,
			<&ccu CLK_TCON_TV>;
			assigned-clock-parents = <&ccu CLK_PLL_PERIPH0_2X>,
			<&ccu CLK_PLL_PERIPH0>,
			<&ccu CLK_PLL_VIDEO0_4X>,
			<&ccu CLK_PLL_VIDEO1_4X>;
			assigned-clock-rates = <300000000>,
			<150000000>,
			<0>,
			<0>;

			boot_disp = <0>;
			boot_disp1 = <0>;
			boot_disp2 = <0>;
			fb_base = <0>;
			iommus = <&mmu_aw 2 0>;
			status = "okay";
		};

		lcd0: lcd0@5461000 {
			compatible = "allwinner,sunxi-lcd0";
			reg = <0x0 0x05461000 0x0 0xfff>;
			pinctrl-names = "active","sleep";
			status = "okay";
		};

		tv0: tv0@5600000 {
			compatible = "allwinner,sunxi-tv";
			reg = <0x0 0x05600000 0x0 0x3fff>,
				<0x0 0x05604000 0x0 0x3fff>;
			clocks = <&ccu CLK_BUS_TVE_TOP>,
				 <&ccu CLK_TVE>,
				 <&ccu CLK_BUS_TVE>;
			clock-names = "clk_bus_tve_top",
				      "clk_tve",
				      "clk_bus_tve";
			resets = <&ccu RST_BUS_TVE_TOP>,
				 <&ccu RST_BUS_TVE>;
			reset-names = "rst_bus_tve_top", "rst_bus_tve";

			device_type = "tv0";
			pinctrl-names = "active","sleep";
			status = "okay";
		};

		hwspinlock: hwspinlock@0x3005000 {
			compatible = "allwinner,sunxi-hwspinlock";
			reg = <0x0 0x3005000 0x0 0x1000>;
			#hwlock-cells = <1>;
			clocks = <&ccu CLK_BUS_SPINLOCK>;
			clock-names = "clk_hwspinlock_bus";
			resets = <&ccu RST_BUS_SPINLOCK>;
			reset-names = "rst";
			num-locks = <32>;
			status = "disabled";
		};
		/* old msgbox in dts
		msgbox: msgbox@3003000 {
			compatible = "sunxi,msgbox-amp";
			reg = <0x0 0x03003000 0x0 0x1000>,
			      <0x0 0x01701000 0x0 0x1000>,
			      <0x0 0x0601f000 0x0 0x1000>;
			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_MSGBOX0>;
			rpmsg_id = "sunxi,dsp-msgbox","sunxi,dsp-power-msgbox";
			resets = <&ccu RST_BUS_MSGBOX0>;
			reset-names = "rst";
			msgbox_amp_counts = <3>;
			msgbox_amp_local = <0>;
			rpmsg_amp_remote-0 = <1>;
			rpmsg_read_channel-0 = <1>;
			rpmsg_write_channel-0 = <1>;
			rpmsg_amp_remote-1 = <1>;
			rpmsg_read_channel-1 = <0>;
			rpmsg_write_channel-1 = <0>;
		}; */
		msgbox: msgbox@3003000 {
			compatible = "allwinner,sun8iw20-msgbox";
			#mbox-cells = <1>;
			reg = <0x0 0x03003000 0x0 0x1000>,
			      <0x0 0x01701000 0x0 0x1000>,
			      <0x0 0x0601f000 0x0 0x1000>;
			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_MSGBOX0>;
			resets = <&ccu RST_BUS_MSGBOX0>;
			reset-names = "rst";
			local_id = <0>;
			status = "okay";
		};

		hdmi: hdmi@5500000 {
			compatible = "allwinner,sunxi-hdmi";
			reg = <0x0 0x05500000 0x0 0xfffff>;
			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_HDMI>,
				<&ccu CLK_HDMI_24M>,
				<&ccu CLK_HDMI_CEC>,
				<&ccu CLK_TCON_TV>;
			clock-names = "clk_bus_hdmi",
					"clk_ddc",
					"clk_cec",
					"clk_tcon_tv";
			resets = <&ccu RST_BUS_HDMI_SUB>,
				<&ccu RST_BUS_HDMI_MAIN>;
			reset-names = "rst_bus_sub",
				      "rst_bus_main";
			assigned-clocks = <&ccu CLK_HDMI_CEC>;
			assigned-clock-parents = <&ccu CLK_HDMI_CEC_32K>;
			assigned-clock-rates = <0>;
			status = "okay";
		};
		usbc0:usbc0@0 {
			device_type = "usbc0";
			compatible = "allwinner,sunxi-otg-manager";
			usb_port_type = <2>;
			usb_detect_type = <1>;
			usb_id_gpio;
			usb_det_vbus_gpio;
			usb_regulator_io = "nocare";
			usb_wakeup_suspend = <0>;
			usb_luns = <3>;
			usb_serial_unique = <0>;
			usb_serial_number = "20080411";
			rndis_wceis = <1>;
			status = "okay";
		};

		udc:udc-controller@0x04100000 {
			compatible = "allwinner,sunxi-udc";
			reg = <0x0 0x04100000 0x0 0x1000>, /*udc base*/
			      <0x0 0x00000000 0x0 0x100>; /*sram base*/
			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_OTG>;
			clock-names = "bus_otg";
			resets = <&ccu RST_BUS_OTG>, <&ccu RST_USB_PHY0>;
			reset-names = "otg", "phy";
			status = "okay";
		};

		ehci0:ehci0-controller@0x04101000 {
			compatible = "allwinner,sunxi-ehci0";
			reg = <0x0 0x04101000 0x0 0xFFF>, /*hci0 base*/
			      <0x0 0x00000000 0x0 0x100>, /*sram base*/
			      <0x0 0x04100000 0x0 0x1000>; /*otg base*/
			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_EHCI0>;
			clock-names = "bus_hci";
			resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_USB_PHY0>;
			reset-names = "hci", "phy";
			hci_ctrl_no = <0>;
			status = "okay";
		};

		ohci0:ohci0-controller@0x04101400 {
			compatible = "allwinner,sunxi-ohci0";
			reg = <0x0 0x04101400 0x0 0xFFF>, /*hci0 base*/
			      <0x0 0x00000000 0x0 0x100>, /*sram base*/
			      <0x0 0x04100000 0x0 0x1000>; /*otg base*/
			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_OHCI0>, <&ccu CLK_USB_OHCI0>;
			clock-names = "bus_hci", "ohci";
			resets = <&ccu RST_BUS_OHCI0>, <&ccu RST_USB_PHY0>;
			reset-names = "hci", "phy";
			hci_ctrl_no = <0>;
			status = "okay";
		};

		usbc1:usbc1@0 {
			device_type = "usbc1";
			usb_regulator_io = "nocare";
			usb_wakeup_suspend = <0>;
			status = "disable";
		};

		ehci1:ehci1-controller@0x04200000 {
			compatible = "allwinner,sunxi-ehci1";
			reg = <0x0 0x04200000 0x0 0xFFF>, /*ehci1 base*/
			      <0x0 0x00000000 0x0 0x100>, /*sram base*/
			      <0x0 0x04100000 0x0 0x1000>; /*otg base*/
			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_EHCI1>;
			clock-names = "bus_hci";
			resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_USB_PHY1>;
			reset-names = "hci", "phy";
			hci_ctrl_no = <1>;
			status = "disable";
		};

		ohci1:ohci1-controller@0x04200400 {
			compatible = "allwinner,sunxi-ohci1";
			reg = <0x0 0x04200400 0x0 0xFFF>, /*ohci1 base*/
			      <0x0 0x00000000 0x0 0x100>, /*sram base*/
			      <0x0 0x04100000 0x0 0x1000>; /*otg base*/
			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_OHCI1>, <&ccu CLK_USB_OHCI1>;
			clock-names = "bus_hci", "ohci";
			resets = <&ccu RST_BUS_OHCI1>, <&ccu RST_USB_PHY1>;
			reset-names = "hci", "phy";
			hci_ctrl_no = <1>;
			status = "disable";
		};

		/* codec addr: 0x02030000, the others is invalid to avoid build warining */
		codec:codec@2030000 {
			#sound-dai-cells = <0>;
			compatible = "allwinner,sunxi-internal-codec";
			reg = <0x0 0x02030000 0x0 0x34c>;
			clocks = <&ccu CLK_PLL_AUDIO0>,
				 <&ccu CLK_PLL_AUDIO1_DIV5>,
				 <&ccu CLK_AUDIO_DAC>,
				 <&ccu CLK_AUDIO_ADC>,
				 <&ccu CLK_BUS_AUDIO_CODEC>;
			clock-names = "pll_audio0", "pll_audio1_div5",
				      "audio_clk_dac", "audio_clk_adc",
				      "audio_clk_bus";
			resets = <&ccu RST_BUS_AUDIO_CODEC>;
			rx_sync_en  = <0x00>;
			device_type = "codec";
			status = "okay";
		};

		dummy_cpudai:dummy_cpudai@203034c {
			compatible = "allwinner,sunxi-dummy-cpudai";
			reg = <0x0 0x0203034c 0x0 0x4>;
			tx_fifo_size    = <128>;
			rx_fifo_size    = <256>;
			dac_txdata      = <0x02030020>;
			adc_txdata      = <0x02030040>;
			playback_cma    = <128>;
			capture_cma     = <256>;
			device_type = "cpudai";
			dmas = <&dma 7>, <&dma 7>;
			dma-names = "tx", "rx";
			status = "okay";
		};

		sndcodec:sound@2030340 {
			compatible = "allwinner,sunxi-codec-machine";
			reg = <0x0 0x02030340 0x0 0x4>;
			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
			sunxi,audio-codec = <&codec>;
			sunxi,cpudai-controller = <&dummy_cpudai>;
			device_type = "sndcodec";
			status = "okay";
		};

		sunxi_rpaf_dsp0:rpaf-dsp@203034c {
			compatible = "allwinner,rpaf-dsp0";
			device_type = "sunxi_rpaf_dsp0";
			dsp_id = <0x0>;
			status = "okay";
		};

		/* dmic addr: 0x02031000, the others is invalid to avoid build warining */
		dmic:dmic@2031000{
			#sound-dai-cells = <0>;
			compatible = "allwinner,sunxi-dmic";
			reg = <0x0 0x02031000 0x0 0x50>;
			clocks = <&ccu CLK_PLL_AUDIO0>, /* 98.304M / 90.3168M */
				 <&ccu CLK_DMIC>,
				 <&ccu CLK_BUS_DMIC>;
			clock-names = "pll_audio", "dmic", "dmic_bus";
			resets = <&ccu RST_BUS_DMIC>;
			dmas		= <&dma 8>;
			dma-names	= "rx";
			interrupts	= <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
			clk_parent	= <0x1>;
			capture_cma	= <256>;
			data_vol	= <0xB0>;
			rx_chmap	= <0x76543210>;
			rx_sync_en      = <0x00>;
			device_type = "dmic";
			status = "disabled";
		};

		dmic_codec:sound@2031050{
			#sound-dai-cells = <0>;
			compatible = "dmic-codec";
			reg = <0x0 0x02031050 0x0 0x4>;
			num-channels = <8>;
		};

		sounddmic:sounddmic@2031060 {
			reg = <0x0 0x02031060 0x0 0x4>;
			compatible = "sunxi,simple-audio-card";
			simple-audio-card,name = "snddmic";
			simple-audio-card,capture_only;
			status = "disabled";
			/* simple-audio-card,format = "i2s"; */
			simple-audio-card,cpu {
				sound-dai = <&dmic>;
			};
			simple-audio-card,codec {
				sound-dai = <&dmic_codec>;
			};
		};

		/* daudio0 addr: 0x02032000, the others is invalid to avoid build warining */
		daudio0:daudio@2032000 {
			#sound-dai-cells = <0>;
			compatible = "allwinner,sunxi-daudio";
			reg = <0x0 0x02032000 0x0 0xa0>;
			clocks = <&ccu CLK_PLL_AUDIO0>, /* 98.304M / 90.3168M */
				 <&ccu CLK_I2S0>,
				 <&ccu CLK_BUS_I2S0>;
			clock-names = "pll_audio", "i2s0", "i2s0_bus";
			resets = <&ccu RST_BUS_I2S0>;
			dmas		= <&dma 3>, <&dma 3>;
			dma-names	= "tx", "rx";
			interrupts	= <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl_used		= <0x01>;
			sign_extend		= <0x00>;
			tx_data_mode		= <0x00>;
			rx_data_mode		= <0x00>;
			msb_lsb_first		= <0x00>;
			pcm_lrck_period		= <0x80>;
			slot_width_select	= <0x20>;
			frametype		= <0x00>;
			tdm_config		= <0x01>;
			tdm_num			= <0x00>;
			mclk_div		= <0x00>;
			clk_parent		= <0x00>;
			capture_cma		= <128>;
			playback_cma		= <128>;
			tx_num			= <4>;
			tx_chmap1		= <0x76543210>;
			tx_chmap0		= <0xFEDCBA98>;
			rx_num			= <4>;
			rx_chmap3		= <0x03020100>;
			rx_chmap2		= <0x07060504>;
			rx_chmap1		= <0x0B0A0908>;
			rx_chmap0		= <0x0F0E0D0C>;
			asrc_function_en	= <0x00>;
			rx_sync_en              = <0x00>;
			device_type = "daudio0";
			status = "disabled";
		};

		sounddaudio0: sounddaudio0@20320a0 {
			reg = <0x0 0x020320a0 0x0 0x4>;
			compatible = "sunxi,simple-audio-card";
			simple-audio-card,name = "snddaudio0";
			simple-audio-card,format = "i2s";
			status = "disabled";
			/* simple-audio-card,frame-master = <&daudio0_master>; */
			/* simple-audio-card,bitclock-master = <&daudio0_master>; */
			/* simple-audio-card,bitclock-inversion; */
			/* simple-audio-card,frame-inversion; */
			simple-audio-card,cpu {
				sound-dai = <&daudio0>;
			};
		};

		/* daudio1 addr: 0x02033000, the others is invalid to avoid build warining */
		daudio1:daudio@2033000 {
			#sound-dai-cells = <0>;
			compatible = "allwinner,sunxi-daudio";
			reg = <0x0 0x02033000 0x0 0xa0>;
			clocks = <&ccu CLK_PLL_AUDIO0>, /* 98.304M / 90.3168M */
				 <&ccu CLK_I2S1>,
				 <&ccu CLK_BUS_I2S1>;
			clock-names = "pll_audio", "i2s1", "i2s1_bus";
			resets = <&ccu RST_BUS_I2S1>;
			dmas		= <&dma 4>, <&dma 4>;
			dma-names	= "tx", "rx";
			interrupts	= <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl_used		= <0x01>;
			sign_extend		= <0x00>;
			tx_data_mode		= <0x00>;
			rx_data_mode		= <0x00>;
			msb_lsb_first		= <0x00>;
			pcm_lrck_period		= <0x80>;
			slot_width_select	= <0x20>;
			frametype		= <0x00>;
			tdm_config		= <0x01>;
			tdm_num			= <0x01>;
			mclk_div		= <0x00>;
			clk_parent		= <0x00>;
			capture_cma		= <128>;
			playback_cma		= <128>;
			tx_num			= <4>;
			tx_chmap1		= <0x76543210>;
			tx_chmap0		= <0xFEDCBA98>;
			rx_num			= <4>;
			rx_chmap3		= <0x03020100>;
			rx_chmap2		= <0x07060504>;
			rx_chmap1		= <0x0B0A0908>;
			rx_chmap0		= <0x0F0E0D0C>;
			asrc_function_en	= <0x00>;
			rx_sync_en              = <0x00>;
			device_type = "daudio1";
			status = "disabled";
		};

		sounddaudio1: sounddaudio1@20330a0 {
			reg = <0x0 0x020330a0 0x0 0x4>;
			compatible = "sunxi,simple-audio-card";
			simple-audio-card,name = "snddaudio1";
			simple-audio-card,format = "i2s";
			status = "disabled";
			simple-audio-card,cpu {
				sound-dai = <&daudio1>;
			};
		};

		/* daudio2 addr: 0x02034000, the others is invalid to avoid build warining */
		daudio2:daudio@2034000 {
			#sound-dai-cells = <0>;
			compatible = "allwinner,sunxi-daudio";
			reg = <0x0 0x02034000 0x0 0xa0>;
			clocks = <&ccu CLK_PLL_AUDIO0>, /* 98.304M / 90.3168M */
				 <&ccu CLK_I2S2>,
				 <&ccu CLK_BUS_I2S2>,
				 <&ccu CLK_PLL_AUDIO0_4X>,
				 <&ccu CLK_I2S2_ASRC>;
			resets = <&ccu RST_BUS_I2S2>;
			dmas		= <&dma 5>, <&dma 5>;
			dma-names	= "tx", "rx";
			interrupts	= <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl_used		= <0x01>;
			daudio_type		= <0x00>;
			sign_extend		= <0x00>;
			tx_data_mode		= <0x00>;
			rx_data_mode		= <0x00>;
			msb_lsb_first		= <0x00>;
			pcm_lrck_period		= <0x80>;
			slot_width_select	= <0x20>;
			frametype		= <0x00>;
			tdm_config		= <0x01>;
			tdm_num			= <0x02>;
			mclk_div		= <0x01>;
			clk_parent		= <0x00>;
			capture_cma		= <128>;
			playback_cma		= <128>;
			tx_num			= <4>;
			tx_chmap1		= <0x76543210>;
			tx_chmap0		= <0xFEDCBA98>;
			rx_num			= <4>;
			rx_chmap3		= <0x03020100>;
			rx_chmap2		= <0x07060504>;
			rx_chmap1		= <0x0B0A0908>;
			rx_chmap0		= <0x0F0E0D0C>;
			asrc_function_en	= <0x00>;
			rx_sync_en              = <0x00>;
			device_type = "daudio2";
			status = "disabled";
		};

		sounddaudio2: sounddaudio2@20340a0 {
			reg = <0x0 0x020340a0 0x0 0x4>;
			compatible = "sunxi,simple-audio-card";
			simple-audio-card,name = "snddaudio2";
			simple-audio-card,format = "i2s";
			status = "disabled";
			simple-audio-card,cpu {
				sound-dai = <&daudio2>;
			};
		};

		hdmiaudio: hdmiaudio@20340a4 {
			#sound-dai-cells = <0>;
			reg = <0x0 0x020340a4 0x0 0x4>;
			compatible = "allwinner,sunxi-hdmiaudio";
			status = "disabled";
		};

		/* spdif addr: 0x02036000, the others is invalid to avoid build warining */
		spdif:spdif@2036000 {
			#sound-dai-cells = <0>;
			compatible = "allwinner,sunxi-spdif";
			reg = <0x0 0x02036000 0x0 0x58>;
			clocks = <&ccu CLK_PLL_AUDIO0_4X>,	/* 90.3168M */
				 <&ccu CLK_SPDIF_TX>,
				 <&ccu CLK_BUS_SPDIF>,
				 <&ccu CLK_PLL_AUDIO1>,         /* 98.304M */
				 <&ccu CLK_PLL_AUDIO1_DIV5>,
				 <&ccu CLK_PLL_PERIPH0>,
				 <&ccu CLK_SPDIF_RX>;
			clock-names = "pll_audio0", "spdif", "spdif_bus",
				      "pll_audio1", "pll_audio1_div5",
				      "pll_periph", "spdif_rx";
			resets = <&ccu RST_BUS_SPDIF>;
			dmas		= <&dma 2>, <&dma 2>;
			dma-names	= "tx", "rx";
			interrupts	= <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
			clk_parent	= <0x1>;
			playback_cma	= <128>;
			capture_cma	= <128>;
			rx_sync_en      = <0>;
			device_type = "spdif";
			status = "disabled";
		};

		soundspdif:soundspdif@203605c {
			reg = <0x0 0x0203605c 0x0 0x4>;
			compatible = "sunxi,simple-audio-card";
			simple-audio-card,name = "sndspdif";
			status = "disabled";
			 /* simple-audio-card,format = "i2s"; */
			 simple-audio-card,cpu {
				 sound-dai = <&spdif>;
			 };
			 simple-audio-card,codec {
				 /*snd-soc-dummy*/
			 };
		};

		ths: ths@02009400 {
			compatible = "allwinner,sun8iw20p1-ths";
			reg = <0x0 0x02009400 0x0 0x400>;
			clocks = <&ccu CLK_BUS_THS>;
			clock-names = "bus";
			resets = <&ccu RST_BUS_THS>;
			nvmem-cells = <&ths_calib>;
			nvmem-cell-names = "calibration";
			#thermal-sensor-cells = <1>;
		};

		tvd: tvd@05c00000 {
			compatible = "allwinner,sunxi-tvd";
			reg = <0x0 0x05c00000 0x0 0x00010000>;/*tvd_top*/
			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&ccu CLK_BUS_TVD_TOP>,
			<&ccu CLK_MBUS_TVIN>;
			clock-names = "clk_bus_tvd_top",
			"clk_mbus_tvd";

			resets = <&ccu RST_BUS_TVD_TOP>;
			reset-names = "rst_bus_tvd_top";

			tvd-number = <1>;
			tvds = <&tvd0>;
			status = "okay";
		};

		tvd0: tvd0@05c01000 {
			compatible = "allwinner,sunxi-tvd0";
			reg = <0x0 0x05c01000 0x0 0x00010000>;
			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&ccu CLK_TVD>,
			<&ccu CLK_BUS_TVD>;
			clock-names = "clk_tvd0","clk_bus_tvd0";

			resets = <&ccu RST_BUS_TVD>;
			reset-names = "rst_bus_tvd0";

			assigned-clocks = <&ccu CLK_TVD>;
			assigned-clock-parents = <&ccu CLK_PLL_VIDEO1>;

			tvd_used = <1>;
			tvd_if = <0>;
			status = "okay";
		};

	};
};

sun8iw20p1.dtsi

/*
 * Allwinner Technology CO., Ltd. sun8iw20p1 platform
 *
 * modify base on juno.dts
 */
 /* optee used 7MB: SHM 2M: OS: 1M: TA:4M*/
/memreserve/ 0x41B00000 0x00100000;

#include <dt-bindings/clock/sun8iw20-ccu.h>
#include <dt-bindings/clock/sun8iw20-r-ccu.h>
#include <dt-bindings/clock/sun8iw20-rtc.h>
#include <dt-bindings/reset/sun8iw20-ccu.h>
#include <dt-bindings/reset/sun8iw20-r-ccu.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/gpio/sun4i-gpio.h>
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/power/r528-power.h>

/ {
	model = "sun8iw20";
	compatible = "allwinner,sun8iw20p1";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		serial3 = &uart3;
		serial4 = &uart4;
		serial5 = &uart5;
		spi0 = &spi0;
		spi1 = &spi1;
		twi0 = &twi0;
		twi1 = &twi1;
		twi2 = &twi2;
		twi3 = &twi3;
		mmc0 = &sdc0;
		mmc2 = &sdc2;
		pwm = &pwm;
		pwm0 = &pwm0;
		pwm1 = &pwm1;
		pwm2 = &pwm2;
		pwm3 = &pwm3;
		pwm4 = &pwm4;
		pwm5 = &pwm5;
		pwm6 = &pwm6;
		pwm7 = &pwm7;
		ir0 = &s_cir0;
		ve0 = &ve;
		tv0 = &tv0;
		tvd = &tvd;
		tvd0 = &tvd0;
		share_space0 = &share_space0;
	};

	chosen {
		bootargs = "earlyprintk=sunxi-uart,0x2500000 loglevel=8 initcall_debug=0 console=ttyS0 init=/init";
		//bootargs = "loglevel=8 initcall_debug=0 console=ttyS0 init=/init";
		linux,initrd-start = <0x0 0x0>;
		linux,initrd-end = <0x0 0x0>;
	};

	firmware {
		optee {
			compatible = "linaro,optee-tz";
			method = "smc";
		};
	};

	cpus {
		enable-method = "allwinner,sun8iw20p1";
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7","arm,armv7";
			reg = <0x0>;
			enable-method = "psci";
			clocks = <&ccu CLK_CPUX>;
			dynamic-power-coefficient = <156>;
			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
			operating-points-v2 = <&cpu_opp_table>;
			#cooling-cells = <2>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a7","arm,armv7";
			reg = <0x1>;
			enable-method = "psci";
			clocks = <&ccu CLK_CPUX>;
			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
			operating-points-v2 = <&cpu_opp_table>;
			#cooling-cells = <2>;
		};

		idle-states {
			entry-method = "arm,psci";

			CPU_SLEEP: cpu-sleep {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x0010000>;
				entry-latency-us = <46>;
				exit-latency-us = <59>;
				min-residency-us = <3570>;
				local-timer-stop;
			};

			CLUSTER_SLEEP: cluster-sleep {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x1010000>;
				entry-latency-us = <47>;
				exit-latency-us = <74>;
				min-residency-us = <5000>;
				local-timer-stop;
			};
		};

	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	dump_reg: dump_reg@20000 {
		compatible = "allwinner,sunxi-dump-reg";
		reg = <0x0 0x00020000 0x0 0x0004>;
		/* 0x00020000: dump_reg test addr, 0x0004: dump_reg test size */
	};

	cpu_opp_table: cpu-opp-table {
		compatible = "allwinner,sun50i-operating-points";
		nvmem-cells = <&speedbin_efuse>, <&cpubin_efuse>;
		nvmem-cell-names = "speed", "bin";
		opp-shared;

		opp@480000000 {
			opp-hz = /bits/ 64 <480000000>;
			clock-latency-ns = <244144>; /* 8 32k periods */
			opp-microvolt-a0 = <900000>;
			opp-microvolt-a1 = <900000>;
			opp-microvolt-a2 = <900000>;

			opp-microvolt-b0 = <950000>;
			opp-supported-hw = <0x3>;
		};

		opp@720000000 {
			opp-hz = /bits/ 64 <720000000>;
			clock-latency-ns = <244144>; /* 8 32k periods */
			opp-microvolt-a0 = <900000>;
			opp-microvolt-a1 = <900000>;
			opp-microvolt-a2 = <900000>;

			opp-microvolt-b0 = <950000>;
			opp-supported-hw = <0x3>;
		};

		opp@912000000 {
			opp-hz = /bits/ 64 <912000000>;
			clock-latency-ns = <244144>; /* 8 32k periods */
			opp-microvolt-a0 = <950000>;
			opp-microvolt-a1 = <900000>;
			opp-microvolt-a2 = <900000>;

			opp-microvolt-b0 = <950000>;
			opp-supported-hw = <0x3>;
		};

		opp@1008000000 {
			opp-hz = /bits/ 64 <1008000000>;
			clock-latency-ns = <244144>; /* 8 32k periods */
			opp-microvolt-a0 = <1000000>;
			opp-microvolt-a1 = <900000>;
			opp-microvolt-a2 = <900000>;

			opp-microvolt-b0 = <950000>;
			opp-supported-hw = <0x3>;
		};

		opp@1104000000 {
			opp-hz = /bits/ 64 <1104000000>;
			clock-latency-ns = <244144>; /* 8 32k periods */
			opp-microvolt-a0 = <1050000>;
			opp-microvolt-a1 = <950000>;
			opp-microvolt-a2 = <950000>;

			opp-microvolt-b0 = <950000>;
			opp-supported-hw = <0x3>;
		};

		opp@1200000000 {
			opp-hz = /bits/ 64 <1200000000>;
			clock-latency-ns = <244144>; /* 8 32k periods */
			opp-microvolt-a0 = <1100000>;
			opp-microvolt-a1 = <1000000>;
			opp-microvolt-a2 = <1000000>;

			opp-supported-hw = <0x1>;
		};
	};


	dcxo24M: dcxo24M_clk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <24000000>;
		clock-output-names = "dcxo24M";
	};

	rc_16m: rc16m_clk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <16000000>;
		clock-accuracy = <300000000>;
		clock-output-names = "rc-16m";
	};

	ext_32k: ext32k_clk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <32768>;
		clock-output-names = "ext-32k";
	};

	dram: dram {
		compatible = "allwinner,dram";
		clocks = <&ccu CLK_PLL_DDR0>;
		clock-names = "pll_ddr";
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0x00000000 0x40000000 0x00000000 0x20000000>;
	};

	share_space0: share_space@42100000 {
		#address-cells = <1>;
		#size-cells = <1>;
		deice_tpye = "share_space0";
		/* dsp write addr and len */
		/* arm write addr and len */
		/* dsp log addr and len */
		/* reserve */
		reg = <	0x42100000 0x00001000
			0x42101000 0x00001000
			0x42102000 0x0000E000
			0x00000000 0x00000000>;
	};

	gic: interrupt-controller@3020000 {
		compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
		#interrupt-cells = <3>;
		#address-cells = <0>;
		device_type = "gic";
		interrupt-controller;
		reg = <0x0 0x03021000 0 0x1000>, /* GIC Dist */
		      <0x0 0x03022000 0 0x2000>, /* GIC CPU */
		      <0x0 0x03024000 0 0x2000>, /* GIC VCPU Control */
		      <0x0 0x03026000 0 0x2000>; /* GIC VCPU */
		interrupts = <GIC_PPI 9 0xf04>; /* GIC Maintenence IRQ */
	};

	timer_arch {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
		clock-frequency = <24000000>;
		arm,cpu-registers-not-fw-configured;
		interrupt-parent = <&gic>;
		arm,no-tick-in-suspend;
	};

	pmu {
		compatible = "arm,cortex-a7-pmu";
		interrupts = <GIC_SPI 172 4>,
			     <GIC_SPI 173 4>;
	};

	power: power-management@ff000000 {
		compatible = "allwinner,r528-pmu", "syscon", "simple-mfd";
		reg = <0x0 0x07001000 0x0 0x400>;

		pd: power-controller {
			compatible = "allwinner,r528-power-controller";
			clocks = <&r_ccu CLK_R_PPU>;
			clock-names = "ppu";
			resets = <&r_ccu RST_R_PPU>;
			reset-names = "ppu_rst";
			#power-domain-cells = <1>;
			#address-cells = <1>;
			#size-cells = <0>;

			/* These power domains are grouped by VD_SYS */
			pd_ve@R528_PD_VE {
				reg = <R528_PD_VE>;
			};
		};
	};

	mmu_aw: iommu@2010000 {
		compatible = "allwinner,sunxi-iommu";
		reg = <0x0 0x02010000 0x0 0x1000>;
		interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "iommu-irq";
		clocks = <&ccu CLK_BUS_IOMMU>;
		clock-names = "iommu";
		#iommu-cells = <2>;
		status = "okay";
	};

	reg_pio1_8: pio-18 {
		compatible = "regulator-fixed";
		regulator-name = "pio-18";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
	};

	reg_pio3_3: pio-33 {
		compatible = "regulator-fixed";
		regulator-name = "pio-33";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	thermal-zones {
		cpu_thermal_zone: cpu_thermal_zone {
			polling-delay-passive = <500>;
			polling-delay = <1000>;
			thermal-sensors = <&ths 0>;
			sustainable-power = <589>;

			cpu_trips: trips {
				cpu_threshold: trip-point@0 {
					temperature = <70000>;
					type = "passive";
					hysteresis = <0>;
				};
				cpu_target: trip-point@1 {
					temperature = <90000>;
					type = "passive";
					hysteresis = <0>;
				};
				cpu_crit: cpu_crit@0 {
					temperature = <110000>;
					type = "critical";
					hysteresis = <0>;
				};
			};

			cooling-maps {
				map0 {
					trip = <&cpu_target>;
					cooling-device = <&cpu0
					THERMAL_NO_LIMIT
					THERMAL_NO_LIMIT>;
					contribution = <1024>;
				};
			};
		};
	};

	soc: soc@3000000 {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		device_type = "soc";

		sram_ctrl: sram_ctrl@3000000 {
			compatible = "allwinner,sram_ctrl";
			reg = <0x0 0x3000000 0 0x16C>;
			soc_ver {
				offset = <0x24>;
				mask = <0x7>;
				shift = <0>;
				ver_a = <0x18590000>;
				ver_b = <0x18590002>;
				ver_d = <0x18590003>;
			};

			soc_id {
				offset = <0x200>;
				mask = <0x1>;
				shift = <22>;
			};

			soc_bin {
				offset = <0x0>;
				mask = <0x3ff>;
				shift = <0x0>;
			};

		};

		rtc_ccu: rtc_ccu@7090000 {
			compatible = "allwinner,sun8iw20-rtc-ccu";
			device_type = "rtc-ccu";
			reg = <0x0 0x07090000 0x0 0x320>;  /* The same as rtc */
			#clock-cells = <1>;
		};

		ccu: ccu@2001000 {
			compatible = "allwinner,sun8iw20-ccu";
			reg = <0x0 0x02001000 0x0 0x1000>;
			clocks = <&dcxo24M>, <&rtc_ccu CLK_OSC32K>, <&rtc_ccu CLK_IOSC>;
			clock-names = "hosc", "losc", "iosc";
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		r_ccu: r_ccu@7010000 {
			compatible = "allwinner,sun8iw20-r-ccu";
			reg = <0x0 0x07010000 0x0 0x240>;
			clocks = <&dcxo24M>, <&rtc_ccu CLK_OSC32K>, <&rtc_ccu CLK_IOSC>,
				 <&ccu CLK_PLL_PERIPH0>;
			clock-names = "hosc", "losc", "iosc", "pll-periph0";
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		rtc: rtc@7090000 {
			compatible = "allwinner,sun8iw20-rtc";
			device_type = "rtc";
			wakeup-source;
			reg = <0x0 0x07090000 0x0 0x320>;
			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&r_ccu CLK_R_AHB_BUS_RTC>, <&rtc_ccu CLK_RTC_1K>, <&rtc_ccu CLK_RTC_SPI>;
			clock-names = "r-ahb-rtc", "rtc-1k", "rtc-spi";
			resets = <&r_ccu RST_R_AHB_BUS_RTC>;
			gpr_cur_pos = <6>;
		};

		dma:dma-controller@3002000 {
			compatible = "allwinner,sun8iw20-dma";
			reg = <0x0 0x03002000 0x0 0x1000>;
			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
			clock-names = "bus", "mbus";
			dma-channels = <8>;
			dma-requests = <48>;
			resets = <&ccu RST_BUS_DMA>;
			#dma-cells = <1>;
		};

		soc_timer0: timer@2050000 {
			compatible = "allwinner,sun4i-a10-timer";
			device_type = "soc_timer";
			reg = <0x0 0x02050000 0x0 0xA0>;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&dcxo24M>;
		};

		wdt: watchdog@20500A0 {
			compatible = "allwinner,sun6i-a31-wdt";
			reg = <0x0 0x020500A0 0x0 0x20>;  /* In Timers Spec */
			interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;  /* In GIC Spec */
		};

		mbus0: mbus-controller@3102000 {
			compatible = "allwinner,sun8i-mbus";
			reg = <0x0 0x03102000 0x0 0x1000>;  /* In SDRAM Controller Spec: DRAMC Common Register */
			#mbus-cells = <1>;
		};

		pio: pinctrl@2000000 {
			compatible = "allwinner,sun8iw20-pinctrl";
			reg = <0x0 0x02000000 0x0 0x500>;
			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,  /* AW1859_GIC_Spec: GPIOB: 101-32=69 */
				     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
			device_type = "pio";
			clocks = <&ccu CLK_APB0>, <&dcxo24M>, <&rtc_ccu CLK_OSC32K>;
			clock-names = "apb", "hosc", "losc";
			gpio-controller;
			#gpio-cells = <3>;
			interrupt-controller;
			#interrupt-cells = <3>;
			#size-cells = <0>;
			vcc-pf-supply = <&reg_pio1_8>;
			vcc-pfo-supply = <&reg_pio3_3>;

			test_pins_a: test_pins@0 {
				allwinner,pins = "PB0", "PB1";
				allwinner,function = "test";
				allwinner,muxsel = <0x9>;
				allwinner,drive = <1>;
				allwinner,pull = <1>;
			};
			test_pins_b: test_pins@1 {
				pins = "PB0", "PB1";
				function = "io_disabled";
				allwinner,muxsel = <0xF>;
				allwinner,drive = <1>;
				allwinner,pull = <1>;
			};

			csi_mclk0_pins_a: csi_mclk0@0 {
				pins = "PE3";
				function = "csi0";
				drive-strength = <10>;
			};
			csi_mclk0_pins_b: csi_mclk0@1 {
				pins = "PE3";
				function = "gpio_in";
			};
			csi0_pins_a: csi0@0 {
				pins = "PE2", "PE0", "PE1", "PE4", "PE5",
						 "PE6", "PE7", "PE8", "PE9", "PE10", "PE11";
				function = "ncsi0";
				drive-strength = <10>;
			};
			csi0_pins_b: csi0@1 {
				pins = "PE2", "PE0", "PE1", "PE4", "PE5",
						 "PE6", "PE7", "PE8", "PE9", "PE10", "PE11";
				function = "io_disabled";
				drive-strength = <10>;
			};

			lvds0_pins_a: lvds0@0 {
				pins  = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9";
				function = "lvds0";
				drive-strength = <30>;
				bias-disable;
			};

			lvds0_pins_b: lvds0@1 {
				pins  = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9";
				function = "io_disabled";
				drive-strength = <30>;
				bias-disable;
			};

			rgb24_pins_a: rgb24@0 {
				pins = "PB2", "PB3", "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", \
					"PB4", "PB5", "PD6", "PD7", "PD8", "PD9", "PD10", "PD11", \
					"PB6", "PB7", "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", \
					"PD18", "PD19", "PD20", "PD21";
				function = "lcd0";
				drive-strength = <30>;
				bias-disable;
			};

			rgb24_pins_b: rgb24@1 {
				pins = "PB2", "PB3", "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", \
					"PB4", "PB5", "PD6", "PD7", "PD8", "PD9", "PD10", "PD11", \
					"PB6", "PB7", "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", \
					"PD18", "PD19", "PD20", "PD21";
				function = "io_disabled";
				bias-disable;
			};

			rgb18_pins_a: rgb18@0 {
				pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", \
					"PD6", "PD7", "PD8", "PD9", "PD10", "PD11", \
					"PD12", "PD13", "PD14", "PD15", "PD16", "PD17", \
					"PD18", "PD19", "PD20", "PD21";
				function = "lcd0";
				drive-strength = <30>;
				bias-disable;
			};

			rgb18_pins_b: rgb18@1 {
				pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", \
					"PD6", "PD7", "PD8", "PD9", "PD10", "PD11", \
					"PD12", "PD13", "PD14", "PD15", "PD16", "PD17", \
					"PD18", "PD19", "PD20", "PD21";
				function = "io_disabled";
				bias-disable;
			};

			dsi2lane_pins_a: dsi2lane@0 {
				pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5";
				function = "dsi";
				drive-strength = <30>;
				bias-disable;
			};

			dsi2lane_pins_b: dsi2lane@1 {
				pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5";
				function = "io_disabled";
				bias-disable;
			};

			dsi4lane_pins_a: dsi4lane@0 {
				pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9";
				function = "dsi";
				drive-strength = <30>;
				bias-disable;
			};

			dsi4lane_pins_b: dsi4lane@1 {
				pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9";
				function = "io_disabled";
				bias-disable;
			};

		};

		pinctrl_test: pinctrl_test@0 {
			reg = <0x0 0x0 0x0 0x0>;
			compatible = "allwinner,sunxi-pinctrl-test";
			device_type = "pinctrl-test";
			/* For pin state selecting test */
			pinctrl-0 = <&test_pins_a>;
			pinctrl-1 = <&test_pins_b>;
			pinctrl-names = "default", "sleep";
			/* For pin basic_function/irq test */
			test-gpios = <&pio PB 0 GPIO_ACTIVE_LOW>;
			interrupt-parent = <&pio>;
			interrupts = <PB 1 IRQ_TYPE_LEVEL_HIGH>;
		};

		uart0: uart@2500000 {
			compatible = "allwinner,sun8i-uart";
			device_type = "uart0";
			reg = <0x0 0x02500000 0x0 0x400>;
			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
			sunxi,uart-fifosize = <64>;
			clocks = <&ccu CLK_BUS_UART0>;
			clock-names = "uart0";
			resets = <&ccu RST_BUS_UART0>;
			uart0_port = <0>;
			uart0_type = <2>;
			status = "disabled";
		};

		uart1: uart@2500400 {
			compatible = "allwinner,sun8i-uart";
			device_type = "uart1";
			reg = <0x0 0x02500400 0x0 0x400>;
			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
			sunxi,uart-fifosize = <256>;
			clocks = <&ccu CLK_BUS_UART1>;
			clock-names = "uart1";
			resets = <&ccu RST_BUS_UART1>;
			uart1_port = <1>;
			uart1_type = <4>;
			status = "okay";
		};

		uart2: uart@2500800 {
			compatible = "allwinner,sun8i-uart";
			device_type = "uart2";
			reg = <0x0 0x02500800 0x0 0x400>;
			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
			sunxi,uart-fifosize = <256>;
			clocks = <&ccu CLK_BUS_UART2>;
			clock-names = "uart2";
			resets = <&ccu RST_BUS_UART2>;
			uart2_port = <2>;
			uart2_type = <4>;
			status = "disabled";
		};

		uart3: uart@2500c00 {
			compatible = "allwinner,sun8i-uart";
			device_type = "uart3";
			reg = <0x0 0x02500c00 0x0 0x400>;
			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
			sunxi,uart-fifosize = <256>;
			clocks = <&ccu CLK_BUS_UART3>;
			clock-names = "uart3";
			resets = <&ccu RST_BUS_UART3>;
			uart3_port = <3>;
			uart3_type = <4>;
			status = "disabled";
		};

		uart4: uart@2501000 {
			compatible = "allwinner,sun8i-uart";
			device_type = "uart4";
			reg = <0x0 0x02501000 0x0 0x400>;
			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
			sunxi,uart-fifosize = <256>;
			clocks = <&ccu CLK_BUS_UART4>;
			clock-names = "uart4";
			resets = <&ccu RST_BUS_UART4>;
			uart4_port = <4>;
			uart4_type = <2>;
			status = "disabled";
		};

		uart5: uart@2501400 {
			compatible = "allwinner,sun8i-uart";
			device_type = "uart5";
			reg = <0x0 0x02501400 0x0 0x400>;
			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
			sunxi,uart-fifosize = <256>;
			clocks = <&ccu CLK_BUS_UART5>;
			clock-names = "uart5";
			resets = <&ccu RST_BUS_UART5>;
			uart5_port = <5>;
			uart5_type = <2>;
			status = "disabled";
		};
		cryptoengine: ce@03040000 {
			compatible = "allwinner,sunxi-ce";
			device_name = "ce";
			reg = <0x0 0x03040000 0x0 0xa0>, /* non-secure space */
			      <0x0 0x03040800 0x0 0xa0>; /* secure space */
			interrupts = <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>, /*non-secure*/
				   <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>; /* secure*/
			clock-frequency = <400000000>; /* 400MHz */
			clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>, <&ccu CLK_MBUS_CE>,
					<&ccu CLK_PLL_PERIPH0_2X>;
			clock-names = "bus_ce", "ce_clk", "mbus_ce", "pll_periph0_2x";
			resets = <&ccu RST_BUS_CE>;
			status = "okay";
		};

		gmac0: eth@4500000 {
			compatible = "allwinner,sunxi-gmac";
			reg = <0x0 0x04500000 0x0 0x10000>,
			      <0x0 0x03000030 0x0 0x4>;
			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "gmacirq";
			clocks = <&ccu CLK_BUS_EMAC0>, <&ccu CLK_EMAC0_25M>;
			clock-names = "gmac", "ephy";
			resets = <&ccu RST_BUS_EMAC0>;
			device_type = "gmac0";
			gmac-power0;
			gmac-power1;
			gmac-power2;
			status = "disabled";
		};

		sdc2: sdmmc@4022000 {
			compatible = "allwinner,sunxi-mmc-v4p6x";
			device_type = "sdc2";
			reg = <0x0 0x04022000 0x0 0x1000>;
			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&dcxo24M>,
				 <&ccu CLK_PLL_PERIPH0_2X>,
				 <&ccu CLK_MMC2>,
				 <&ccu CLK_BUS_MMC2>;
			clock-names = "osc24m","pll_periph","mmc","ahb";
			resets = <&ccu RST_BUS_MMC2>;
			reset-names = "rst";
			pinctrl-names = "default","sleep";
			pinctrl-0 = <&sdc2_pins_a>;
			pinctrl-1 = <&sdc2_pins_b>;
			bus-width = <4>;
			req-page-count = <2>;
			cap-mmc-highspeed;
			cap-cmd23;
			mmc-cache-ctrl;
			non-removable;
			/*max-frequency = <200000000>;*/
			max-frequency = <50000000>;
			cap-erase;
			mmc-high-capacity-erase-size;
			no-sdio;
			no-sd;
			/*-- speed mode --*/
			/*sm0: DS26_SDR12*/
			/*sm1: HSSDR52_SDR25*/
			/*sm2: HSDDR52_DDR50*/
			/*sm3: HS200_SDR104*/
			/*sm4: HS400*/
			/*-- frequency point --*/
			/*f0: CLK_400K*/
			/*f1: CLK_25M*/
			/*f2: CLK_50M*/
			/*f3: CLK_100M*/
			/*f4: CLK_150M*/
			/*f5: CLK_200M*/

			sdc_tm4_sm0_freq0 = <0>;
			sdc_tm4_sm0_freq1 = <0>;
			sdc_tm4_sm1_freq0 = <0x00000000>;
			sdc_tm4_sm1_freq1 = <0>;
			sdc_tm4_sm2_freq0 = <0x00000000>;
			sdc_tm4_sm2_freq1 = <0>;
			sdc_tm4_sm3_freq0 = <0x05000000>;
			sdc_tm4_sm3_freq1 = <0x00000005>;
			sdc_tm4_sm4_freq0 = <0x00050000>;
			sdc_tm4_sm4_freq1 = <0x00000004>;
			sdc_tm4_sm4_freq0_cmd = <0>;
			sdc_tm4_sm4_freq1_cmd = <0>;

			/*vmmc-supply = <&reg_3p3v>;*/
			/*vqmc-supply = <&reg_3p3v>;*/
			/*vdmc-supply = <&reg_3p3v>;*/
			/*vmmc = "vcc-card";*/
			/*vqmc = "";*/
			/*vdmc = "";*/
			/*sunxi-power-save-mode;*/
		};

		sdc0: sdmmc@4020000 {
			compatible = "allwinner,sunxi-mmc-v5p3x";
			device_type = "sdc0";
			reg = <0x0 0x04020000 0x0 0x1000>;
			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&dcxo24M>,
				 <&ccu CLK_PLL_PERIPH0_2X>,
				 <&ccu CLK_MMC0>,
				 <&ccu CLK_BUS_MMC0>;
			clock-names = "osc24m","pll_periph","mmc","ahb";
			resets = <&ccu RST_BUS_MMC0>;
			reset-names = "rst";
			pinctrl-names = "default","mmc_1v8","sleep","uart_jtag";
			pinctrl-0 = <&sdc0_pins_a>;
			pinctrl-1 = <&sdc0_pins_b>;
			pinctrl-2 = <&sdc0_pins_c>;
			pinctrl-3 = <&sdc0_pins_d &sdc0_pins_e>;
			max-frequency = <50000000>;
			bus-width = <4>;
			req-page-count = <2>;
			/*non-removable;*/
			/*broken-cd;*/
			/*cd-inverted*/
			/*cd-gpios = <&pio PF 6 GPIO_ACTIVE_LOW>;*/
			/* vmmc-supply = <&reg_3p3v>;*/
			/* vqmc-supply = <&reg_3p3v>;*/
			/* vdmc-supply = <&reg_3p3v>;*/
			/*vmmc = "vcc-card";*/
			/*vqmc = "";*/
			/*vdmc = "";*/
			cap-sd-highspeed;
			cap-wait-while-busy;
			no-sdio;
			no-mmc;
			/*sd-uhs-sdr50;*/
			/*sd-uhs-ddr50;*/
			/*cap-sdio-irq;*/
			/*keep-power-in-suspend;*/
			/*ignore-pm-notify;*/
			/*sunxi-power-save-mode;*/
			/*sunxi-dly-400k = <1 0 0 0>; */
			/*sunxi-dly-26M  = <1 0 0 0>;*/
			/*sunxi-dly-52M  = <1 0 0 0>;*/
			/*sunxi-dly-52M-ddr4  = <1 0 0 0>;*/
			/*sunxi-dly-52M-ddr8  = <1 0 0 0>;*/
			/*sunxi-dly-104M  = <1 0 0 0>;*/
			/*sunxi-dly-208M  = <1 0 0 0>;*/
			/*sunxi-dly-104M-ddr  = <1 0 0 0>;*/
			/*sunxi-dly-208M-ddr  = <1 0 0 0>;*/
		};

		sdc1: sdmmc@4021000 {
			compatible = "allwinner,sunxi-mmc-v5p3x";
			device_type = "sdc1";
			reg = <0x0 0x04021000 0x0 0x1000>;
			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&dcxo24M>,
				 <&ccu CLK_PLL_PERIPH0_2X>,
				 <&ccu CLK_MMC1>,
				 <&ccu CLK_BUS_MMC1>;
			clock-names = "osc24m","pll_periph","mmc","ahb";
			resets = <&ccu RST_BUS_MMC1>;
			reset-names = "rst";
			pinctrl-names = "default","sleep";
			pinctrl-0 = <&sdc1_pins_a>;
			pinctrl-1 = <&sdc1_pins_b>;
			max-frequency = <50000000>;
			bus-width = <4>;
			/*broken-cd;*/
			/*cd-inverted*/
			/*cd-gpios = <&pio PG 6 6 1 2 0>;*/
			/* vmmc-supply = <&reg_3p3v>;*/
			/* vqmc-supply = <&reg_3p3v>;*/
			/* vdmc-supply = <&reg_3p3v>;*/
			/*vmmc = "vcc-card";*/
			/*vqmc = "";*/
			/*vdmc = "";*/
			cap-sd-highspeed;
			no-mmc;
			/*sd-uhs-sdr50;*/
			/*sd-uhs-ddr50;*/
			/*sd-uhs-sdr104;*/
			/*cap-sdio-irq;*/
			keep-power-in-suspend;
			/*ignore-pm-notify;*/
			/*sunxi-power-save-mode;*/
			/*sunxi-dly-400k = <1 0 0 0 0>; */
			/*sunxi-dly-26M  = <1 0 0 0 0>;*/
			/*sunxi-dly-52M  = <1 0 0 0 0>;*/
			sunxi-dly-52M-ddr4  = <1 0 0 0 2>;
			/*sunxi-dly-52M-ddr8  = <1 0 0 0 0>;*/
			sunxi-dly-104M  = <1 0 0 0 1>;
			/*sunxi-dly-208M  = <1 1 0 0 0>;*/
			sunxi-dly-208M  = <1 0 0 0 1>;
			/*sunxi-dly-104M-ddr  = <1 0 0 0 0>;*/
			/*sunxi-dly-208M-ddr  = <1 0 0 0 0>;*/

			status = "okay";
		};

		tpadc: tpadc@2009c00 {
			compatible = "allwinner,tp_key";
			reg = <0x0 0x02009c00 0x0 0x400>;
			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_TPADC>, <&ccu CLK_BUS_TPADC>;
			clock-names = "mod", "bus";
			clock-frequency = <1000000>;
			resets = <&ccu RST_BUS_TPADC>;
			status = "disabled";
		};

		rtp:rtp@2009c00 {
			compatible = "allwinner,sun8i-ts";
			reg = <0x0 0x02009c00 0x0 0x400>;
			clocks = <&ccu CLK_TPADC>, <&ccu CLK_BUS_TPADC>;
			clock-names = "mod", "bus";
			clock-frequency = <1000000>;
			resets = <&ccu RST_BUS_TPADC>;
			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
		};

		spi0: spi@4025000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sun8i-spi";
			device_type = "spi0";
			reg = <0x0 0x04025000 0x0 0x1000>;
			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_PLL_PERIPH0>, <&ccu CLK_SPI0>, <&ccu CLK_BUS_SPI0>;
			clock-names = "pll", "mod", "bus";
			resets = <&ccu RST_BUS_SPI0>;
			clock-frequency = <100000000>;
			spi0_cs_number = <1>;
			spi0_cs_bitmap = <1>;
			dmas = <&dma 22>, <&dma 22>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		spi1: spi@4026000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sun8i-spi";
			device_type = "spi1";
			reg = <0x0 0x04026000 0x0 0x1000>;
			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_PLL_PERIPH0>, <&ccu CLK_SPI1>, <&ccu CLK_BUS_SPI1>;
			clock-names = "pll", "mod", "bus";
			resets = <&ccu RST_BUS_SPI1>;
			clock-frequency = <100000000>;
			spi1_cs_number = <1>;
			spi1_cs_bitmap = <1>;
			dmas = <&dma 23>, <&dma 23>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		ve: ve@1c0e000 {
			    compatible = "allwinner,sunxi-cedar-ve";
			    reg = <0x0 0x01c0e000 0x0 0x1000>,
				<0x0 0x03000000 0x0 0x10>,
				<0x0 0x03001000 0x0 0x1000>;
			    interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
			    clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, <&ccu CLK_MBUS_VE>;
			    clock-names = "bus_ve", "ve", "mbus_ve";
			    resets = <&ccu RST_BUS_VE>;
			    power-domains = <&pd R528_PD_VE>;
			    iommus = <&mmu_aw 0 1>;
			    status = "okay";
		};

		twi0: twi@2502000{
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sun8i-twi";
			device_type = "twi0";
			reg = <0x0 0x02502000 0x0 0x400>;
			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_I2C0>;
			resets = <&ccu RST_BUS_I2C0>;
			clock-names = "bus";
			clock-frequency = <400000>;
			status = "disabled";
		};

		twi1: twi@2502400{
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sun8i-twi";
			device_type = "twi1";
			reg = <0x0 0x02502400 0x0 0x400>;
			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_I2C1>;
			resets = <&ccu RST_BUS_I2C1>;
			clock-names = "bus";
			clock-frequency = <200000>;
			status = "disabled";
		};

		twi2: twi@2502800{
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sun8i-twi";
			device_type = "twi2";
			reg = <0x0 0x02502800 0x0 0x400>;
			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_I2C2>;
			resets = <&ccu RST_BUS_I2C2>;
			clock-names = "bus";
			clock-frequency = <100000>;
			status = "disabled";
		};

		twi3: twi@2502c00{
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sun8i-twi";
			device_type = "twi3";
			reg = <0x0 0x02502c00 0x0 0x400>;
			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_I2C3>;
			resets = <&ccu RST_BUS_I2C3>;
			clock-names = "bus";
			clock-frequency = <100000>;
			status = "disabled";
		};

		ledc: ledc@2008000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sunxi-leds";
			reg = <0x0 0x02008000 0x0 0x400>;
			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "ledcirq";
			clocks = <&ccu CLK_LEDC>, <&ccu CLK_BUS_LEDC>;
			clock-names = "clk_ledc", "clk_cpuapb";
			dmas = <&dma 42>, <&dma 42>;
			dma-names = "rx", "tx";
			resets = <&ccu RST_BUS_LEDC>;
			reset-names = "ledc_reset";
			status = "disable";
		};

		pwm: pwm@2000c00 {
			#pwm-cells = <0x3>;
			compatible = "allwinner,sunxi-pwm";
			reg = <0x0 0x02000c00 0x0 0x400>;
			clocks = <&ccu CLK_BUS_PWM>;
			resets = <&ccu RST_BUS_PWM>;
			pwm-number = <8>;
			pwm-base = <0x0>;
			sunxi-pwms = <&pwm0>, <&pwm1>, <&pwm2>, <&pwm3>, <&pwm4>,
				<&pwm5>, <&pwm6>, <&pwm7>;
		};

		pwm0: pwm0@2000c10 {
			compatible = "allwinner,sunxi-pwm0";
			pinctrl-names = "active", "sleep";
			reg = <0x0 0x02000c10 0x0 0x4>;
			reg_base = <0x02000c00>;
		};

		pwm1: pwm1@2000c11 {
			compatible = "allwinner,sunxi-pwm1";
			pinctrl-names = "active", "sleep";
			reg = <0x0 0x02000c11 0x0 0x4>;
			reg_base = <0x02000c00>;
		};

		pwm2: pwm2@2000c12 {
			compatible = "allwinner,sunxi-pwm2";
			pinctrl-names = "active", "sleep";
			reg = <0x0 0x02000c12 0x0 0x4>;
			reg_base = <0x02000c00>;
		};

		pwm3: pwm3@2000c13 {
			compatible = "allwinner,sunxi-pwm3";
			pinctrl-names = "active", "sleep";
			reg = <0x0 0x02000c13 0x0 0x4>;
			reg_base = <0x02000c00>;
		};

		pwm4: pwm4@2000c14 {
			compatible = "allwinner,sunxi-pwm4";
			pinctrl-names = "active", "sleep";
			reg = <0x0 0x02000c14 0x0 0x4>;
			reg_base = <0x02000c00>;
		};

		pwm5: pwm5@2000c15 {
			compatible = "allwinner,sunxi-pwm5";
			pinctrl-names = "active", "sleep";
			reg = <0x0 0x02000c15 0x0 0x4>;
			reg_base = <0x02000c00>;
		};

		pwm6: pwm6@2000c16 {
			compatible = "allwinner,sunxi-pwm6";
			pinctrl-names = "active", "sleep";
			reg = <0x0 0x02000c16 0x0 0x4>;
			reg_base = <0x02000c00>;
		};

		pwm7: pwm7@2000c17 {
			compatible = "allwinner,sunxi-pwm7";
			pinctrl-names = "active", "sleep";
			reg = <0x0 0x02000c17 0x0 0x4>;
			reg_base = <0x02000c00>;
		};

		lcd_fb0: lcd_fb0@0 {
			compatible = "allwinner,sunxi-lcd_fb0";
			pinctrl-names = "active","sleep";

			status = "okay";
		};

		keyboard0: keyboard@2009800 {
			compatible = "allwinner,keyboard_1350mv";
			reg = <0x0 0x02009800 0x0 0x400>;
			interrupts = <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>;
			clocks = <&ccu CLK_BUS_LRADC>;
			clock-names = "mclk";
			resets = <&ccu RST_BUS_LRADC>;
			key_cnt = <5>;
			key0 = <210 115>;
			key1 = <410 114>;
			key2 = <590 139>;
			key3 = <750 28>;
			key4 = <880 172>;
			wakeup-source;
			status = "okay";
		};

		sid@3006000 {
			compatible = "allwinner,sun8iw20p1-sid", "allwinner,sunxi-sid";
			reg = <0x0 0x03006000 0 0x1000>;
			#address-cells = <1>;
			#size-cells = <1>;

			secure_status {
				reg = <0x0 0>;
				offset = <0xa0>;
				size = <0x4>;
			};

			chipid {
				reg = <0x0 0>;
				offset = <0x200>;
				size = <0x10>;
			};

			rotpk {
				reg = <0x0 0>;
				offset = <0x140>;
				size = <0x4>;
			};

			speedbin_efuse: speedbin@00 {
				reg = <0x00 4>;
			};

			cpubin_efuse: cpubin@28 {
				reg = <0x28 4>;
			};

			ths_calib: calib@14 {
				reg = <0x14 8>;
			};
		};

		gpadc: gpadc@2009000 {
			compatible = "allwinner,sunxi-gpadc";
			reg = <0x0 0x02009000 0x0 0x400>;
			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_GPADC>;
			clock-names = "bus";
			resets = <&ccu RST_BUS_GPADC>;
			status = "okay";
		};

		vind0: vind@5800800 {
			compatible = "allwinner,sunxi-vin-media", "simple-bus";
			#address-cells = <2>;
			#size-cells = <2>;
			ranges;
			device_id = <0>;
			csi_top = <336000000>;
			csi_isp = <327000000>;
			reg = <0x0 0x05800800 0x0 0x200>,
				<0x0 0x05800000 0x0 0x800>;
			clocks = <&ccu CLK_CSI_TOP>, <&ccu CLK_PLL_VIDEO1_2X>,
				<&ccu CLK_CSI0_MCLK>, <&dcxo24M>, <&ccu CLK_PLL_VIDEO1>,
				<&ccu CLK_BUS_CSI>, <&ccu CLK_MBUS_CSI>;
			clock-names = "csi_top", "csi_top_src",
					"csi_mclk0", "csi_mclk0_24m", "csi_mclk0_pll",
					"csi_bus", "csi_mbus";
			resets = <&ccu RST_BUS_CSI>;
			reset-names = "csi_ret";
			pinctrl-names = "mclk0-default", "mclk0-sleep";
			pinctrl-0 = <&csi_mclk0_pins_a>;
			pinctrl-1 = <&csi_mclk0_pins_b>;
			status = "okay";

			csi0: csi@5801000{
				compatible = "allwinner,sunxi-csi";
				reg = <0x0 0x05801000 0x0 0x1000>;
				interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
				pinctrl-names = "default","sleep";
				pinctrl-0 = <&csi0_pins_a>;
				pinctrl-1 = <&csi0_pins_b>;
				device_id = <0>;
				iommus = <&mmu_aw 1 1>;
				status = "okay";
			};
			isp0: isp@5809410 {
				compatible = "allwinner,sunxi-isp";
				reg = <0x0 0x05809410 0x0 0x10>;
				device_id = <0xfe>;

				status = "okay";
			};
			isp1: isp@5809420 {
				compatible = "allwinner,sunxi-isp";
				reg = <0x0 0x05809420 0x0 0x10>;
				device_id = <0xff>;
				status = "okay";
			};
			scaler0: scaler@5809430 {
				compatible = "allwinner,sunxi-scaler";
				reg = <0x0 0x05809430 0x0 0x10>;
				device_id = <0xfe>;
				status = "okay";
			};
			scaler1: scaler@5809440 {
				compatible = "allwinner,sunxi-scaler";
				reg = <0x0 0x05809440 0x0 0x10>;
				device_id = <0xff>;
				status = "okay";
			};
			actuator0: actuator@5809450 {
				compatible = "allwinner,sunxi-actuator";
				device_type = "actuator0";
				reg = <0x0 0x05809450 0x0 0x10>;
				actuator0_name = "ad5820_act";
				actuator0_slave = <0x18>;
				actuator0_af_pwdn = <>;
				actuator0_afvdd = "afvcc-csi";
				actuator0_afvdd_vol = <2800000>;
				status = "disabled";
			};
			flash0: flash@5809460 {
				device_type = "flash0";
				compatible = "allwinner,sunxi-flash";
				reg = <0x0 0x05809460 0x0 0x10>;
				flash0_type = <2>;
				flash0_en = <>;
				flash0_mode = <>;
				flash0_flvdd = "";
				flash0_flvdd_vol = <>;
				device_id = <0>;
				status = "disabled";
			};
			sensor0: sensor@5809470 {
				reg = <0x0 0x05809470 0x0 0x10>;
				device_type = "sensor0";
				compatible = "allwinner,sunxi-sensor";
				sensor0_mname = "ov5640";
				sensor0_twi_cci_id = <2>;
				sensor0_twi_addr = <0x78>;
				sensor0_mclk_id = <0>;
				sensor0_pos = "rear";
				sensor0_isp_used = <0>;
				sensor0_fmt = <0>;
				sensor0_stby_mode = <0>;
				sensor0_vflip = <0>;
				sensor0_hflip = <0>;
				sensor0_iovdd-supply = <>;
				sensor0_iovdd_vol = <>;
				sensor0_avdd-supply = <>;
				sensor0_avdd_vol = <>;
				sensor0_dvdd-supply = <>;
				sensor0_dvdd_vol = <>;
				sensor0_power_en = <>;
				sensor0_reset = <&pio PE 9 GPIO_ACTIVE_LOW>;
				sensor0_pwdn = <&pio PE 8 GPIO_ACTIVE_LOW>;
				sensor0_sm_vs = <>;
				flash_handle = <&flash0>;
				act_handle = <&actuator0>;
				device_id = <0>;
				status	= "okay";
			};
			sensor1: sensor@5809480 {
				reg = <0x0 0x05809480 0x0 0x10>;
				device_type = "sensor1";
				compatible = "allwinner,sunxi-sensor";
				sensor1_mname = "ov5647";
				sensor1_twi_cci_id = <3>;
				sensor1_twi_addr = <0x6c>;
				sensor1_mclk_id = <1>;
				sensor1_pos = "front";
				sensor1_isp_used = <0>;
				sensor1_fmt = <0>;
				sensor1_stby_mode = <0>;
				sensor1_vflip = <0>;
				sensor1_hflip = <0>;
				sensor1_iovdd-supply = <>;
				sensor1_iovdd_vol = <>;
				sensor1_avdd-supply = <>;
				sensor1_avdd_vol = <>;
				sensor1_dvdd-supply = <>;
				sensor1_dvdd_vol = <>;
				sensor1_power_en = <>;
				sensor1_reset = <&pio PE 7 GPIO_ACTIVE_LOW>;
				sensor1_pwdn = <&pio PE 6 GPIO_ACTIVE_LOW>;
				sensor1_sm_vs = <>;
				flash_handle = <>;
				act_handle = <>;
				device_id = <1>;
				status	= "okay";
			};
			vinc0: vinc@5809000 {
				compatible = "allwinner,sunxi-vin-core";
				device_type = "vinc0";
				reg = <0x0 0x05809000 0x0 0x200>;
				interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
				vinc0_csi_sel = <0>;
				vinc0_mipi_sel = <0xff>;
				vinc0_isp_sel = <0>;
				vinc0_tdm_rx_sel = <0xff>;
				vinc0_rear_sensor_sel = <0>;
				vinc0_front_sensor_sel = <0>;
				vinc0_sensor_list = <0>;
				device_id = <0>;
				iommus = <&mmu_aw 1 1>;
				status = "okay";
			};
			vinc1: vinc@5809200 {
				device_type = "vinc1";
				compatible = "allwinner,sunxi-vin-core";
				reg = <0x0 0x05809200 0x0 0x200>;
				interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
				vinc1_csi_sel = <0>;
				vinc1_mipi_sel = <0xff>;
				vinc1_isp_sel = <1>;
				vinc1_tdm_rx_sel = <0xff>;
				vinc1_rear_sensor_sel = <0>;
				vinc1_front_sensor_sel = <0>;
				vinc1_sensor_list = <0>;
				device_id = <1>;
				iommus = <&mmu_aw 1 1>;
				status = "okay";
			};

		};
		s_cir0: s_cir@7040000 {
			compatible = "allwinner,s_cir";
			reg = <0x0 0x07040000 0x0 0x400>;
			interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&r_ccu CLK_R_APB0_BUS_IRRX>, <&dcxo24M>, <&r_ccu CLK_R_APB0_IRRX>;
			clock-names = "bus", "pclk", "mclk";
			resets = <&r_ccu RST_R_APB0_BUS_IRRX>;
			status = "disabled";
		};

		ir1: ir@2003000 {
			compatible = "allwinner,irtx";
			reg = <0x0 0x02003000 0x0 0x400>;
			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_IR_TX>, <&dcxo24M>, <&ccu CLK_IR_TX>;
			clock-names = "bus", "pclk", "mclk";
			resets = <&ccu RST_BUS_IR_TX>;
			status = "disabled";
		};

		di: deinterlace@5400000 {
			compatible = "allwinner,sunxi-deinterlace";
			reg = <0x0 0x05400000 0x0 0x0000ffff>;
			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_DI>,
				 <&ccu CLK_BUS_DI>,
				 <&ccu CLK_PLL_PERIPH0_2X>;
			clock-names = "clk_di",
				      "pll_periph",
				      "clk_bus_di";
			resets = <&ccu RST_BUS_DI>;
			reset-names = "rst_bus_di";

			assigned-clocks = <&ccu CLK_DI>;
			assigned-clock-parents = <&ccu CLK_PLL_PERIPH0_2X>;
			assigned-clock-rates = <300000000>;

			iommus = <&mmu_aw 4 1>;
			status = "okay";
		};

		g2d: g2d@5410000 {
			compatible = "allwinner,sunxi-g2d";
			reg = <0x0 0x05410000 0x0 0x3ffff>;
			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_G2D>, <&ccu CLK_G2D>, <&ccu CLK_MBUS_G2D>;
			clock-names = "bus", "g2d", "mbus_g2d";
			resets = <&ccu RST_BUS_G2D>;
			iommus = <&mmu_aw 3 1>;
			status = "okay";
		};

		disp: disp@5000000 {
			compatible = "allwinner,sunxi-disp";
			reg = <0x0 0x05000000 0x0 0x3fffff>,	/* de0 */
			      <0x0 0x05460000 0x0 0xfff>,	/*display_if_top*/
			      <0x0 0x05461000 0x0 0xfff>,	/* tcon-lcd0 */
			      <0x0 0x05470000 0x0 0xfff>,	/* tcon-tv */
			      <0x0 0x05450000 0x0 0x1fff>;	/* dsi0*/
			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,/*tcon-lcd0*/
				     <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,/*tcon-tv */
				     <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;/*dsi*/
			clocks = <&ccu CLK_DE0>,
				 <&ccu CLK_DE0>,
				 <&ccu CLK_BUS_DE0>,
				 <&ccu CLK_BUS_DE0>,
				 <&ccu CLK_BUS_DPSS_TOP0>,
				 <&ccu CLK_BUS_DPSS_TOP0>,
				 <&ccu CLK_MIPI_DSI>,
				 <&ccu CLK_BUS_MIPI_DSI>,
				 <&ccu CLK_TCON_LCD0>,
				 <&ccu CLK_TCON_TV>,
				 <&ccu CLK_BUS_TCON_LCD0>,
				 <&ccu CLK_BUS_TCON_TV>,
				 <&ccu CLK_MIPI_DSI>,
				 <&ccu CLK_BUS_MIPI_DSI>;
			clock-names = "clk_de0",
					"clk_de1",
					"clk_bus_de0",
					"clk_bus_de1",
					"clk_bus_dpss_top0",
					"clk_bus_dpss_top1",
					"clk_mipi_dsi0",
					"clk_bus_mipi_dsi0",
					"clk_tcon0",
					"clk_tcon1",/*tcon-tv actually*/
					"clk_bus_tcon0",
					"clk_bus_tcon1",/*tcon-tv actually*/
					"clk_mipi_dsi0",
					"clk_bus_mipi_dsi0";
			resets = <&ccu RST_BUS_DE0>,
				 <&ccu RST_BUS_DE0>,
				 <&ccu RST_BUS_DPSS_TOP0>,
				 <&ccu RST_BUS_DPSS_TOP0>,
				 <&ccu RST_BUS_MIPI_DSI>,
				 <&ccu RST_BUS_TCON_LCD0>,
				 <&ccu RST_BUS_TCON_TV>,
				 <&ccu RST_BUS_LVDS0>;
			reset-names = "rst_bus_de0",
					"rst_bus_de1",
					"rst_bus_dpss_top0",
					"rst_bus_dpss_top1",
					"rst_bus_mipi_dsi0",
					"rst_bus_tcon0",
					"rst_bus_tcon1",
					"rst_bus_lvds0";

			assigned-clocks = <&ccu CLK_DE0>,
			<&ccu CLK_MIPI_DSI>,
			<&ccu CLK_TCON_LCD0>,
			<&ccu CLK_TCON_TV>;
			assigned-clock-parents = <&ccu CLK_PLL_PERIPH0_2X>,
			<&ccu CLK_PLL_PERIPH0>,
			<&ccu CLK_PLL_VIDEO0_4X>,
			<&ccu CLK_PLL_VIDEO1_4X>;
			assigned-clock-rates = <300000000>,
			<150000000>,
			<0>,
			<0>;

			boot_disp = <0>;
			boot_disp1 = <0>;
			boot_disp2 = <0>;
			fb_base = <0>;
			iommus = <&mmu_aw 2 0>;
			status = "okay";
		};

		lcd0: lcd0@5461000 {
			compatible = "allwinner,sunxi-lcd0";
			reg = <0x0 0x05461000 0x0 0xfff>;
			pinctrl-names = "active","sleep";
			status = "okay";
		};

		tv0: tv0@5600000 {
			compatible = "allwinner,sunxi-tv";
			reg = <0x0 0x05600000 0x0 0x3fff>,
				<0x0 0x05604000 0x0 0x3fff>;
			clocks = <&ccu CLK_BUS_TVE_TOP>,
				 <&ccu CLK_TVE>,
				 <&ccu CLK_BUS_TVE>;
			clock-names = "clk_bus_tve_top",
				      "clk_tve",
				      "clk_bus_tve";
			resets = <&ccu RST_BUS_TVE_TOP>,
				 <&ccu RST_BUS_TVE>;
			reset-names = "rst_bus_tve_top", "rst_bus_tve";

			device_type = "tv0";
			pinctrl-names = "active","sleep";
			status = "okay";
		};

		hwspinlock: hwspinlock@0x3005000 {
			compatible = "allwinner,sunxi-hwspinlock";
			reg = <0x0 0x3005000 0x0 0x1000>;
			#hwlock-cells = <1>;
			clocks = <&ccu CLK_BUS_SPINLOCK>;
			clock-names = "clk_hwspinlock_bus";
			resets = <&ccu RST_BUS_SPINLOCK>;
			reset-names = "rst";
			num-locks = <32>;
			status = "disabled";
		};
		/* old msgbox in dts
		msgbox: msgbox@3003000 {
			compatible = "sunxi,msgbox-amp";
			reg = <0x0 0x03003000 0x0 0x1000>,
			      <0x0 0x01701000 0x0 0x1000>,
			      <0x0 0x0601f000 0x0 0x1000>;
			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_MSGBOX0>;
			rpmsg_id = "sunxi,dsp-msgbox","sunxi,dsp-power-msgbox";
			resets = <&ccu RST_BUS_MSGBOX0>;
			reset-names = "rst";
			msgbox_amp_counts = <3>;
			msgbox_amp_local = <0>;
			rpmsg_amp_remote-0 = <1>;
			rpmsg_read_channel-0 = <1>;
			rpmsg_write_channel-0 = <1>;
			rpmsg_amp_remote-1 = <1>;
			rpmsg_read_channel-1 = <0>;
			rpmsg_write_channel-1 = <0>;
		}; */
		msgbox: msgbox@3003000 {
			compatible = "allwinner,sun8iw20-msgbox";
			#mbox-cells = <1>;
			reg = <0x0 0x03003000 0x0 0x1000>,
			      <0x0 0x01701000 0x0 0x1000>,
			      <0x0 0x0601f000 0x0 0x1000>;
			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_MSGBOX0>;
			resets = <&ccu RST_BUS_MSGBOX0>;
			reset-names = "rst";
			local_id = <0>;
			status = "okay";
		};

		hdmi: hdmi@5500000 {
			compatible = "allwinner,sunxi-hdmi";
			reg = <0x0 0x05500000 0x0 0xfffff>;
			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_HDMI>,
				<&ccu CLK_HDMI_24M>,
				<&ccu CLK_HDMI_CEC>,
				<&ccu CLK_TCON_TV>;
			clock-names = "clk_bus_hdmi",
					"clk_ddc",
					"clk_cec",
					"clk_tcon_tv";
			resets = <&ccu RST_BUS_HDMI_SUB>,
				<&ccu RST_BUS_HDMI_MAIN>;
			reset-names = "rst_bus_sub",
				      "rst_bus_main";
			assigned-clocks = <&ccu CLK_HDMI_CEC>;
			assigned-clock-parents = <&ccu CLK_HDMI_CEC_32K>;
			assigned-clock-rates = <0>;
			status = "okay";
		};
		usbc0:usbc0@0 {
			device_type = "usbc0";
			compatible = "allwinner,sunxi-otg-manager";
			usb_port_type = <2>;
			usb_detect_type = <1>;
			usb_id_gpio;
			usb_det_vbus_gpio;
			usb_regulator_io = "nocare";
			usb_wakeup_suspend = <0>;
			usb_luns = <3>;
			usb_serial_unique = <0>;
			usb_serial_number = "20080411";
			rndis_wceis = <1>;
			status = "okay";
		};

		udc:udc-controller@0x04100000 {
			compatible = "allwinner,sunxi-udc";
			reg = <0x0 0x04100000 0x0 0x1000>, /*udc base*/
			      <0x0 0x00000000 0x0 0x100>; /*sram base*/
			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_OTG>;
			clock-names = "bus_otg";
			resets = <&ccu RST_BUS_OTG>, <&ccu RST_USB_PHY0>;
			reset-names = "otg", "phy";
			status = "okay";
		};

		ehci0:ehci0-controller@0x04101000 {
			compatible = "allwinner,sunxi-ehci0";
			reg = <0x0 0x04101000 0x0 0xFFF>, /*hci0 base*/
			      <0x0 0x00000000 0x0 0x100>, /*sram base*/
			      <0x0 0x04100000 0x0 0x1000>; /*otg base*/
			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_EHCI0>;
			clock-names = "bus_hci";
			resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_USB_PHY0>;
			reset-names = "hci", "phy";
			hci_ctrl_no = <0>;
			status = "okay";
		};

		ohci0:ohci0-controller@0x04101400 {
			compatible = "allwinner,sunxi-ohci0";
			reg = <0x0 0x04101400 0x0 0xFFF>, /*hci0 base*/
			      <0x0 0x00000000 0x0 0x100>, /*sram base*/
			      <0x0 0x04100000 0x0 0x1000>; /*otg base*/
			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_OHCI0>, <&ccu CLK_USB_OHCI0>;
			clock-names = "bus_hci", "ohci";
			resets = <&ccu RST_BUS_OHCI0>, <&ccu RST_USB_PHY0>;
			reset-names = "hci", "phy";
			hci_ctrl_no = <0>;
			status = "okay";
		};

		usbc1:usbc1@0 {
			device_type = "usbc1";
			usb_regulator_io = "nocare";
			usb_wakeup_suspend = <0>;
			status = "disable";
		};

		ehci1:ehci1-controller@0x04200000 {
			compatible = "allwinner,sunxi-ehci1";
			reg = <0x0 0x04200000 0x0 0xFFF>, /*ehci1 base*/
			      <0x0 0x00000000 0x0 0x100>, /*sram base*/
			      <0x0 0x04100000 0x0 0x1000>; /*otg base*/
			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_EHCI1>;
			clock-names = "bus_hci";
			resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_USB_PHY1>;
			reset-names = "hci", "phy";
			hci_ctrl_no = <1>;
			status = "disable";
		};

		ohci1:ohci1-controller@0x04200400 {
			compatible = "allwinner,sunxi-ohci1";
			reg = <0x0 0x04200400 0x0 0xFFF>, /*ohci1 base*/
			      <0x0 0x00000000 0x0 0x100>, /*sram base*/
			      <0x0 0x04100000 0x0 0x1000>; /*otg base*/
			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_OHCI1>, <&ccu CLK_USB_OHCI1>;
			clock-names = "bus_hci", "ohci";
			resets = <&ccu RST_BUS_OHCI1>, <&ccu RST_USB_PHY1>;
			reset-names = "hci", "phy";
			hci_ctrl_no = <1>;
			status = "disable";
		};

		/* codec addr: 0x02030000, the others is invalid to avoid build warining */
		codec:codec@2030000 {
			#sound-dai-cells = <0>;
			compatible = "allwinner,sunxi-internal-codec";
			reg = <0x0 0x02030000 0x0 0x34c>;
			clocks = <&ccu CLK_PLL_AUDIO0>,
				 <&ccu CLK_PLL_AUDIO1_DIV5>,
				 <&ccu CLK_AUDIO_DAC>,
				 <&ccu CLK_AUDIO_ADC>,
				 <&ccu CLK_BUS_AUDIO_CODEC>;
			clock-names = "pll_audio0", "pll_audio1_div5",
				      "audio_clk_dac", "audio_clk_adc",
				      "audio_clk_bus";
			resets = <&ccu RST_BUS_AUDIO_CODEC>;
			rx_sync_en  = <0x00>;
			device_type = "codec";
			status = "okay";
		};

		dummy_cpudai:dummy_cpudai@203034c {
			compatible = "allwinner,sunxi-dummy-cpudai";
			reg = <0x0 0x0203034c 0x0 0x4>;
			tx_fifo_size    = <128>;
			rx_fifo_size    = <256>;
			dac_txdata      = <0x02030020>;
			adc_txdata      = <0x02030040>;
			playback_cma    = <128>;
			capture_cma     = <256>;
			device_type = "cpudai";
			dmas = <&dma 7>, <&dma 7>;
			dma-names = "tx", "rx";
			status = "okay";
		};

		sndcodec:sound@2030340 {
			compatible = "allwinner,sunxi-codec-machine";
			reg = <0x0 0x02030340 0x0 0x4>;
			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
			sunxi,audio-codec = <&codec>;
			sunxi,cpudai-controller = <&dummy_cpudai>;
			device_type = "sndcodec";
			status = "okay";
		};

		sunxi_rpaf_dsp0:rpaf-dsp@203034c {
			compatible = "allwinner,rpaf-dsp0";
			device_type = "sunxi_rpaf_dsp0";
			dsp_id = <0x0>;
			status = "okay";
		};

		/* dmic addr: 0x02031000, the others is invalid to avoid build warining */
		dmic:dmic@2031000{
			#sound-dai-cells = <0>;
			compatible = "allwinner,sunxi-dmic";
			reg = <0x0 0x02031000 0x0 0x50>;
			clocks = <&ccu CLK_PLL_AUDIO0>, /* 98.304M / 90.3168M */
				 <&ccu CLK_DMIC>,
				 <&ccu CLK_BUS_DMIC>;
			clock-names = "pll_audio", "dmic", "dmic_bus";
			resets = <&ccu RST_BUS_DMIC>;
			dmas		= <&dma 8>;
			dma-names	= "rx";
			interrupts	= <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
			clk_parent	= <0x1>;
			capture_cma	= <256>;
			data_vol	= <0xB0>;
			rx_chmap	= <0x76543210>;
			rx_sync_en      = <0x00>;
			device_type = "dmic";
			status = "disabled";
		};

		dmic_codec:sound@2031050{
			#sound-dai-cells = <0>;
			compatible = "dmic-codec";
			reg = <0x0 0x02031050 0x0 0x4>;
			num-channels = <8>;
		};

		sounddmic:sounddmic@2031060 {
			reg = <0x0 0x02031060 0x0 0x4>;
			compatible = "sunxi,simple-audio-card";
			simple-audio-card,name = "snddmic";
			simple-audio-card,capture_only;
			status = "disabled";
			/* simple-audio-card,format = "i2s"; */
			simple-audio-card,cpu {
				sound-dai = <&dmic>;
			};
			simple-audio-card,codec {
				sound-dai = <&dmic_codec>;
			};
		};

		/* daudio0 addr: 0x02032000, the others is invalid to avoid build warining */
		daudio0:daudio@2032000 {
			#sound-dai-cells = <0>;
			compatible = "allwinner,sunxi-daudio";
			reg = <0x0 0x02032000 0x0 0xa0>;
			clocks = <&ccu CLK_PLL_AUDIO0>, /* 98.304M / 90.3168M */
				 <&ccu CLK_I2S0>,
				 <&ccu CLK_BUS_I2S0>;
			clock-names = "pll_audio", "i2s0", "i2s0_bus";
			resets = <&ccu RST_BUS_I2S0>;
			dmas		= <&dma 3>, <&dma 3>;
			dma-names	= "tx", "rx";
			interrupts	= <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl_used		= <0x01>;
			sign_extend		= <0x00>;
			tx_data_mode		= <0x00>;
			rx_data_mode		= <0x00>;
			msb_lsb_first		= <0x00>;
			pcm_lrck_period		= <0x80>;
			slot_width_select	= <0x20>;
			frametype		= <0x00>;
			tdm_config		= <0x01>;
			tdm_num			= <0x00>;
			mclk_div		= <0x00>;
			clk_parent		= <0x00>;
			capture_cma		= <128>;
			playback_cma		= <128>;
			tx_num			= <4>;
			tx_chmap1		= <0x76543210>;
			tx_chmap0		= <0xFEDCBA98>;
			rx_num			= <4>;
			rx_chmap3		= <0x03020100>;
			rx_chmap2		= <0x07060504>;
			rx_chmap1		= <0x0B0A0908>;
			rx_chmap0		= <0x0F0E0D0C>;
			asrc_function_en	= <0x00>;
			rx_sync_en              = <0x00>;
			device_type = "daudio0";
			status = "disabled";
		};

		sounddaudio0: sounddaudio0@20320a0 {
			reg = <0x0 0x020320a0 0x0 0x4>;
			compatible = "sunxi,simple-audio-card";
			simple-audio-card,name = "snddaudio0";
			simple-audio-card,format = "i2s";
			status = "disabled";
			/* simple-audio-card,frame-master = <&daudio0_master>; */
			/* simple-audio-card,bitclock-master = <&daudio0_master>; */
			/* simple-audio-card,bitclock-inversion; */
			/* simple-audio-card,frame-inversion; */
			simple-audio-card,cpu {
				sound-dai = <&daudio0>;
			};
		};

		/* daudio1 addr: 0x02033000, the others is invalid to avoid build warining */
		daudio1:daudio@2033000 {
			#sound-dai-cells = <0>;
			compatible = "allwinner,sunxi-daudio";
			reg = <0x0 0x02033000 0x0 0xa0>;
			clocks = <&ccu CLK_PLL_AUDIO0>, /* 98.304M / 90.3168M */
				 <&ccu CLK_I2S1>,
				 <&ccu CLK_BUS_I2S1>;
			clock-names = "pll_audio", "i2s1", "i2s1_bus";
			resets = <&ccu RST_BUS_I2S1>;
			dmas		= <&dma 4>, <&dma 4>;
			dma-names	= "tx", "rx";
			interrupts	= <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl_used		= <0x01>;
			sign_extend		= <0x00>;
			tx_data_mode		= <0x00>;
			rx_data_mode		= <0x00>;
			msb_lsb_first		= <0x00>;
			pcm_lrck_period		= <0x80>;
			slot_width_select	= <0x20>;
			frametype		= <0x00>;
			tdm_config		= <0x01>;
			tdm_num			= <0x01>;
			mclk_div		= <0x00>;
			clk_parent		= <0x00>;
			capture_cma		= <128>;
			playback_cma		= <128>;
			tx_num			= <4>;
			tx_chmap1		= <0x76543210>;
			tx_chmap0		= <0xFEDCBA98>;
			rx_num			= <4>;
			rx_chmap3		= <0x03020100>;
			rx_chmap2		= <0x07060504>;
			rx_chmap1		= <0x0B0A0908>;
			rx_chmap0		= <0x0F0E0D0C>;
			asrc_function_en	= <0x00>;
			rx_sync_en              = <0x00>;
			device_type = "daudio1";
			status = "disabled";
		};

		sounddaudio1: sounddaudio1@20330a0 {
			reg = <0x0 0x020330a0 0x0 0x4>;
			compatible = "sunxi,simple-audio-card";
			simple-audio-card,name = "snddaudio1";
			simple-audio-card,format = "i2s";
			status = "disabled";
			simple-audio-card,cpu {
				sound-dai = <&daudio1>;
			};
		};

		/* daudio2 addr: 0x02034000, the others is invalid to avoid build warining */
		daudio2:daudio@2034000 {
			#sound-dai-cells = <0>;
			compatible = "allwinner,sunxi-daudio";
			reg = <0x0 0x02034000 0x0 0xa0>;
			clocks = <&ccu CLK_PLL_AUDIO0>, /* 98.304M / 90.3168M */
				 <&ccu CLK_I2S2>,
				 <&ccu CLK_BUS_I2S2>,
				 <&ccu CLK_PLL_AUDIO0_4X>,
				 <&ccu CLK_I2S2_ASRC>;
			resets = <&ccu RST_BUS_I2S2>;
			dmas		= <&dma 5>, <&dma 5>;
			dma-names	= "tx", "rx";
			interrupts	= <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl_used		= <0x01>;
			daudio_type		= <0x00>;
			sign_extend		= <0x00>;
			tx_data_mode		= <0x00>;
			rx_data_mode		= <0x00>;
			msb_lsb_first		= <0x00>;
			pcm_lrck_period		= <0x80>;
			slot_width_select	= <0x20>;
			frametype		= <0x00>;
			tdm_config		= <0x01>;
			tdm_num			= <0x02>;
			mclk_div		= <0x01>;
			clk_parent		= <0x00>;
			capture_cma		= <128>;
			playback_cma		= <128>;
			tx_num			= <4>;
			tx_chmap1		= <0x76543210>;
			tx_chmap0		= <0xFEDCBA98>;
			rx_num			= <4>;
			rx_chmap3		= <0x03020100>;
			rx_chmap2		= <0x07060504>;
			rx_chmap1		= <0x0B0A0908>;
			rx_chmap0		= <0x0F0E0D0C>;
			asrc_function_en	= <0x00>;
			rx_sync_en              = <0x00>;
			device_type = "daudio2";
			status = "disabled";
		};

		sounddaudio2: sounddaudio2@20340a0 {
			reg = <0x0 0x020340a0 0x0 0x4>;
			compatible = "sunxi,simple-audio-card";
			simple-audio-card,name = "snddaudio2";
			simple-audio-card,format = "i2s";
			status = "disabled";
			simple-audio-card,cpu {
				sound-dai = <&daudio2>;
			};
		};

		hdmiaudio: hdmiaudio@20340a4 {
			#sound-dai-cells = <0>;
			reg = <0x0 0x020340a4 0x0 0x4>;
			compatible = "allwinner,sunxi-hdmiaudio";
			status = "disabled";
		};

		/* spdif addr: 0x02036000, the others is invalid to avoid build warining */
		spdif:spdif@2036000 {
			#sound-dai-cells = <0>;
			compatible = "allwinner,sunxi-spdif";
			reg = <0x0 0x02036000 0x0 0x58>;
			clocks = <&ccu CLK_PLL_AUDIO0_4X>,	/* 90.3168M */
				 <&ccu CLK_SPDIF_TX>,
				 <&ccu CLK_BUS_SPDIF>,
				 <&ccu CLK_PLL_AUDIO1>,         /* 98.304M */
				 <&ccu CLK_PLL_AUDIO1_DIV5>,
				 <&ccu CLK_PLL_PERIPH0>,
				 <&ccu CLK_SPDIF_RX>;
			clock-names = "pll_audio0", "spdif", "spdif_bus",
				      "pll_audio1", "pll_audio1_div5",
				      "pll_periph", "spdif_rx";
			resets = <&ccu RST_BUS_SPDIF>;
			dmas		= <&dma 2>, <&dma 2>;
			dma-names	= "tx", "rx";
			interrupts	= <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
			clk_parent	= <0x1>;
			playback_cma	= <128>;
			capture_cma	= <128>;
			rx_sync_en      = <0>;
			device_type = "spdif";
			status = "disabled";
		};

		soundspdif:soundspdif@203605c {
			reg = <0x0 0x0203605c 0x0 0x4>;
			compatible = "sunxi,simple-audio-card";
			simple-audio-card,name = "sndspdif";
			status = "disabled";
			 /* simple-audio-card,format = "i2s"; */
			 simple-audio-card,cpu {
				 sound-dai = <&spdif>;
			 };
			 simple-audio-card,codec {
				 /*snd-soc-dummy*/
			 };
		};

		ths: ths@02009400 {
			compatible = "allwinner,sun8iw20p1-ths";
			reg = <0x0 0x02009400 0x0 0x400>;
			clocks = <&ccu CLK_BUS_THS>;
			clock-names = "bus";
			resets = <&ccu RST_BUS_THS>;
			nvmem-cells = <&ths_calib>;
			nvmem-cell-names = "calibration";
			#thermal-sensor-cells = <1>;
		};

		tvd: tvd@05c00000 {
			compatible = "allwinner,sunxi-tvd";
			reg = <0x0 0x05c00000 0x0 0x00010000>;/*tvd_top*/
			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&ccu CLK_BUS_TVD_TOP>,
			<&ccu CLK_MBUS_TVIN>;
			clock-names = "clk_bus_tvd_top",
			"clk_mbus_tvd";

			resets = <&ccu RST_BUS_TVD_TOP>;
			reset-names = "rst_bus_tvd_top";

			tvd-number = <1>;
			tvds = <&tvd0>;
			status = "okay";
		};

		tvd0: tvd0@05c01000 {
			compatible = "allwinner,sunxi-tvd0";
			reg = <0x0 0x05c01000 0x0 0x00010000>;
			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&ccu CLK_TVD>,
			<&ccu CLK_BUS_TVD>;
			clock-names = "clk_tvd0","clk_bus_tvd0";

			resets = <&ccu RST_BUS_TVD>;
			reset-names = "rst_bus_tvd0";

			assigned-clocks = <&ccu CLK_TVD>;
			assigned-clock-parents = <&ccu CLK_PLL_VIDEO1>;

			tvd_used = <1>;
			tvd_if = <0>;
			status = "okay";
		};

	};
};

日志

shz18877605430

@lucky123456 改了的，https://bbs.aw-ol.com/topic/3339/芒果t113-s3-uart0改为uart1-uboot无法启动?_=1681694893355

shz18877605430

芒果T113-s3 uart0改为uart1，uboot无法启动，具体更改了如下内容，但是还是不行，请教各位大佬。

1、设备树 board.dts

2、sys_config.fex

3、env.cfg

4、配置文件sun8iw20p1_defconfig

5、内核配置

终端串口输出的信息如下：

之前大佬说是optee.bin的问题，我更换了也还是不行。不知道哪里有问题，但是使用别人提供得固件烧录是可以正常启动的。

shz18877605430

@yteraa 我也遇到了这个问题，还没解决。

shz18877605430

@yudidage 打一下patch，再全志官网下载代码的地方，D1s和T113都是一样的，补丁打好后，改一下uboot和内核设备树中的lcd节点，改一下dclk，改到22或者24Mhz

shz18877605430

@whycan 测过了，是拉高的。高电平

shz18877605430

@whycan 这个蓝牙使能管脚会一直高吗？还是瞬间拉高然后回到低电平？

shz18877605430

@whycan 我测了的时候已经是拉低了（不上电默认和GND导通的），但是我还是把100k的电阻接上去做下拉了。还是出现这个问题。

shz18877605430

F133跑bluez的时候，加载rtk_hciattach -n -s 115200 ttyS1 rtk_h5 &报错

运行了以下操作，rtl8723ds驱动已经运行，hci_uart.ko也运行了。

/etc/init.d/dbus start
echo 0 > /sys/class/rfkill/rfkill0/state
echo 1 > /sys/class/rfkill/rfkill0/state

加载rtk_hciattach -n -s 115200 ttyS1 rtk_h5 &的时候出现了协议不支持。但是内核已经开启了h5


root@TinaLinux:/# Realtek Bluetooth :Realtek Bluetooth init uart with init speed:115200, type:HCI UART H5
Realtek Bluetooth :Realtek hciattach version 3.1

Realtek Bluetooth :Use epoll
Realtek Bluetooth :[SYNC] Get SYNC Resp Pkt
Realtek Bluetooth :[CONFIG] Get SYNC pkt
Realtek Bluetooth :[CONFIG] Get CONFG pkt
Realtek Bluetooth :[CONFIG] Get CONFG resp pkt
Realtek Bluetooth :dic is 1, cfg field 0x14
Realtek Bluetooth :H5 init finished

Realtek Bluetooth :Realtek H5 IC
Realtek Bluetooth :Receive cmd complete event of command: 1001
Realtek Bluetooth :HCI Version 0x08
Realtek Bluetooth :HCI Revision 0x000d
Realtek Bluetooth :LMP Subversion 0x8723
Realtek Bluetooth :Receive cmd complete event of command: fc6d
Realtek Bluetooth :Read ROM version 02
Realtek Bluetooth :LMP Subversion 0x8723
Realtek Bluetooth :EVersion 2
Realtek Bluetooth :IC: RTL8723DS
Realtek Bluetooth :Firmware/config: rtl8723d_fw, rtl8723d_config
Realtek Bluetooth :Couldnt open extra config /opt/rtk_btconfig.txt, No such file or directory
Realtek Bluetooth :Couldnt access customer BT MAC file /opt/bdaddr
Realtek Bluetooth :Origin cfg len 48
Realtek Bluetooth :55 ab 23 87 2a 00 0c 00 10 02 80 92 04 50 c5 ea
Realtek Bluetooth :19 e1 1b fd af 5f 01 a4 0b d9 00 01 0f e4 00 01
Realtek Bluetooth :08 f3 00 01 0c f4 00 08 01 00 01 90 00 00 09 04
Realtek Bluetooth :Config baudrate: 04928002
Realtek Bluetooth :uart flow ctrl: 1
Realtek Bluetooth :Vendor baud from Config file: 04928002
Realtek Bluetooth :New cfg len 48
Realtek Bluetooth :55 ab 23 87 2a 00 0c 00 10 02 80 92 04 50 c5 ea
Realtek Bluetooth :19 e1 1b fd af 5f 01 a4 0b d9 00 01 0f e4 00 01
Realtek Bluetooth :08 f3 00 01 0c f4 00 08 01 00 01 90 00 00 09 04
Realtek Bluetooth :Load FW /lib/firmware/rtlbt/rtl8723d_fw OK, size 52096
Realtek Bluetooth :rtb_get_fw_project_id: opcode 0, len 1, data 9
Realtek Bluetooth :FW version 0xaa7add92, Patch num 3
Realtek Bluetooth :Chip id 0x0001
Realtek Bluetooth :Chip id 0x0002
Realtek Bluetooth :Chip id 0x0003
Realtek Bluetooth :Patch length 0x81b8
Realtek Bluetooth :Start offset 0x00004980
Realtek Bluetooth :Svn version:    20318
Realtek Bluetooth :Coexistence: BTCOEX_20180125-2323

Realtek Bluetooth :FW  exists, Config file  exists
Realtek Bluetooth :Total len 33256 for fwc
Realtek Bluetooth :baudrate in change speed command: 0x02 0x80 0x92 0x04
Realtek Bluetooth :Receive cmd complete event of command: fc17
Realtek Bluetooth :Received cc of vendor change baud
Realtek Bluetooth :Final speed 1500000
Realtek Bluetooth :end_idx: 131, lp_len: 244, additional pkts: 0

Realtek Bluetooth :Start downloading...
Realtek Bluetooth :Send last pkt
Realtek Bluetooth :Enable host hw flow control
Realtek Bluetooth :h5_hci_reset: Issue hci reset cmd
Realtek Bluetooth :Receive cmd complete event of command: 0c03
Realtek Bluetooth :Received cc of hci reset cmd
Realtek Bluetooth :Init Process finished
Realtek Bluetooth ERROR: Can't set device 93, Protocol not supported
Realtek Bluetooth ERROR: Can't initialize device 93, Protocol not supported

各位大佬指教一下！！！

shz18877605430

8723ds的wlan0是能正常使用的，已经连接网络，能ping通。

shz18877605430

大佬们，F133启动之后，/sys/class目录下找不到rfkill文件，配置已经开启，内核已经打开驱动，但是就是找不到rfkill目录。

内核日志如下：

U-Boot 2018.05-g24521d6-dirty (Mar 10 2023 - 20:31:27 +0800) Allwinner Technology

[00.354]DRAM:  64 MiB
[00.356]Relocation Offset is: 01ee7000
[00.361]secure enable bit: 0
[00.364]CPU=720 MHz,PLL6=600 Mhz,AHB=200 Mhz, APB1=100Mhz  MBus=300Mhz
[00.370]flash init start
[00.372]workmode = 0,storage type = 0
sspi->base_addr = 0x4025000, the SPI control register:
[VER] 0x4025000 = 0x00010001, [GCR] 0x4025004 = 0x00000083, [TCR] 0x4025008 = 0x00000184
[ICR] 0x4025010 = 0x00000f00, [ISR] 0x4025014 = 0x00000032, [FCR] 0x4025018 = 0x00200020
[FSR] 0x402501c = 0x00000000, [WCR] 0x4025020 = 0x00000000, [CCR] 0x4025024 = 0x00000002
[SDC] 0x4025028 = 0x00002000, [BCR] 0x4025030 = 0x00000000, [TCR] 0x4025034 = 0x00000000
[BCC] 0x4025038 = 0x20000000, [DMA] 0x4025088 = 0x000000e5

[00.421]sunxi-spinand-phy: not detect any munufacture from id table
[00.427]sunxi-spinand-phy: get spi-nand Model from fdt fail
[00.433]sunxi-spinand-phy: get phy info from fdt fail

device nand0 <nand>, # parts = 4
 #: name                size            offset          mask_flags
 0: boot0               0x00100000      0x00000000      1
 1: uboot               0x00300000      0x00100000      1
 2: secure_storage      0x00100000      0x00400000      1
 3: sys                 0x07b00000      0x00500000      0

active partition: nand0,0 - (boot0) 0x00100000 @ 0x00000000

defaults:
mtdids  : nand0=nand
mtdparts: mtdparts=nand:1024k@0(boot0)ro,3072k@1048576(uboot)ro,1024k@4194304(secure_storage)ro,-(sys)
[00.547]ubi0: attaching mtd4
[00.643]ubi0: scanning is finished
[00.650]ubi0: attached mtd4 (name "sys", size 123 MiB)
[00.655]ubi0: PEB size: 262144 bytes (256 KiB), LEB size: 258048 bytes
[00.661]ubi0: min./max. I/O unit sizes: 4096/4096, sub-page size 2048
[00.667]ubi0: VID header offset: 2048 (aligned 2048), data offset: 4096
[00.674]ubi0: good PEBs: 492, bad PEBs: 0, corrupted PEBs: 0
[00.679]ubi0: user volume: 9, internal volumes: 1, max. volumes count: 128
[00.686]ubi0: max/mean erase counter: 2/1, WL threshold: 4096, image sequence number: 0
[00.693]ubi0: available PEBs: 0, total reserved PEBs: 492, PEBs reserved for bad PEB handling: 20
[00.702]sunxi flash init ok
[00.704]line:703 init_clocks
[00.708]drv_disp_init
fdt_getprop_u32 s_pwm.pwm-base fail
[00.728]drv_disp_init finish
[00.730]boot_gui_init:start
[00.733]set disp.dev2_output_type fail. using defval=0
[00.740]boot_gui_init:finish
partno erro : can't find partition bootloader
54 bytes read in 1 ms (52.7 KiB/s)
[00.871]bmp_name=bootlogo.bmp size 38454
38454 bytes read in 3 ms (12.2 MiB/s)
[00.920]LCD open finish
[00.995]Loading Environment from SUNXI_FLASH... OK
[01.018]out of usb burn from boot: not need burn key
[01.024]Item0 (Map) magic is bad
partno erro : can't find partition private
[01.052]update bootcmd
[01.065]change working_fdt 0x42aa6da0 to 0x42a86da0
No reserved memory region found in source FDT
[01.101]update dts
noncached_alloc(): addr = 0x42ca5080
noncached_alloc(): addr = 0x42ca50c0
noncached_alloc(): addr = 0x42ca5100
noncached_alloc(): addr = 0x42ca5940
geth_sys_init:634: get node 'gmac0' error
geth_sys_init fail!
[01.121]Board Net Initialization Failed
[01.125]No ethernet found.
Hit any key to stop autoboot:  0
[02.528]no vendor_boot partition is found
Android's image name: d1s-nezha
Detect comp none
[02.547]
Starting kernel ...

** 4 printk messages dropped **
Movable zone start for each node
Early memory node ranges
  node   0: [mem 0x0000000040000000-0x0000000043ffffff]
Initmem setup node 0 [mem 0x0000000040000000-0x0000000043ffffff]
On node 0 totalpages: 16384
  DMA32 zone: 224 pages used for memmap
  DMA32 zone: 0 pages reserved
  DMA32 zone: 16384 pages, LIFO batch:3
elf_hwcap is 0x20112d
pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768
pcpu-alloc: [0] 0
Built 1 zonelists, mobility grouping on.  Total pages: 16160
Kernel command line: ubi.mtd=sys ubi.block=0,rootfs earlyprintk=sunxi-uart,0x02500000 clk_ignore_unused initcall_debug=0 console=ttyS0,115200 loglevel=8 root=/dev/ubiblock0_5 rootfstype=squashfs init=/pseudo_init partitions=mbr@ubi0_0:boot-resource@ubi0_1:env@ubi0_2:env-redund@ubi0_3:boot@ubi0_4:rootfs@ubi0_5:recovery@ubi0_6:rootfs_data@ubi0_7:UDISK@ubi0_8: cma=0M snum= mac_addr= wifi_mac= bt_mac= specialstr= gpt=1 androidboot.hardware=sun20iw1p1 boot_type=5 androidboot.boot_type=5 gpt=1 uboot_message=2018.05-g24521d6-dirty(03
Dentry cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
Inode-cache hash table entries: 4096 (order: 3, 32768 bytes, linear)
Sorting __ex_table...
mem auto-init: stack:off, heap alloc:off, heap free:off
Memory: 54564K/65536K available (5087K kernel code, 497K rwdata, 1868K rodata, 144K init, 331K bss, 10972K reserved, 0K cma-reserved)
SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
rcu: Preemptible hierarchical RCU implementation.
        Tasks RCU enabled.
rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
NR_IRQS: 0, nr_irqs: 0, preallocated irqs: 0
plic: mapped 200 interrupts with 1 handlers for 2 contexts.
riscv_timer_init_dt: Registering clocksource cpuid [0] hartid [0]
clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x588fe9dc0, max_idle_ns: 440795202592 ns
sched_clock: 64 bits at 24MHz, resolution 41ns, wraps every 4398046511097ns
riscv_timer_clockevent depends on broadcast, but no broadcast function available
clocksource: timer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=240000)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 512 (order: 0, 4096 bytes, linear)
Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes, linear)
ASID allocator initialised with 65536 entries
rcu: Hierarchical SRCU implementation.
devtmpfs: initialized
random: get_random_u32 called from bucket_table_alloc.isra.27+0xfe/0x120 with crng_init=0
clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
futex hash table entries: 256 (order: 0, 6144 bytes, linear)
pinctrl core: initialized pinctrl subsystem
NET: Registered protocol family 16
DMA: preallocated 256 KiB pool for atomic allocations
cpuidle: using governor menu
rtc_ccu: sunxi ccu init OK
clock: sunxi ccu init OK
clock: sunxi ccu init OK
iommu: Default domain type: Translated
sunxi iommu: irq = 4
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
videodev: Linux video capture interface: v2.00
Advanced Linux Sound Architecture Driver Initialized.
Bluetooth: Core ver 2.22
NET: Registered protocol family 31
Bluetooth: HCI device and connection manager initialized
Bluetooth: HCI socket layer initialized
Bluetooth: L2CAP socket layer initialized
Bluetooth: SCO socket layer initialized
pwm module init!
g2d 5410000.g2d: Adding to iommu group 0
G2D: rcq version initialized.major:252
clocksource: Switched to clocksource riscv_clocksource
sun8iw20-pinctrl 2000000.pinctrl: initialized sunXi PIO driver
NET: Registered protocol family 2
tcp_listen_portaddr_hash hash table entries: 256 (order: 0, 4096 bytes, linear)
TCP established hash table entries: 512 (order: 0, 4096 bytes, linear)
TCP bind hash table entries: 512 (order: 0, 4096 bytes, linear)
TCP: Hash tables configured (established 512 bind 512)
UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
NET: Registered protocol family 1
sun8iw20-pinctrl 2000000.pinctrl: 2000000.pinctrl supply vcc-pc not found, using dummy regulator
spi spi0: spi0 supply spi not found, using dummy regulator
sunxi_spi_resource_get()2151 - [spi0] SPI MASTER MODE
sunxi_spi_resource_get()2189 - Failed to get sample mode
sunxi_spi_resource_get()2194 - Failed to get sample delay
sunxi_spi_resource_get()2198 - sample_mode:-1431633921 sample_delay:-1431633921
sunxi_spi_clk_init()2240 - [spi0] mclk 100000000
sunxi_spi_probe()2653 - [spi0]: driver probe succeed, base ffffffd004058000, irq 31
workingset: timestamp_bits=62 max_order=14 bucket_order=0
squashfs: version 4.0 (2009/01/31) Phillip Lougher
ntfs: driver 2.1.32 [Flags: R/W].
io scheduler mq-deadline registered
io scheduler kyber registered
[DISP]disp_module_init
disp 5000000.disp: Adding to iommu group 0
[DISP] parser_disp_init_para,line:1430:
of_property_read fb0_width fail
[DISP] disp_init,line:2386:
smooth display screen:0 type:1 mode:4
display_fb_request,fb_id:0
Freeing logo buffer memory: 1500K
disp_al_manager_apply ouput_type:1
sun8iw20-pinctrl 2000000.pinctrl: 2000000.pinctrl supply vcc-pd not found, using dummy regulator
[DISP]disp_module_init finish
sunxi_sid_init()551 - insmod ok
pwm-regulator: supplied by regulator-dummy
sun8iw20-pinctrl 2000000.pinctrl: 2000000.pinctrl supply vcc-pe not found, using dummy regulator
uart uart0: get regulator failed
uart uart0: uart0 supply uart not found, using dummy regulator
uart0: ttyS0 at MMIO 0x2500000 (irq = 18, base_baud = 1500000) is a SUNXI
sw_console_setup()1808 - console setup baud 115200 parity n bits 8, flow n
printk: console [ttyS0] enabled
sun8iw20-pinctrl 2000000.pinctrl: 2000000.pinctrl supply vcc-pg not found, using dummy regulator
uart uart1: get regulator failed
uart uart1: uart1 supply uart not found, using dummy regulator
uart1: ttyS1 at MMIO 0x2500400 (irq = 19, base_baud = 1500000) is a SUNXI
misc dump reg init
sunxi-rfkill soc@3000000:rfkill@0: module version: v1.0.9
sunxi-rfkill soc@3000000:rfkill@0: get gpio chip_en failed
sunxi-rfkill soc@3000000:rfkill@0: get gpio power_en failed
sunxi-rfkill soc@3000000:rfkill@0: wlan_busnum (1)
sunxi-rfkill soc@3000000:rfkill@0: Missing wlan_power.
sunxi-rfkill soc@3000000:rfkill@0: wlan clock[0] (32k-fanout1)
sunxi-rfkill soc@3000000:rfkill@0: get gpio wlan_regon failed
sunxi-rfkill soc@3000000:rfkill@0: wlan_hostwake gpio=202 assert=1
sunxi-rfkill soc@3000000:rfkill@0: wakeup source is enabled
sunxi-rfkill soc@3000000:rfkill@0: Missing bt_power.
sunxi-rfkill soc@3000000:rfkill@0: bt clock[0] (32k-fanout1)
sunxi-rfkill soc@3000000:rfkill@0: bt_rst gpio=210 assert=0
[ADDR_MGT] addr_mgt_probe: module version: v1.0.10
[ADDR_MGT] addr_mgt_probe: success.
sunxi-spinand: AW SPINand MTD Layer Version: 2.0 20201228
sunxi-spinand-phy: AW SPINand Phy Layer Version: 1.10 20200306
sunxi-spinand-phy: not detect any munufacture from id table
sunxi-spinand-phy: get spi-nand Model from fdt fail
sunxi-spinand-phy: get phy info from fdt fail
sunxi-spinand-phy: not detect munufacture from fdt
sunxi-spinand-phy: detect munufacture from id table: GD
sunxi-spinand-phy: detect spinand id: ffff51c8 ffffffff
sunxi-spinand-phy: ========== arch info ==========
sunxi-spinand-phy: Model:               GD5F1GQ5UEYIG
sunxi-spinand-phy: Munufacture:         GD
sunxi-spinand-phy: DieCntPerChip:       1
sunxi-spinand-phy: BlkCntPerDie:        1024
sunxi-spinand-phy: PageCntPerBlk:       64
sunxi-spinand-phy: SectCntPerPage:      4
sunxi-spinand-phy: OobSizePerPage:      64
sunxi-spinand-phy: BadBlockFlag:        0x0
sunxi-spinand-phy: OperationOpt:        0x7
sunxi-spinand-phy: MaxEraseTimes:       50000
sunxi-spinand-phy: EccFlag:             0x1
sunxi-spinand-phy: EccType:             7
sunxi-spinand-phy: EccProtectedType:    2
sunxi-spinand-phy: ========================================
sunxi-spinand-phy:
sunxi-spinand-phy: ========== physical info ==========
sunxi-spinand-phy: TotalSize:    128 M
sunxi-spinand-phy: SectorSize:   512 B
sunxi-spinand-phy: PageSize:     2 K
sunxi-spinand-phy: BlockSize:    128 K
sunxi-spinand-phy: OOBSize:      64 B
sunxi-spinand-phy: ========================================
sunxi-spinand-phy:
sunxi-spinand-phy: ========== logical info ==========
sunxi-spinand-phy: TotalSize:    128 M
sunxi-spinand-phy: SectorSize:   512 B
sunxi-spinand-phy: PageSize:     4 K
sunxi-spinand-phy: BlockSize:    256 K
sunxi-spinand-phy: OOBSize:      128 B
sunxi-spinand-phy: ========================================
sunxi-spinand-phy: GD5F1GQ5UEYIG reset rx bit width to 1
sunxi-spinand-phy: GD5F1GQ5UEYIG reset tx bit width to 1
sunxi-spinand-phy: block lock register: 0x00
sunxi-spinand-phy: feature register: 0x11
sunxi-spinand-phy: sunxi physic nand init end
Creating 4 MTD partitions on "sunxi_mtd_nand":
0x000000000000-0x000000100000 : "boot0"
0x000000100000-0x000000500000 : "uboot"
random: fast init done
0x000000500000-0x000000600000 : "secure_storage"
0x000000600000-0x000008000000 : "sys"
RTL871X: module init start
RTL871X: rtl8189fs v4.3.24.8_22657.20170607
RTL871X: module init ret=0
ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
sunxi-ehci: EHCI SUNXI driver
get ehci1-controller wakeup-source is fail.
sunxi ehci1-controller don't init wakeup source
[sunxi-ehci1]: probe, pdev->name: 4200000.ehci1-controller, sunxi_ehci: 0xffffffe00079b9c0, 0x:ffffffd004071000, irq_no:31
sunxi-ehci 4200000.ehci1-controller: 4200000.ehci1-controller supply drvvbus not found, using dummy regulator
sunxi-ehci 4200000.ehci1-controller: 4200000.ehci1-controller supply hci not found, using dummy regulator
sunxi-ehci 4200000.ehci1-controller: EHCI Host Controller
sunxi-ehci 4200000.ehci1-controller: new USB bus registered, assigned bus number 1
sunxi-ehci 4200000.ehci1-controller: irq 49, io mem 0x04200000
sunxi-ehci 4200000.ehci1-controller: USB 2.0 started, EHCI 1.00
hub 1-0:1.0: USB hub found
hub 1-0:1.0: 1 port detected
ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
sunxi-ohci: OHCI SUNXI driver
get ohci1-controller wakeup-source is fail.
sunxi ohci1-controller don't init wakeup source
[sunxi-ohci1]: probe, pdev->name: 4200400.ohci1-controller, sunxi_ohci: 0xffffffe00079bd88
sunxi-ohci 4200400.ohci1-controller: 4200400.ohci1-controller supply drvvbus not found, using dummy regulator
sunxi-ohci 4200400.ohci1-controller: 4200400.ohci1-controller supply hci not found, using dummy regulator
sunxi-ohci 4200400.ohci1-controller: OHCI Host Controller
sunxi-ohci 4200400.ohci1-controller: new USB bus registered, assigned bus number 2
sunxi-ohci 4200400.ohci1-controller: irq 50, io mem 0x04200400
hub 2-0:1.0: USB hub found
hub 2-0:1.0: 1 port detected
sunxi-rtc 7090000.rtc: errata__fix_alarm_day_reg_default_value(): ALARM0_DAY_REG=0, set it to 1
sunxi-rtc 7090000.rtc: registered as rtc0
sunxi-rtc 7090000.rtc: setting system clock to 1970-01-01T00:00:04 UTC (4)
sunxi-rtc 7090000.rtc: sunxi rtc probed
i2c /dev entries driver
IR NEC protocol handler initialized
uvcvideo: Unable to create debugfs directory
usbcore: registered new interface driver uvcvideo
USB Video Class driver (1.1.1)
sunxi cedar version 1.1
sunxi-cedar 1c0e000.ve: Adding to iommu group 0
VE: install start!!!

VE: cedar-ve the get irq is 6

VE: install end!!!

VE: sunxi_cedar_probe
sunxi-mmc 4021000.sdmmc: SD/MMC/SDIO Host Controller Driver(v4.21 2021-11-18 10:02)
sunxi-mmc 4021000.sdmmc: ***ctl-spec-caps*** 8
sunxi-mmc 4021000.sdmmc: No vmmc regulator found
sunxi-mmc 4021000.sdmmc: No vqmmc regulator found
sunxi-mmc 4021000.sdmmc: No vdmmc regulator found
sunxi-mmc 4021000.sdmmc: No vd33sw regulator found
sunxi-mmc 4021000.sdmmc: No vd18sw regulator found
sunxi-mmc 4021000.sdmmc: No vq33sw regulator found
sunxi-mmc 4021000.sdmmc: No vq18sw regulator found
sunxi-mmc 4021000.sdmmc: Cann't get pin bias hs pinstate,check if needed
sunxi-mmc 4021000.sdmmc: sdc set ios:clk 0Hz bm PP pm UP vdd 21 width 1 timing LEGACY(SDR12) dt B
sunxi-mmc 4021000.sdmmc: no vqmmc,Check if there is regulator
sunxi-mmc 4021000.sdmmc: sdc set ios:clk 400000Hz bm PP pm ON vdd 21 width 1 timing LEGACY(SDR12) dt B
sunxi-mmc 4021000.sdmmc: detmode:manually by software
ashmem: initialized
exFAT: Version 1.3.0
sunxi-mmc 4021000.sdmmc: sdc set ios:clk 400000Hz bm PP pm ON vdd 21 width 1 timing LEGACY(SDR12) dt B
[AUDIOCODEC][sunxi_codec_parse_params][2412]:digital_vol:0, lineout_vol:26, mic1gain:31, mic2gain:31 pa_msleep:120, pa_level:1, pa_pwr_level:1

[AUDIOCODEC][sunxi_codec_parse_params][2448]:adcdrc_cfg:0, adchpf_cfg:1, dacdrc_cfg:0, dachpf:0
[AUDIOCODEC][sunxi_internal_codec_probe][2609]:codec probe finished
sunxi-mmc 4021000.sdmmc: sdc set ios:clk 400000Hz bm PP pm ON vdd 21 width 1 timing LEGACY(SDR12) dt B
sid_rd_ver_reg()254 - ver >= 4, soc ver:5
[SNDCODEC][sunxi_card_init][583]:card init finished
sunxi-mmc 4021000.sdmmc: card claims to support voltages below defined range
sunxi-codec-machine 2030340.sound: 2030000.codec <-> 203034c.dummy_cpudai mapping ok
input: audiocodec sunxi Audio Jack as /devices/platform/soc@3000000/2030340.sound/sound/card0/input0
[SNDCODEC][sunxi_card_dev_probe][836]:register card finished
NET: Registered protocol family 10
Segment Routing with IPv6
[SNDCODEC][sunxi_hs_init_work][259]:resume-->report switch
NET: Registered protocol family 17
Bluetooth: RFCOMM TTY layer initialized
Bluetooth: RFCOMM socket layer initialized
sunxi-mmc 4021000.sdmmc: sdc set ios:clk 400000Hz bm PP pm ON vdd 21 width 1 timing SD-HS(SDR25) dt B
Bluetooth: RFCOMM ver 1.11
sunxi-mmc 4021000.sdmmc: sdc set ios:clk 50000000Hz bm PP pm ON vdd 21 width 1 timing SD-HS(SDR25) dt B
sunxi-i2c sunxi-i2c2: sunxi-i2c2 supply twi not found, using dummy regulator
sunxi-mmc 4021000.sdmmc: sdc set ios:clk 50000000Hz bm PP pm ON vdd 21 width 4 timing SD-HS(SDR25) dt B
mmc0: new high speed SDIO card at address 0001
input: fts_ts as /devices/platform/soc@3000000/sunxi-i2c2/i2c-2/2-0038/input/input1
sunxi-i2c sunxi-i2c2: SLA+W has been transmitted; ACK not received
sunxi-i2c sunxi-i2c2: engine-mode: xfer failed(dev addr:0x38)
sunxi-i2c sunxi-i2c2: engine-mode: xfer failed(dev addr:0x38)
fts_ts 2-0038: 2-0038 supply  not found, using dummy regulator
fts_ts 2-0038: 2-0038 supply  not found, using dummy regulator
sun8iw20-pinctrl 2000000.pinctrl: 2000000.pinctrl supply vcc-pb not found, using dummy regulator
sunxi-i2c sunxi-i2c2: SLA+W has been transmitted; ACK not received
sunxi-i2c sunxi-i2c2: engine-mode: xfer failed(dev addr:0x38)
sunxi-i2c sunxi-i2c2: SLA+W has been transmitted; ACK not received
sunxi-i2c sunxi-i2c2: engine-mode: xfer failed(dev addr:0x38)
sunxi-i2c sunxi-i2c2: SLA+W has been transmitted; ACK not received
sunxi-i2c sunxi-i2c2: engine-mode: xfer failed(dev addr:0x38)
sunxi-i2c sunxi-i2c2: SLA+W has been transmitted; ACK not received
sunxi-i2c sunxi-i2c2: engine-mode: xfer failed(dev addr:0x38)
sunxi-i2c sunxi-i2c2: SLA+W has been transmitted; ACK not received
sunxi-i2c sunxi-i2c2: engine-mode: xfer failed(dev addr:0x38)
sunxi-i2c sunxi-i2c2: SLA+W has been transmitted; ACK not received
sunxi-i2c sunxi-i2c2: engine-mode: xfer failed(dev addr:0x38)
sunxi-i2c sunxi-i2c2: SLA+W has been transmitted; ACK not received
sunxi-i2c sunxi-i2c2: engine-mode: xfer failed(dev addr:0x38)
sunxi-i2c sunxi-i2c2: SLA+W has been transmitted; ACK not received
sunxi-i2c sunxi-i2c2: engine-mode: xfer failed(dev addr:0x38)
sunxi-i2c sunxi-i2c2: SLA+W has been transmitted; ACK not received
sunxi-i2c sunxi-i2c2: engine-mode: xfer failed(dev addr:0x38)
sunxi-i2c sunxi-i2c2: SLA+W has been transmitted; ACK not received
sunxi-i2c sunxi-i2c2: engine-mode: xfer failed(dev addr:0x38)
sunxi-i2c sunxi-i2c2: SLA+W has been transmitted; ACK not received
sunxi-i2c sunxi-i2c2: engine-mode: xfer failed(dev addr:0x38)
sunxi-i2c sunxi-i2c2: SLA+W has been transmitted; ACK not received
sunxi-i2c sunxi-i2c2: engine-mode: xfer failed(dev addr:0x38)
sunxi-i2c sunxi-i2c2: SLA+W has been transmitted; ACK not received
sunxi-i2c sunxi-i2c2: engine-mode: xfer failed(dev addr:0x38)
sunxi-i2c sunxi-i2c2: SLA+W has been transmitted; ACK not received
sunxi-i2c sunxi-i2c2: engine-mode: xfer failed(dev addr:0x38)
sunxi-i2c sunxi-i2c2: SLA+W has been transmitted; ACK not received
sunxi-i2c sunxi-i2c2: engine-mode: xfer failed(dev addr:0x38)
sunxi-i2c sunxi-i2c2: probe success
reg-fixed-voltage usb1-vbus: nonexclusive access to GPIO for usb1-vbus
get ehci0-controller wakeup-source is fail.
sunxi ehci0-controller don't init wakeup source
[sunxi-ehci0]: probe, pdev->name: 4101000.ehci0-controller, sunxi_ehci: 0xffffffe00079b230, 0x:ffffffd0040f4000, irq_no:2e
[sunxi-ehci0]: Not init ehci0
get ohci0-controller wakeup-source is fail.
sunxi ohci0-controller don't init wakeup source
[sunxi-ohci0]: probe, pdev->name: 4101400.ohci0-controller, sunxi_ohci: 0xffffffe00079b5f8
[sunxi-ohci0]: Not init ohci0
ubi0: attaching mtd3
ubi0: scanning is finished
ubi0: attached mtd3 (name "sys", size 122 MiB)
ubi0: PEB size: 262144 bytes (256 KiB), LEB size: 258048 bytes
ubi0: min./max. I/O unit sizes: 4096/4096, sub-page size 2048
ubi0: VID header offset: 2048 (aligned 2048), data offset: 4096
ubi0: good PEBs: 488, bad PEBs: 0, corrupted PEBs: 0
ubi0: user volume: 9, internal volumes: 1, max. volumes count: 128
ubi0: max/mean erase counter: 2/1, WL threshold: 4096, image sequence number: 0
ubi0: available PEBs: 6, total reserved PEBs: 482, PEBs reserved for bad PEB handling: 10
ubi0: background thread "ubi_bgt0d" started, PID 62
block ubiblock0_5: created from ubi0:5(rootfs)
ERR: det_vbus gpio_request failed
platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
clk: Not disabling unused clocks
ALSA device list:
  #0: audiocodec
alloc_fd: slot 0 not NULL!
cfg80211: failed to load regulatory.db
VFS: Mounted root (squashfs filesystem) readonly on device 254:0.
devtmpfs: mounted
Freeing unused kernel memory: 144K
This architecture does not have kernel memory protection.
Run /pseudo_init as init process
random: crng init done
mount: mounting none on /dev failed: Device or resource busy
UBIFS (ubi0:7): Mounting in unauthenticated mode
UBIFS (ubi0:7): background thread "ubifs_bgt0_7" started, PID 90
UBIFS (ubi0:7): recovery needed
UBIFS (ubi0:7): recovery completed
UBIFS (ubi0:7): UBIFS: mounted UBI device 0, volume 7, name "rootfs_data"
UBIFS (ubi0:7): LEB size: 258048 bytes (252 KiB), min./max. I/O unit sizes: 4096 bytes/4096 bytes
UBIFS (ubi0:7): FS size: 3096576 bytes (2 MiB, 12 LEBs), journal size 1806337 bytes (1 MiB, 5 LEBs)
UBIFS (ubi0:7): reserved for root: 146258 bytes (142 KiB)
UBIFS (ubi0:7): media format: w5/r0 (latest is w5/r0), UUID EF7D946C-F15A-4E7A-8105-8B255A805796, small LPT model
can't run '/etc/preinit': No such file or directory
mount: mounting proc on /proc failed: Device or resource busy
mount: mounting tmpfs on /run failed: No such file or directory
hostname: can't open '/etc/hostname': No such file or directory
------run rc.preboot file-----
UBIFS (ubi0:8): Mounting in unauthenticated mode
UBIFS (ubi0:8): background thread "ubifs_bgt0_8" started, PID 119
UBIFS (ubi0:8): recovery needed
UBIFS (ubi0:8): recovery completed
UBIFS (ubi0:8): UBIFS: mounted UBI device 0, volume 8, name "UDISK"
UBIFS (ubi0:8): LEB size: 258048 bytes (252 KiB), min./max. I/O unit sizes: 4096 bytes/4096 bytes
UBIFS (ubi0:8): FS size: 47738880 bytes (45 MiB, 185 LEBs), journal size 2322432 bytes (2 MiB, 9 LEBs)
UBIFS (ubi0:8): reserved for root: 2254825 bytes (2201 KiB)
UBIFS (ubi0:8): media format: w5/r0 (latest is w5/r0), UUID 26DCDA98-CAB6-4A6D-B43F-4EC2345931D8, small LPT model
------run rc.modules file-----
usbcore: registered new interface driver usb-storage
sunxi_gpadc_init,2151, success
sunxi_gpadc_setup: get channel scan data failed
input: sunxi-gpadc0 as /devices/virtual/input/input2


sunxi-rfkill soc@3000000:rfkill@0: wlan power on success
sunxi-rfkill soc@3000000:rfkill@0: bus_index: 1
Successfully initialized wpa_supplicant
------run rc.final file-----
numid=30,iface=MIXER,name='Headphone Switch'
  ; type=BOOLEAN,access=rw------,values=1
  : values=on
file system registered
configfs-gadget 4100000.udc-controller: failed to start g1: -19
sh: write error: No such device
read descriptors
read strings

insmod_host_driver

[ehci0-controller]: sunxi_usb_enable_ehci
[sunxi-ehci0]: probe, pdev->name: 4101000.ehci0-controller, sunxi_ehci: 0xffffffe00079b230, 0x:ffffffd0040f4000, irq_no:2e
sunxi-ehci 4101000.ehci0-controller: 4101000.ehci0-controller supply hci not found, using dummy regulator
sunxi-ehci 4101000.ehci0-controller: EHCI Host Controller
sunxi-ehci 4101000.ehci0-controller: new USB bus registered, assigned bus number 3
sunxi-ehci 4101000.ehci0-controller: irq 46, io mem 0x04101000
sunxi-ehci 4101000.ehci0-controller: USB 2.0 started, EHCI 1.00
hub 3-0:1.0: USB hub found
hub 3-0:1.0: 1 port detected
[ohci0-controller]: sunxi_usb_enable_ohci
[sunxi-ohci0]: probe, pdev->name: 4101400.ohci0-controller, sunxi_ohci: 0xffffffe00079b5f8
sunxi-ohci 4101400.ohci0-controller: 4101400.ohci0-controller supply hci not found, using dummy regulator
sunxi-ohci 4101400.ohci0-controller: OHCI Host Controller
sunxi-ohci 4101400.ohci0-controller: new USB bus registered, assigned bus number 4
sunxi-ohci 4101400.ohci0-controller: irq 47, io mem 0x04101400
hub 4-0:1.0: USB hub found
hub 4-0:1.0: 1 port detected
host_chose finished!
IPv6: ADDRCONF(NETDEV_CHANGE): wlan0: link becomes ready


BusyBox v1.27.2 () built-in shell (ash)

------run profile file-----
nice: can't execute '/usr/bin/story_bin': No such file or directory
 _____  _              __     _
|_   _||_| ___  _ _   |  |   |_| ___  _ _  _ _
  | |   _ |   ||   |  |  |__ | ||   || | ||_'_|
  | |  | || | || _ |  |_____||_||_|_||___||_,_|
  |_|  |_||_|_||_|_|  Tina is Based on OpenWrt!
 ----------------------------------------------
 Tina Linux (Neptune, 61CC0487)
 ----------------------------------------------
root@TinaLinux:/#

shz18877605430

T113跑bluez，bluetoothctl命令行操作的时候，手机能搜索到蓝牙，但是连接的时候一直连接不上，

大致流程如下操作：

/etc/init.d/dbus start
echo 0 > /sys/class/rfkill/rfkill0/state
echo 1 > /sys/class/rfkill/rfkill0/state
rtk_hciattach -n -s 115200 ttyS1 rtk_h5 & 	
hciconfig hci0 up
bluetoothd -C &
bluetoothctl
    ---->power on               //打开电源
    ---->discoverable on     //打开可发现
    ---->menu adv
         ---->name qq123      //设置蓝牙名字：qq123
         ---->back
    ---->advertise on           //广播

然后使用手机端的nrf connect助手搜索蓝牙，然后点击连接，但是连接不上，超时。

各位大佬，支支招！！！

shz18877605430

@yunchawaishi 改一下dclk的屏幕，改到24Mhz，你现在肯定是48Mhz

shz18877605430

1、前序

前几天，买了个显示屏，5寸的RGB（800*480），遇到了个奇葩的问题，用了芒果的F133（MQ-R）板子，然后开启了lvgl的demo程序，发现屏幕整体图像很淡，有抖动波纹，有种撕裂的感觉，不信你看。可能不是很清晰，如下：

fe38c654-be68-4624-bcd3-4ca028bc165f-2D13F840CE14A7DBEBF4D6BB2B56EDC6.jpg

2、过程

当时出现了这个问题的时候，我首先看了设备树，发现设备树该改的都改了呀，也没看出啥毛病，然后一直在哪里乱调，群里问了大佬，得到了一点点的灵感，看来还是要上RGB显示屏的手册才行，如下图所示。

接着对着手册改，发现改了也没用，然后用了示波器测量dclk，发现时钟频率是48Mhz,哇，这么嗨高，手册显示最高也就27Mhz，以是我想了想，要不把频率降下来看看，然后打了两个补丁：

0001-disp-support-dynamic-adjust-tcon_div.patch：
    放置到 lichee/linux-5.4 目录中执行 
    git apply 0001-disp-support-dynamic-adjust-tcon_div.patch

0001-disp-support-dynamic-adjust-tcon_div-uboot.patch：
    放置到 lichee/brandy-2.0/u-boot-2018 目录中执行 
    git apply 0001-disp-support-dynamic-adjust-tcon_div-uboot.patch

补丁在这个全志服务平台上：https://open.allwinnertech.com/#/sdk/0?menuID=36

如图所示：

接着依旧于事无补，没用啊，算了，打了补丁就不管了，过了两天，带着板子到公司的示波器上测测波形，靠，还是48Mhz，无语，只能看看有没有同步吧，接着在uboot命令行下用了fdt print命令看了一下设备树的参数，发现和内核的设备树一样，这下扯淡了，证明改的设备树内啥问题啊，都更新进去了，于是我还是不死心，坚决拿uboot的设备树开刀，改成了和内核的参数一样，烧录进去，啪，示波器测量，24Mhz，成了。没了，请看下一集。

贴图贴图，收工。

贴个内核设备树（uboot也是一样的）上来给大家看看：

&lcd0 {
	lcd_used            = <1>;

	lcd_driver_name     = "default_lcd";
	lcd_backlight       = <50>;
	lcd_if              = <0>;

	lcd_x               = <800>;
	lcd_y               = <480>;
	lcd_width           = <108>;
	lcd_height          = <65>;
	lcd_dclk_freq       = <22>;

	lcd_pwm_used        = <1>;
	lcd_pwm_ch          = <9>;
	lcd_pwm_freq        = <50000>;
	lcd_pwm_pol         = <0>;
	lcd_pwm_max_limit   = <255>;
	
	lcd_hbp             = <12>;
	lcd_ht              = <816>;
	lcd_hspw            = <4>;
	lcd_vbp             = <12>;
	lcd_vt              = <496>;
	lcd_vspw            = <4>;

	lcd_lvds_if         = <0>;
	lcd_lvds_colordepth = <1>;
	lcd_lvds_mode       = <0>;
	lcd_frm             = <0>;
	lcd_io_phase        = <0x0000>;
	lcd_gamma_en        = <0>;
	lcd_bright_curve_en = <0>;
	lcd_cmap_en         = <0>;

	deu_mode            = <0>;
	lcdgamma4iep        = <22>;
	smart_color         = <90>;

	pinctrl-0 = <&rgb18_pins_a>;
	pinctrl-1 = <&rgb18_pins_b>;
};

// 记得改uboot的设备树，一定、一定、一定，重要的事情要说三遍！！！

shz18877605430

1、开了adb ,启动板子，然后使用命令：cat /sys/devices/platform/soc@3000000/soc@3000000:usbc0@0/usb_device
出现了截图中的第一个红框的现象。

2、重新给板子上电，在没有使用上面的命令，然后出现了截图中的第二个红框的现象。

各位大佬，求解！！！

shz18877605430

@whycan 已搞定，谢谢

shz18877605430

请问各位大佬，tina（F133）怎么开启adb功能。求指教！！1

shz18877605430

@whycan 晕哥，请问一下，uboot的命令行中没有load这个命令，加载不了mmc的内容。怎么办？

shz18877605430

@whycan 晕哥，就是想不用flash，换成SD卡启动，但是不懂改哪里才能从sd启动，我用的是licheepi的sdk。

shz18877605430

f1c200s怎么从SD启动，uboot、kernel、这个阶段需要怎么改呢，uboot我改了传参，发现uboot没阶段没起来，用的是uboot-2018.01。制作镜像用了这个工具“genimage”，然后用这个烧录工具“Win32DiskImager”。

shz18877605430

@shz18877605430 晕哥，不是说要更改uboot得.config吗？但是我没找到改分辨率得地方，现在还是用480*272得分辨率，uboot往内核传参的地方没找到。

shz18877605430

@whycan 有背光，其他的准备测一下。

shz18877605430

@whycan 我的7寸RGB已经转成40pin了，正点原子的7寸RGB

shz18877605430

@whycan lichepi nano的，uboot_2018.01 内核是4.15

shz18877605430

@shz18877605430 看了晕哥的评论说改uboot下的.config，但是没有找到设置分辨率的地方。

shz18877605430

tiny200（F1C200s）的板子，跑4.3寸RGB没问题，换成7寸RGB，什么显示也没有，需要更改什么呢？各位大佬，救救急。

shz18877605430

@whycan 那晕哥这个怎么改才能正确触摸？谢谢。

shz18877605430

@whycan 晕哥，电阻屏不能/dev/input/eventX?吗？

shz18877605430

@whycan 是的。

shz18877605430

@whycan ts_uinput 转换是什么意思呢？有点不太懂，晕哥指点一下，谢谢。

shz18877605430

@whycan 用tslib-触摸屏校准的./ts_test是可以点击的，会不会是我的LVGL没弄好？

shz18877605430

@whycan 晕哥，校准屏幕的时候，发现发现坐标不对，请问是怎么回事呢？

shz18877605430

最近再调试f1c200s的板子，运行LVGL，触摸屏触摸的时候，基本整个屏幕都不能触摸，唯独最左边的一点点地方是可以触摸的，而且位置也不对，驱动是有的，就是触摸的时候出现触摸不了。不知道是不是没校准屏幕，屏幕是480*272的4.3寸RGB。驱动芯片是ns2009。求解！！！

shz18877605430

@yuzukitsuru 怎么换？？请指教。

shz18877605430

@yuzukitsuru 知道怎么解决吗？大佬

shz18877605430

@whycan 只要去掉了158的中断号那句就能编译。已经试过了。

shz18877605430

@whycan 可以的

shz18877605430

@whycan 在 f1c200s 触摸屏问题中说：

哪个地方有语法错误，会不会弄错dts文件

这个设备树文件

shz18877605430

@whycan 没错，就只有这个设备树文件，一直都是这个

shz18877605430

最近再f1c200s（tiny200的板子 r3）上添加触摸屏驱动的时候遇到了奇怪的问题，用着晕哥的内核设备树，一样的设备节点，但是我编译的时候直接解析不了，内核的menuconfig也打开了驱动。奇怪。而且我还专门看了示范文档，也是这么写的，报错的地方在中断号的地方（interrupts = <4 12 IRQ_TYPE_EDGE_FALLING>;）。欢迎各位大佬来救救菜鸡吧，如图所示。

shz18877605430

@whycan 我想烧录32M flash的后16M（起始地址是0x1000000）的空间,因为sunix-fel烧录的话，会直接覆盖前16M的分区，导致板子直接起不来，连uboot都没起来。所以我换了XFEL，但是XFEL不支持，如果要烧录后16M，请问需要怎么改呢？谢谢。

shz18877605430

最近使用XFEL进行烧录程序，烧录华邦32M的nor flash，发现接上去，烧录的时候，说不支持，有没有遇到过这种问题的兄弟们，或者说是XFEL本身就不支持，欢迎大家来回答。

shz18877605430 发布的帖子

1、前序

2、过程