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    麻雀D1s ,编译了新的Tina_d1_open_v2,选择了D1S,用TF卡烧录,启动时候卡住了,挂载不了文件系统,各位大神帮忙看下

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      daMing123 LV 5 最后由 YuzukiTsuru 编辑

      [170]HELLO! BOOT0 is starting!
      [173]BOOT0 commit : 88480af
      [175]set pll start
      [177]fix vccio detect value:0xc0
      [180]periph0 has been enabled
      [183]set pll end
      [185][pmu]: bus read error
      [188]board init ok
      [189]ZQ value = 0x30
      [191]get_pmu_exist() = -1
      [194]ddr_efuse_type: 0xa
      [196]trefi:7.8ms
      [198][AUTO DEBUG] single rank and full DQ!
      [202]ddr_efuse_type: 0xa
      [205]trefi:7.8ms
      [207][AUTO DEBUG] rank 0 row = 13 
      [210][AUTO DEBUG] rank 0 bank = 4 
      [213][AUTO DEBUG] rank 0 page size = 2 KB 
      [217]DRAM BOOT DRIVE INFO: V0.33
      [220]DRAM CLK = 528 MHz
      [222]DRAM Type = 2 (2:DDR2,3:DDR3)
      [225]DRAMC read ODT  off.
      [228]DRAM ODT off.
      [230]ddr_efuse_type: 0xa
      [233]DRAM SIZE =64 M
      [234]dram_tpr4:0x0
      [236]PLL_DDR_CTRL_REG:0xf8002b00
      [239]DRAM_CLK_REG:0xc0000000
      [242][TIMING DEBUG] MR2= 0x0
      [246]DRAM simple test OK.
      [249]dram size =64
      [250]card no is 0
      [252]sdcard 0 line count 4
      [255][mmc]: mmc driver ver 2021-04-2 16:45
      [264][mmc]: Wrong media type 0x0
      [267][mmc]: ***Try SD card 0***
      [277][mmc]: HSSDR52/SDR25 4 bit
      [280][mmc]: 50000000 Hz
      [282][mmc]: 7681 MB
      [284][mmc]: ***SD/MMC 0 init OK!!!***
      [335]Loading boot-pkg Succeed(index=0).
      [338]Entry_name        = opensbi
      [341]Entry_name        = u-boot
      [345]Entry_name        = dtb
      [348]mmc not para
      
      U-Boot 2018.05-g24521d6-dirty-config-dirty (Mar 30 2022 - 15:25:54 +0800) Allwinner Technology
      
      [00.361]DRAM:  64 MiB
      [00.363]Relocation Offset is: 01eed000
      [00.367]secure enable bit: 0
      [00.370]CPU=720 MHz,PLL6=600 Mhz,AHB=200 Mhz, APB1=100Mhz  MBus=300Mhz
      [00.377]flash init start
      [00.379]workmode = 0,storage type = 1
      [00.382][mmc]: mmc driver ver uboot2018:2021-11-19 15:38:00
      [00.388][mmc]: get sdc_type fail and use default host:tm1.
      [00.394][mmc]: can't find node "mmc0",will add new node
      [00.399][mmc]: fdt err returned <no error>
      [00.403][mmc]: Using default timing para
      [00.407][mmc]: SUNXI SDMMC Controller Version:0x50310
      [00.425][mmc]: card_caps:0x3000000a
      [00.428][mmc]: host_caps:0x3000003f
      [00.433]sunxi flash init ok
      [00.435]line:703 init_clocks
      [00.438]drv_disp_init
      request pwm success, pwm7:pwm7:0x2000c00.
      [00.459]drv_disp_init finish
      [00.461]boot_gui_init:start
      [00.465]set disp.dev2_output_type fail. using defval=0
      [00.471]boot_gui_init:finish
      partno erro : can't find partition bootloader
      54 bytes read in 2 ms (26.4 KiB/s)
      [00.510]bmp_name=bootlogo.bmp size 38454
      38454 bytes read in 5 ms (7.3 MiB/s)
      [00.551]Loading Environment from SUNXI_FLASH... OK
      [00.575]out of usb burn from boot: not need burn key
      [00.610]Item0 (Map) magic is bad
      [00.613]the secure storage item0 copy0 magic is bad
      [00.648]Item0 (Map) magic is bad
      [00.[00.653]LCD open finish
      651]the secure storage item0 copy1 magic is bad
      [00.659]Item0 (Map) magic is bad
      partno erro : can't find partition private
      root_partition is rootfs
      set root to /dev/mmcblk0p5
      [00.675]update part info
      [00.680]update bootcmd
      [00.685]change working_fdt 0x42aacda0 to 0x42a8cda0
      disable nand error: FDT_ERR_BADPATH
      No reserved memory region found in source FDT
      [00.725]update dts
      noncached_alloc(): addr = 0x42c90080
      noncached_alloc(): addr = 0x42c900c0
      noncached_alloc(): addr = 0x42c90100
      noncached_alloc(): addr = 0x42c90940
      geth_sys_init:634: get node 'gmac0' error
      geth_sys_init fail!
      [00.745]Board Net Initialization Failed
      [00.749]No ethernet found.
      Hit any key to stop autoboot:  0 
      [02.075]no vendor_boot partition is found
      Android's image name: d1s-nezha
      Detect comp none
      [02.092]
      Starting kernel ...
      
      [02.095][mmc]: MMC Device 2 not found
      [02.099][mmc]: mmc 2 not find, so not exit
      Linux version 5.4.61 (kim@kimpc) (riscv64-unknown-linux-gnu-gcc (C-SKY RISCV Tools V1.8.4 B20200702) 8.1.0, GNU ld (GNU Binutils) 2.32) #15 PREEMPT Wed Mar 30 07:41:58 UTC 2022
      Zone ranges:
        DMA32    [mem 0x0000000040000000-0x0000000043ffffff]
        Normal   empty
      Movable zone start for each node
      Early memory node ranges
        node   0: [mem 0x0000000040000000-0x0000000043ffffff]
      Initmem setup node 0 [mem 0x0000000040000000-0x0000000043ffffff]
      On node 0 totalpages: 16384
        DMA32 zone: 224 pages used for memmap
        DMA32 zone: 0 pages reserved
        DMA32 zone: 16384 pages, LIFO batch:3
      elf_hwcap is 0x20112d
      pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768
      pcpu-alloc: [0] 0 
      Built 1 zonelists, mobility grouping on.  Total pages: 16160
      Kernel command line: earlyprintk=sunxi-uart,0x02500000 clk_ignore_unused initcall_debug=0 console=ttyS0,115200 loglevel=8 root=/dev/mmcblk0p5 init=/pseudo_init partitions=boot-resource@mmcblk0p1:env@mmcblk0p2:env-redund@mmcblk0p3:boot@mmcblk0p4:rootfs@mmcblk0p5:recovery@mmcblk0p6:rootfs_data@mmcblk0p7:UDISK@mmcblk0p8 cma=0M snum= mac_addr= wifi_mac= bt_mac= specialstr= gpt=1 androidboot.mode=normal androidboot.hardware=sun20iw1p1 boot_type=1 androidboot.boot_type=1 gpt=1 uboot_message=2018.05-g24521d6-dirty-config-dirty(03/30/
      Dentry cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
      Inode-cache hash table entries: 4096 (order: 3, 32768 bytes, linear)
      Sorting __ex_table...
      mem auto-init: stack:off, heap alloc:off, heap free:off
      Memory: 55284K/65536K available (4654K kernel code, 402K rwdata, 1776K rodata, 144K init, 231K bss, 10252K reserved, 0K cma-reserved)
      SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
      rcu: Preemptible hierarchical RCU implementation.
              Tasks RCU enabled.
      rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
      NR_IRQS: 0, nr_irqs: 0, preallocated irqs: 0
      plic: mapped 200 interrupts with 1 handlers for 2 contexts.
      riscv_timer_init_dt: Registering clocksource cpuid [0] hartid [0]
      clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x588fe9dc0, max_idle_ns: 440795202592 ns
      sched_clock: 64 bits at 24MHz, resolution 41ns, wraps every 4398046511097ns
      riscv_timer_clockevent depends on broadcast, but no broadcast function available
      clocksource: timer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
      Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=240000)
      pid_max: default: 32768 minimum: 301
      Mount-cache hash table entries: 512 (order: 0, 4096 bytes, linear)
      Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes, linear)
      ASID allocator initialised with 65536 entries
      rcu: Hierarchical SRCU implementation.
      devtmpfs: initialized
      random: get_random_u32 called from bucket_table_alloc.isra.27+0x10a/0x12c with crng_init=0
      clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
      futex hash table entries: 256 (order: 0, 6144 bytes, linear)
      pinctrl core: initialized pinctrl subsystem
      NET: Registered protocol family 16
      DMA: preallocated 256 KiB pool for atomic allocations
      cpuidle: using governor menu
      rtc_ccu: sunxi ccu init OK
      clock: sunxi ccu init OK
      clock: sunxi ccu init OK
      iommu: Default domain type: Translated 
      sunxi iommu: irq = 4
      SCSI subsystem initialized
      usbcore: registered new interface driver usbfs
      usbcore: registered new interface driver hub
      usbcore: registered new device driver usb
      videodev: Linux video capture interface: v2.00
      Advanced Linux Sound Architecture Driver Initialized.
      pwm module init!
      g2d 5410000.g2d: Adding to iommu group 0
      G2D: rcq version initialized.major:252
      clocksource: Switched to clocksource riscv_clocksource
      sun8iw20-pinctrl 2000000.pinctrl: initialized sunXi PIO driver
      NET: Registered protocol family 2
      tcp_listen_portaddr_hash hash table entries: 256 (order: 0, 4096 bytes, linear)
      TCP established hash table entries: 512 (order: 0, 4096 bytes, linear)
      TCP bind hash table entries: 512 (order: 0, 4096 bytes, linear)
      TCP: Hash tables configured (established 512 bind 512)
      UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
      UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
      NET: Registered protocol family 1
      sun8iw20-pinctrl 2000000.pinctrl: 2000000.pinctrl supply vcc-pc not found, using dummy regulator
      spi spi0: spi0 supply spi not found, using dummy regulator
      sunxi_spi_resource_get()2151 - [spi0] SPI MASTER MODE
      sunxi_spi_resource_get()2189 - Failed to get sample mode
      sunxi_spi_resource_get()2194 - Failed to get sample delay
      sunxi_spi_resource_get()2198 - sample_mode:-1431633921 sample_delay:-1431633921
      sunxi_spi_clk_init()2240 - [spi0] mclk 100000000
      sunxi_spi_probe()2653 - [spi0]: driver probe succeed, base ffffffd004058000, irq 31
      workingset: timestamp_bits=62 max_order=14 bucket_order=0
      squashfs: version 4.0 (2009/01/31) Phillip Lougher
      ntfs: driver 2.1.32 [Flags: R/W].
      jffs2: version 2.2. (NAND) (SUMMARY)  © 2001-2006 Red Hat, Inc.
      io scheduler mq-deadline registered
      io scheduler kyber registered
      [DISP]disp_module_init
      disp 5000000.disp: Adding to iommu group 0
      [DISP] parser_disp_init_para,line:1430:
      of_property_read fb0_width fail
      [DISP] disp_init,line:2386:
      smooth display screen:0 type:1 mode:4
      display_fb_request,fb_id:0
      Freeing logo buffer memory: 1500K
      disp_al_manager_apply ouput_type:1
      sun8iw20-pinctrl 2000000.pinctrl: 2000000.pinctrl supply vcc-pd not found, using dummy regulator
      [DISP]disp_module_init finish
      sunxi_sid_init()551 - insmod ok
      pwm-regulator: supplied by regulator-dummy
      uart uart0: get regulator failed
      uart uart0: uart0 supply uart not found, using dummy regulator
      uart0: ttyS0 at MMIO 0x2500000 (irq = 18, base_baud = 1500000) is a SUNXI
      sw_console_setup()1808 - console setup baud 115200 parity n bits 8, flow n
      printk: console [ttyS0] enabled
      misc dump reg init
      sun8iw20-pinctrl 2000000.pinctrl: 2000000.pinctrl supply vcc-pg not found, using dummy regulator
      sunxi-rfkill soc@3000000:rfkill@0: module version: v1.0.9
      sunxi-rfkill soc@3000000:rfkill@0: get gpio chip_en failed
      sunxi-rfkill soc@3000000:rfkill@0: get gpio power_en failed
      sunxi-rfkill soc@3000000:rfkill@0: wlan_busnum (1)
      sunxi-rfkill soc@3000000:rfkill@0: Missing wlan_power.
      sunxi-rfkill soc@3000000:rfkill@0: wlan clock[0] (32k-fanout1)
      sunxi-rfkill soc@3000000:rfkill@0: wlan_regon gpio=131 assert=1
      sun8iw20-pinctrl 2000000.pinctrl: 2000000.pinctrl supply vcc-pe not found, using dummy regulator
      sunxi-rfkill soc@3000000:rfkill@0: wlan_hostwake gpio=202 assert=1
      sunxi-rfkill soc@3000000:rfkill@0: wakeup source is enabled
      sunxi-rfkill soc@3000000:rfkill@0: Missing bt_power.
      sunxi-rfkill soc@3000000:rfkill@0: bt clock[0] (32k-fanout1)
      sunxi-rfkill soc@3000000:rfkill@0: bt_rst gpio=210 assert=0
      [ADDR_MGT] addr_mgt_probe: module version: v1.0.10
      [ADDR_MGT] addr_mgt_probe: success.
      sunxi-spinand: AW SPINand MTD Layer Version: 2.0 20201228
      sunxi-spinand-phy: AW SPINand Phy Layer Version: 1.10 20200306
      sunxi-spinand-phy: not detect any munufacture from id table
      sunxi-spinand-phy: get spi-nand Model from fdt fail
      sunxi-spinand-phy: get phy info from fdt fail
      sunxi-spinand-phy: not detect munufacture from fdt
      sunxi-spinand-phy: detect munufacture from id table: Winbond
      sunxi-spinand-phy: detect spinand id: ff21aaef ffffffff
      sunxi-spinand-phy: ========== arch info ==========
      sunxi-spinand-phy: Model:               W25N01GVZEIG
      sunxi-spinand-phy: Munufacture:         Winbond
      sunxi-spinand-phy: DieCntPerChip:       1
      sunxi-spinand-phy: BlkCntPerDie:        1024
      sunxi-spinand-phy: PageCntPerBlk:       64
      sunxi-spinand-phy: SectCntPerPage:      4
      sunxi-spinand-phy: OobSizePerPage:      64
      sunxi-spinand-phy: BadBlockFlag:        0x0
      sunxi-spinand-phy: OperationOpt:        0x7
      sunxi-spinand-phy: MaxEraseTimes:       65000
      sunxi-spinand-phy: EccFlag:             0x0
      sunxi-spinand-phy: EccType:             2
      sunxi-spinand-phy: EccProtectedType:    3
      sunxi-spinand-phy: ========================================
      sunxi-spinand-phy: 
      sunxi-spinand-phy: ========== physical info ==========
      sunxi-spinand-phy: TotalSize:    128 M
      sunxi-spinand-phy: SectorSize:   512 B
      sunxi-spinand-phy: PageSize:     2 K
      sunxi-spinand-phy: BlockSize:    128 K
      sunxi-spinand-phy: OOBSize:      64 B
      sunxi-spinand-phy: ========================================
      sunxi-spinand-phy: 
      sunxi-spinand-phy: ========== logical info ==========
      sunxi-spinand-phy: TotalSize:    128 M
      sunxi-spinand-phy: SectorSize:   512 B
      sunxi-spinand-phy: PageSize:     4 K
      sunxi-spinand-phy: BlockSize:    256 K
      sunxi-spinand-phy: OOBSize:      128 B
      sunxi-spinand-phy: ========================================
      sunxi-spinand-phy: W25N01GVZEIG reset rx bit width to 1
      sunxi-spinand-phy: W25N01GVZEIG reset tx bit width to 1
      sunxi-spinand-phy: block lock register: 0x00
      sunxi-spinand-phy: feature register: 0x19
      sunxi-spinand-phy: sunxi physic nand init end
      Creating 4 MTD partitions on "sunxi_mtd_nand":
      0x000000000000-0x000000100000 : "boot0"
      0x000000100000-0x000000500000 : "uboot"
      random: fast init done
      0x000000500000-0x000000600000 : "secure_storage"
      0x000000600000-0x000008000000 : "sys"
      sunxi-spinand-phy: phy blk 477 is bad
      sunxi-spinand-phy: phy blk 478 is bad
      sunxi-spinand-phy: phy blk 480 is bad
      sunxi-spinand-phy: phy blk 482 is bad
      sunxi-spinand-phy: phy blk 484 is bad
      sunxi-spinand-phy: phy blk 486 is bad
      sunxi-spinand-phy: phy blk 488 is bad
      sunxi-spinand-phy: phy blk 490 is bad
      sunxi-spinand-phy: phy blk 492 is bad
      sunxi-spinand-phy: phy blk 494 is bad
      sunxi-spinand-phy: phy blk 496 is bad
      sunxi-spinand-phy: ecc error 0x2
      sunxi-spinand-phy: phy blk 580 is bad
      sunxi-spinand-phy: ecc error 0x2
      sunxi-spinand-phy: phy blk 582 is bad
      sunxi-spinand-phy: ecc error 0x2
      sunxi-spinand-phy: phy blk 584 is bad
      sunxi-spinand-phy: ecc error 0x2
      sunxi-spinand-phy: phy blk 586 is bad
      sunxi-spinand-phy: phy blk 588 is bad
      sunxi-spinand-phy: phy blk 590 is bad
      sunxi-spinand-phy: phy blk 593 is bad
      sunxi-spinand-phy: phy blk 594 is bad
      sunxi-spinand-phy: phy blk 596 is bad
      sunxi-spinand-phy: phy blk 598 is bad
      sunxi-spinand-phy: phy blk 602 is bad
      sunxi-spinand-phy: phy blk 605 is bad
      sunxi-spinand-phy: phy blk 606 is bad
      sunxi-spinand-phy: phy blk 608 is bad
      sunxi-spinand-phy: phy blk 610 is bad
      sunxi-spinand-phy: phy blk 614 is bad
      sunxi-spinand-phy: phy blk 616 is bad
      sunxi-spinand-phy: phy blk 618 is bad
      sunxi-spinand-phy: phy blk 620 is bad
      sunxi-spinand-phy: phy blk 623 is bad
      sunxi-spinand-phy: phy blk 625 is bad
      sunxi-spinand-phy: phy blk 626 is bad
      sunxi-spinand-phy: phy blk 629 is bad
      sunxi-spinand-phy: phy blk 630 is bad
      sunxi-spinand-phy: phy blk 632 is bad
      sunxi-spinand-phy: phy blk 634 is bad
      sunxi-spinand-phy: phy blk 636 is bad
      sunxi-spinand-phy: phy blk 639 is bad
      sunxi-spinand-phy: phy blk 641 is bad
      sunxi-spinand-phy: phy blk 642 is bad
      sunxi-spinand-phy: phy blk 644 is bad
      sunxi-spinand-phy: phy blk 647 is bad
      sunxi-spinand-phy: phy blk 649 is bad
      sunxi-spinand-phy: phy blk 650 is bad
      sunxi-spinand-phy: phy blk 652 is bad
      sunxi-spinand-phy: phy blk 654 is bad
      sunxi-spinand-phy: phy blk 658 is bad
      sunxi-spinand-phy: phy blk 661 is bad
      sunxi-spinand-phy: phy blk 669 is bad
      sunxi-spinand-phy: phy blk 670 is bad
      sunxi-spinand-phy: phy blk 672 is bad
      sunxi-spinand-phy: phy blk 674 is bad
      sunxi-spinand-phy: phy blk 681 is bad
      sunxi-spinand-phy: phy blk 682 is bad
      sunxi-spinand-phy: phy blk 688 is bad
      sunxi-spinand-phy: phy blk 692 is bad
      sunxi-spinand-phy: phy blk 695 is bad
      sunxi-spinand-phy: phy blk 696 is bad
      sunxi-spinand-phy: phy blk 698 is bad
      sunxi-spinand-phy: phy blk 700 is bad
      sunxi-spinand-phy: phy blk 702 is bad
      sunxi-spinand-phy: phy blk 704 is bad
      sunxi-spinand-phy: phy blk 709 is bad
      sunxi-spinand-phy: phy blk 713 is bad
      sunxi-spinand-phy: phy blk 714 is bad
      sunxi-spinand-phy: phy blk 719 is bad
      sunxi-spinand-phy: phy blk 721 is bad
      sunxi-spinand-phy: phy blk 723 is bad
      sunxi-spinand-phy: phy blk 725 is bad
      sunxi-spinand-phy: phy blk 726 is bad
      sunxi-spinand-phy: phy blk 730 is bad
      sunxi-spinand-phy: phy blk 732 is bad
      sunxi-spinand-phy: phy blk 734 is bad
      sunxi-spinand-phy: phy blk 737 is bad
      sunxi-spinand-phy: phy blk 738 is bad
      ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
      sunxi-ehci: EHCI SUNXI driver
      get ehci1-controller wakeup-source is fail.
      sunxi ehci1-controller don't init wakeup source
      [sunxi-ehci1]: probe, pdev->name: 4200000.ehci1-controller, sunxi_ehci: 0xffffffe0006face8, 0x:ffffffd00406f000, irq_no:31
      sunxi-ehci 4200000.ehci1-controller: 4200000.ehci1-controller supply drvvbus not found, using dummy regulator
      sunxi-ehci 4200000.ehci1-controller: 4200000.ehci1-controller supply hci not found, using dummy regulator
      sunxi-ehci 4200000.ehci1-controller: EHCI Host Controller
      sunxi-ehci 4200000.ehci1-controller: new USB bus registered, assigned bus number 1
      sunxi-ehci 4200000.ehci1-controller: irq 49, io mem 0x04200000
      sunxi-ehci 4200000.ehci1-controller: USB 2.0 started, EHCI 1.00
      hub 1-0:1.0: USB hub found
      hub 1-0:1.0: 1 port detected
      ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
      sunxi-ohci: OHCI SUNXI driver
      get ohci1-controller wakeup-source is fail.
      sunxi ohci1-controller don't init wakeup source
      [sunxi-ohci1]: probe, pdev->name: 4200400.ohci1-controller, sunxi_ohci: 0xffffffe0006fb0b0
      sunxi-ohci 4200400.ohci1-controller: 4200400.ohci1-controller supply drvvbus not found, using dummy regulator
      sunxi-ohci 4200400.ohci1-controller: 4200400.ohci1-controller supply hci not found, using dummy regulator
      sunxi-ohci 4200400.ohci1-controller: OHCI Host Controller
      sunxi-ohci 4200400.ohci1-controller: new USB bus registered, assigned bus number 2
      sunxi-ohci 4200400.ohci1-controller: irq 50, io mem 0x04200400
      hub 2-0:1.0: USB hub found
      hub 2-0:1.0: 1 port detected
      sunxi-rtc 7090000.rtc: errata__fix_alarm_day_reg_default_value(): ALARM0_DAY_REG=0, set it to 1
      sunxi-rtc 7090000.rtc: registered as rtc0
      sunxi-rtc 7090000.rtc: setting system clock to 1970-01-01T00:00:03 UTC (3)
      sunxi-rtc 7090000.rtc: sunxi rtc probed
      i2c /dev entries driver
      IR NEC protocol handler initialized
      uvcvideo: Unable to create debugfs directory
      usbcore: registered new interface driver uvcvideo
      USB Video Class driver (1.1.1)
      sunxi cedar version 1.1
      sunxi-cedar 1c0e000.ve: Adding to iommu group 0
      VE: install start!!!
      
      VE: cedar-ve the get irq is 6
      
      VE: install end!!!
      
      VE: sunxi_cedar_probe
      sun8iw20-pinctrl 2000000.pinctrl: pin PF2 already requested by 2500000.uart; cannot claim for 4020000.sdmmc
      sun8iw20-pinctrl 2000000.pinctrl: pin-162 (4020000.sdmmc) status -22
      sun8iw20-pinctrl 2000000.pinctrl: could not request pin 162 (PF2) from group PF2  on device 2000000.pinctrl
      sunxi-mmc 4020000.sdmmc: Error applying setting, reverse things back
      sunxi-mmc: probe of 4020000.sdmmc failed with error -22
      sunxi-mmc 4021000.sdmmc: SD/MMC/SDIO Host Controller Driver(v4.21 2021-11-18 10:02)
      sunxi-mmc 4021000.sdmmc: ***ctl-spec-caps*** 8
      sunxi-mmc 4021000.sdmmc: No vmmc regulator found
      sunxi-mmc 4021000.sdmmc: No vqmmc regulator found
      sunxi-mmc 4021000.sdmmc: No vdmmc regulator found
      sunxi-mmc 4021000.sdmmc: No vd33sw regulator found
      sunxi-mmc 4021000.sdmmc: No vd18sw regulator found
      sunxi-mmc 4021000.sdmmc: No vq33sw regulator found
      sunxi-mmc 4021000.sdmmc: No vq18sw regulator found
      sunxi-mmc 4021000.sdmmc: Cann't get pin bias hs pinstate,check if needed
      sunxi-mmc 4021000.sdmmc: sdc set ios:clk 0Hz bm PP pm UP vdd 21 width 1 timing LEGACY(SDR12) dt B
      sunxi-mmc 4021000.sdmmc: no vqmmc,Check if there is regulator
      sunxi-mmc 4021000.sdmmc: sdc set ios:clk 400000Hz bm PP pm ON vdd 21 width 1 timing LEGACY(SDR12) dt B
      sunxi-mmc 4021000.sdmmc: detmode:manually by software
      ashmem: initialized
      exFAT: Version 1.3.0
      sunxi-mmc 4021000.sdmmc: sdc set ios:clk 400000Hz bm PP pm ON vdd 21 width 1 timing LEGACY(SDR12) dt B
      [AUDIOCODEC][sunxi_codec_parse_params][2412]:digital_vol:0, lineout_vol:26, mic1gain:31, mic2gain:31 pa_msleep:120, pa_level:1, pa_pwr_level:1
      
      [AUDIOCODEC][sunxi_codec_parse_params][2448]:adcdrc_cfg:0, adchpf_cfg:1, dacdrc_cfg:0, dachpf:0
      [AUDIOCODEC][sunxi_internal_codec_probe][2609]:codec probe finished
      sunxi-mmc 4021000.sdmmc: sdc set ios:clk 400000Hz bm PP pm ON vdd 21 width 1 timing LEGACY(SDR12) dt B
      sid_rd_ver_reg()254 - ver >= 4, soc ver:5
      [SNDCODEC][sunxi_card_init][583]:card init finished
      sunxi-codec-machine 2030340.sound: 2030000.codec <-> 203034c.dummy_cpudai mapping ok
      input: audiocodec sunxi Audio Jack as /devices/platform/soc@3000000/2030340.sound/sound/card0/input0
      [SNDCODEC][sunxi_card_dev_probe][836]:register card finished
      NET: Registered protocol family 10
      [SNDCODEC][sunxi_hs_init_work][259]:resume-->report switch
      sunxi-mmc 4021000.sdmmc: sdc set ios:clk 400000Hz bm PP pm ON vdd 21 width 1 timing SD-HS(SDR25) dt B
      Segment Routing with IPv6
      NET: Registered protocol family 17
      sunxi-mmc 4021000.sdmmc: sdc set ios:clk 50000000Hz bm PP pm ON vdd 21 width 1 timing SD-HS(SDR25) dt B
      sunxi-i2c sunxi-i2c2: sunxi-i2c2 supply twi not found, using dummy regulator
      sunxi-mmc 4021000.sdmmc: sdc set ios:clk 50000000Hz bm PP pm ON vdd 21 width 4 timing SD-HS(SDR25) dt B
      sunxi-i2c sunxi-i2c2: probe success
      mmc0: new high speed SDIO card at address 0001
      sun8iw20-pinctrl 2000000.pinctrl: pin PF2 already requested by 2500000.uart; cannot claim for 4020000.sdmmc
      sun8iw20-pinctrl 2000000.pinctrl: pin-162 (4020000.sdmmc) status -22
      sun8iw20-pinctrl 2000000.pinctrl: could not request pin 162 (PF2) from group PF2  on device 2000000.pinctrl
      sunxi-mmc 4020000.sdmmc: Error applying setting, reverse things back
      sunxi-mmc: probe of 4020000.sdmmc failed with error -22
      sun8iw20-pinctrl 2000000.pinctrl: 2000000.pinctrl supply vcc-pb not found, using dummy regulator
      get ehci0-controller wakeup-source is fail.
      sunxi ehci0-controller don't init wakeup source
      [sunxi-ehci0]: probe, pdev->name: 4101000.ehci0-controller, sunxi_ehci: 0xffffffe0006fa558, 0x:ffffffd0040fe000, irq_no:2e
      [sunxi-ehci0]: Not init ehci0
      get ohci0-controller wakeup-source is fail.
      sunxi ohci0-controller don't init wakeup source
      [sunxi-ohci0]: probe, pdev->name: 4101400.ohci0-controller, sunxi_ohci: 0xffffffe0006fa920
      [sunxi-ohci0]: Not init ohci0
      clk: Not disabling unused clocks
      platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
      ALSA device list:
        #0: audiocodec
      alloc_fd: slot 0 not NULL!
      VFS: Cannot open root device "mmcblk0p5" or unknown-block(0,0): error -6
      cfg80211: failed to load regulatory.db
      Please append a correct "root=" boot option; here are the available partitions:
      1f00            1024 mtdblock0 
       (driver?)
      1f01            4096 mtdblock1 
       (driver?)
      1f02            1024 mtdblock2 
       (driver?)
      1f03          124928 mtdblock3 
       (driver?)
      Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)
      CPU: 0 PID: 1 Comm: swapper Not tainted 5.4.61 #15
      Call Trace:
      [<ffffffe000026130>] walk_stackframe+0x0/0x98
      [<ffffffe0000262e8>] show_stack+0x2a/0x34
      [<ffffffe00049986e>] dump_stack+0x20/0x28
      [<ffffffe00002a6f0>] panic+0xec/0x272
      [<ffffffe000000ef6>] mount_block_root+0x214/0x27a
      [<ffffffe000000fe2>] mount_root+0x86/0x90
      [<ffffffe000001134>] prepare_namespace+0x148/0x152
      [<ffffffe000000b58>] kernel_init_freeable+0x166/0x198
      [<ffffffe0004aa420>] kernel_init+0x12/0xee
      [<ffffffe000024e9c>] ret_from_exception+0x0/0xc
      ---[ end Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0) ]---
      
      1 条回复 最后回复 回复 引用 分享 0
      • YuzukiTsuru
        柚木 鉉 LV 9 最后由 YuzukiTsuru 编辑

        默认是mtd设备也就是spi flash 启动

        修改
        device/config/chips/d1-h/configs/nezha/sys_config.fex

        ;----------------------------------------------------------------------------------
        ;storage_type   = boot medium, 0-nand, 1-sd, 2-emmc, 3-nor, 4-emmc3, 5-spinand -1(defualt)auto scan
        ;----------------------------------------------------------------------------------
        [target]
        storage_type    = 1
        ···
        D 1 条回复 最后回复 回复 引用 分享 0
        • D
          daMing123 LV 5 @YuzukiTsuru 最后由 编辑

          @yuzukitsuru 这里我已经 改成 storage_type = 1 ,一样的启动,就算改成5,用spinand,一样的卡死在这里,不知道为什么 。

          1 条回复 最后回复 回复 引用 分享 0
          • YuzukiTsuru
            柚木 鉉 LV 9 最后由 YuzukiTsuru 编辑

            @daming123 设备树也要改一下

            board.dts

            /*
             * Allwinner Technology CO., Ltd. sun20iw1p1 fpga.
             *
             * fpga support.
             */
            
            /dts-v1/;
            
            /memreserve/ 0x42000000 0x100000;  /* dsp used 1MB */
            #include "sun20iw1p1.dtsi"
            
            /{
            	compatible = "allwinner,d1-h", "arm,sun20iw1p1", "allwinner,sun20iw1p1";
            
            	aliases {
            		dsp0 = &dsp0;
            		dsp0_gpio_int= &dsp0_gpio_int;
            		gmac0 = &gmac0;
            	};
            
            	dsp0: dsp0 {
            		compatible = "allwinner,sun20iw1-dsp";
            		status = "okay";
            	};
            
            	dsp0_gpio_int: dsp0_gpio_int {
            		compatible = "allwinner,sun20iw1-dsp-gpio-int";
            		pin-group = "PB", "PC", "PD", "PE";
            		status = "disabled";
            	};
            
            	reg_vdd_cpu: vdd-cpu {
            		compatible = "sunxi-pwm-regulator";
            		pwms = <&pwm 0 5000 1>;
            		regulator-name = "vdd_cpu";
            		regulator-min-microvolt = <810000>;
            		regulator-max-microvolt = <1160000>;
            		regulator-ramp-delay = <25>;
            		regulator-always-on;
            		regulator-boot-on;
            		status = "okay";
            	};
            
            	reg_usb1_vbus: usb1-vbus {
            		compatible = "regulator-fixed";
            		regulator-name = "usb1-vbus";
            		regulator-min-microvolt = <5000000>;
            		regulator-max-microvolt = <5000000>;
            		regulator-enable-ramp-delay = <1000>;
            		gpio = <&pio PD 19 GPIO_ACTIVE_HIGH>;
            		enable-active-high;
            	};
            };
            
            &CPU0 {
            	cpu-supply = <&reg_vdd_cpu>;
            };
            
            &pio {
            	sdc0_pins_a: sdc0@0 {
            		allwinner,pins = "PF0", "PF1", "PF2",
            				 "PF3", "PF4", "PF5";
            		allwinner,function = "sdc0";
            		allwinner,muxsel = <2>;
            		allwinner,drive = <3>;
            		allwinner,pull = <1>;
            		pins = "PF0", "PF1", "PF2",
            		       "PF3", "PF4", "PF5";
            		function = "sdc0";
            		drive-strength = <30>;
            		bias-pull-up;
            		power-source = <3300>;
            	};
            
            
            	sdc0_pins_b: sdc0@1 {
            		pins = "PF0", "PF1", "PF2",
            		       "PF3", "PF4", "PF5";
            		function = "sdc0";
            		drive-strength = <30>;
            		bias-pull-up;
            		power-source = <1800>;
            	};
            
            	sdc0_pins_c: sdc0@2 {
            		pins = "PF0", "PF1", "PF2",
            			"PF3", "PF4", "PF5";
            		function = "gpio_in";
            	};
            
            	/* TODO: add jtag pin */
            	sdc0_pins_d: sdc0@3 {
            		pins = "PF2", "PF4";
            		function = "uart0";
            		drive-strength = <10>;
            		bias-pull-up;
            	};
            
            	sdc0_pins_e: sdc0@4 {
            		pins = "PF0", "PF1", "PF3",
            			"PF5";
            		function = "jtag";
            		drive-strength = <10>;
            		bias-pull-up;
            	};
            
            
            	sdc1_pins_a: sdc1@0 {
            		pins = "PG0", "PG1", "PG2",
            		       "PG3", "PG4", "PG5";
            		function = "sdc1";
            		drive-strength = <30>;
            		bias-pull-up;
            	};
            
            	sdc1_pins_b: sdc1@1 {
            		pins = "PG0", "PG1", "PG2",
            		       "PG3", "PG4", "PG5";
            			function = "gpio_in";
            	};
            
            	sdc2_pins_a: sdc2@0 {
            		allwinner,pins = "PC2", "PC3", "PC4",
            				 "PC5", "PC6", "PC7";
            		allwinner,function = "sdc2";
            		allwinner,muxsel = <3>;
            		allwinner,drive = <3>;
            		allwinner,pull = <1>;
            		pins = "PC2", "PC3", "PC4",
            			"PC5", "PC6", "PC7";
            		function = "sdc2";
            		drive-strength = <30>;
            		bias-pull-up;
            	};
            
            	sdc2_pins_b: sdc2@1 {
            		pins = "PC2", "PC3", "PC4",
            		       "PC5", "PC6", "PC7";
            		function = "gpio_in";
            	};
            
            	wlan_pins_a:wlan@0 {
            		pins = "PG11";
            		function = "clk_fanout1";
            	};
            
            	uart0_pins_a: uart0_pins@0 {  /* For nezha board */
            		pins = "PB8", "PB9";
            		function = "uart0";
            		drive-strength = <10>;
            		bias-pull-up;
            	};
            
            	uart0_pins_b: uart0_pins@1 {  /* For nezha board */
            		pins = "PB8", "PB9";
            		function = "gpio_in";
            	};
            
            	uart1_pins_a: uart1_pins@0 {  /* For EVB1 board */
            		pins = "PG6", "PG7", "PG8", "PG9";
            		function = "uart1";
            		drive-strength = <10>;
            		bias-pull-up;
            	};
            
            	uart1_pins_b: uart1_pins {  /* For EVB1 board */
            		pins = "PG6", "PG7", "PG8", "PG9";
            		function = "gpio_in";
            	};
            
            	uart2_pins_a: uart2_pins@0 {  /* For EVB1 board */
            		pins = "PC0", "PC1";
            		function = "uart2";
            		drive-strength = <10>;
            		bias-pull-up;
            	};
            
            	uart2_pins_b: uart2_pins@1 {  /* For EVB1 board */
            		pins = "PC0", "PC1";
            		function = "gpio_in";
            	};
            
            	uart3_pins_a: uart3_pins@0 {  /* For EVB1 board */
            		pins = "PD10", "PD11";
            		function = "uart3";
            		muxsel = <5>;
            		drive-strength = <10>;
            		bias-pull-up;
            	};
            
            	twi0_pins_a: twi0@0 {
            		pins = "PB10", "PB11";	/*sck sda*/
            		function = "twi0";
            		drive-strength = <10>;
            	};
            
            	twi0_pins_b: twi0@1 {
            		pins = "PB10", "PB11";
            		function = "gpio_in";
            	};
            
            	twi1_pins_a: twi1@0 {
            		pins = "PB4", "PB5";
            		function = "twi1";
            		drive-strength = <10>;
            	};
            
            	twi1_pins_b: twi1@1 {
            		pins = "PB4", "PB5";
            		function = "gpio_in";
            	};
            
            	twi2_pins_a: twi2@0 {
            		pins = "PB0", "PB1";
            		function = "twi2";
            		drive-strength = <10>;
            	};
            
            	twi2_pins_b: twi2@1 {
            		pins = "PB0", "PB1";
            		function = "gpio_in";
            	};
            
            	twi3_pins_a: twi3@0 {
            		pins = "PB6", "PB7";
            		function = "twi3";
            		drive-strength = <10>;
            	};
            
            	twi3_pins_b: twi3@1 {
            		pins = "PB6", "PB7";
            		function = "gpio_in";
            	};
            
            	gmac_pins_a: gmac@0 {
            		pins = "PE0", "PE1", "PE2", "PE3",
            		       "PE4", "PE5", "PE6", "PE7",
            		       "PE8", "PE9", "PE10", "PE11",
            		       "PE12", "PE13", "PE14", "PE15";
            		function = "gmac0";
            		muxsel = <8>; /* for uboot driver */
            		drive-strength = <10>;
            	};
            
            	gmac_pins_b: gmac@1 {
            		pins = "PE0", "PE1", "PE2", "PE3",
            		       "PE4", "PE5", "PE6", "PE7",
            		       "PE8", "PE9", "PE10", "PE11",
            		       "PE12", "PE13", "PE14", "PE15";
            		function = "gpio_in";
            	};
            
            	dmic_pins_a: dmic@0 {
            		/* DMIC_PIN: CLK, DATA0, DATA1, DATA2 */
            		pins = "PE17", "PB11", "PB10", "PD17";
            		function = "dmic";
            		drive-strength = <20>;
            		bias-disable;
            	};
            
            	dmic_pins_b: dmic@1 {
            		pins = "PE17", "PB11", "PB10", "PD17";
            		function = "io_disabled";
            		drive-strength = <20>;
            		bias-disable;
            	};
            
            	daudio0_pins_a: daudio0@0 {
            		/* MCLK, BCLK, LRCK */
            		pins = "PE17", "PE16", "PE15";
            		function = "i2s0";
            		drive-strength = <20>;
            		bias-disable;
            	};
            
            	daudio0_pins_b: daudio0@1 {
            		/* DIN0 */
            		pins = "PE14";
            		function = "i2s0_din";
            		drive-strength = <20>;
            		bias-disable;
            	};
            
            	daudio0_pins_c: daudio0@2 {
            		/* DOUT0 */
            		pins = "PE13";
            		function = "i2s0_dout";
            		drive-strength = <20>;
            		bias-disable;
            	};
            
            	daudio0_pins_d: daudio0_sleep@0 {
            		pins = "PE17", "PE16", "PE15", "PE14", "PE13";
            		function = "io_disabled";
            		drive-strength = <20>;
            		bias-disable;
            	};
            
            	daudio1_pins_a: daudio1@0 {
            		/* MCLK, LRCK, BCLK */
            		pins = "PG11", "PG12", "PG13";
            		function = "i2s1";
            		drive-strength = <20>;
            		bias-disable;
            	};
            
            	daudio1_pins_b: daudio1@1 {
            		/* DIN0 */
            		pins = "PG14";
            		function = "i2s1_din";
            		drive-strength = <20>;
            		bias-disable;
            	};
            
            	daudio1_pins_c: daudio1@2 {
            		/* DOUT0 */
            		pins = "PG15";
            		function = "i2s1_dout";
            		drive-strength = <20>;
            		bias-disable;
            	};
            
            	daudio1_pins_d: daudio1_sleep@0 {
            		pins = "PG11", "PG12", "PG13", "PG14", "PG15";
            		function = "io_disabled";
            		drive-strength = <20>;
            		bias-disable;
            	};
            
            	daudio2_pins_a: daudio2@0 {
            		/* I2S_PIN: MCLK, BCLK, LRCK */
            		pins = "PB7", "PB5", "PB6";
            		function = "i2s2";
            		drive-strength = <20>;
            		bias-disable;
            	};
            
            	daudio2_pins_b: daudio2@1 {
            		/* I2S_PIN: DOUT0 */
            		pins = "PB4";
            		function = "i2s2_dout";
            		drive-strength = <20>;
            		bias-disable;
            	};
            
            	daudio2_pins_c: daudio2@2 {
            		/* I2S_PIN: DIN0 */
            		pins = "PB3";
            		function = "i2s2_din";
            		drive-strength = <20>;
            		bias-disable;
            	};
            
            	daudio2_pins_d: daudio2_sleep@0 {
            		pins = "PB7", "PB5", "PB6", "PB4", "PB3";
            		function = "io_disabled";
            		drive-strength = <20>;
            		bias-disable;
            	};
            
            	spdif_pins_a: spdif@0 {
            		/* SPDIF_PIN: SPDIF_OUT */
            		pins = "PB0";
            		function = "spdif";
            		drive-strength = <20>;
            		bias-disable;
            	};
            
            	spdif_pins_b: spdif_sleep@0 {
            		pins = "PB0";
            		function = "io_disabled";
            		drive-strength = <20>;
            		bias-disable;
            	};
            
            	spi0_pins_a: spi0@0 {
            		pins = "PC2", "PC4", "PC5"; /* clk, mosi, miso */
            		function = "spi0";
            		muxsel = <2>;
            		drive-strength = <10>;
            	};
            
            	spi0_pins_b: spi0@1 {
            		pins = "PC3", "PC7", "PC6";
            		function = "spi0";
            		muxsel = <2>;
            		drive-strength = <10>;
            		bias-pull-up;   /* cs, hold, wp should be pulled up */
            	};
            
            	spi0_pins_c: spi0@2 {
            		pins = "PC2", "PC3", "PC4", "PC5","PC6", "PC7";
            		function = "gpio_in";
            		muxsel = <0>;
            		drive-strength = <10>;
            	};
            
            	spi1_pins_a: spi1@0 {
            		pins = "PD11", "PD12", "PD13"; /* clk, mosi, miso */
            		function = "spi1";
            		drive-strength = <10>;
            	};
            
            	spi1_pins_b: spi1@1 {
            		pins = "PD10", "PD14", "PD15";
            		function = "spi1";
            		drive-strength = <10>;
            		bias-pull-up;   /* cs, hold, wp should be pulled up */
            	};
            
            	spi1_pins_c: spi1@2 {
            		pins = "PD10", "PD11", "PD12", "PD13","PD14", "PD15";
            		function = "gpio_in";
            		drive-strength = <10>;
            	};
            
            	ledc_pins_a: ledc@0 {
            		pins = "PC0";
            		function = "ledc";
            		drive-strength = <10>;
            	};
            
            	ledc_pins_b: ledc@1 {
            		pins = "PC0";
            		function = "gpio_in";
            	};
            
            	pwm0_pin_a: pwm0@0 {
            		pins = "PD16";
            		function = "pwm0";
            		drive-strength = <10>;
            		bias-pull-up;
            	};
            
            	pwm0_pin_b: pwm0@1 {
            		pins = "PD16";
            		function = "gpio_in";
            		bias-disable;
            	};
            
            	pwm2_pin_a: pwm2@0 {
            		pins = "PD18";
            		function = "pwm2";
            		drive-strength = <10>;
            		bias-pull-up;
            	};
            
            	pwm2_pin_b: pwm2@1 {
            		pins = "PD18";
            		function = "gpio_out";
            	};
            /*
            	pwm7_pin_a: pwm7@0 {
            		pins = "PD22";
            		function = "pwm7";
            		drive-strength = <10>;
            		bias-pull-up;
            	};
            
            	pwm7_pin_b: pwm7@1 {
            		pins = "PD22";
            		function = "gpio_in";
            	};
            */
            
            	s_cir0_pins_a: s_cir@0 {
            		pins = "PB12";
            		function = "ir";
            		drive-strength = <10>;
            		bias-pull-up;
            	};
            
            	s_cir0_pins_b: s_cir@1 {
            		pins = "PB12";
            		function = "gpio_in";
            	};
            
            	ir1_pins_a: ir1@0 {
            		pins = "PB0";
            		function = "ir";
            		drive-strength = <10>;
            		bias-pull-up;
            	};
            
            	ir1_pins_b: ir1@1 {
            		pins = "PB0";
            		function = "gpio_in";
            	};
            };
            
            &uart0 {
            	pinctrl-names = "default", "sleep";
            	pinctrl-0 = <&uart0_pins_a>;
            	pinctrl-1 = <&uart0_pins_b>;
            	status = "okay";
            };
            
            &uart1 {
            	pinctrl-names = "default", "sleep";
            	pinctrl-0 = <&uart1_pins_a>;
            	pinctrl-1 = <&uart1_pins_b>;
            	status = "okay";
            };
            
            &uart2 {
            	pinctrl-names = "default", "sleep";
            	pinctrl-0 = <&uart2_pins_a>;
            	pinctrl-1 = <&uart2_pins_b>;
            	status = "disabled";
            };
            
            &uart3 {
            	compatible = "allwinner,sun20iw1-dsp-uart";
            	pinctrl-names = "default", "sleep";
            	pinctrl-0 = <&uart3_pins_a>;
            	pinctrl-1 = <&uart3_pins_a>;
            	status = "okay";
            };
            
            &soc {
            	card0_boot_para@2 {
            		/*
            		 * Avoid dtc compiling warnings.
            		 * @TODO: Developer should modify this to the actual value
            		 */
            		reg = <0x0 0x2 0x0 0x0>;
            		device_type = "card0_boot_para";
            		card_ctrl = <0x0>;
            		card_high_speed = <0x1>;
            		card_line = <0x4>;
            		pinctrl-0 = <&sdc0_pins_a>;
            	};
            
            	card2_boot_para@3 {
            		/*
            		 * Avoid dtc compiling warnings.
            		 * @TODO: Developer should modify this to the actual value
            		 */
            		reg = <0x0 0x3 0x0 0x0>;
            		device_type = "card2_boot_para";
            		card_ctrl = <0x2>;
            		card_high_speed = <0x1>;
            		card_line = <0x4>;
            		pinctrl-0 = <&sdc2_pins_a>;
            		/*pinctrl-0 = <&sdc0_pins_a>;*/
            		/*sdc_ex_dly_used = <0x2>;*/
            		sdc_io_1v8 = <0x1>;
            		/*sdc_type = "tm4";*/
            		sdc_tm4_hs200_max_freq = <150>;
            		sdc_tm4_hs400_max_freq = <100>;
            		sdc_ex_dly_used = <2>;
            		/*sdc_tm4_win_th = <8>;*/
            		/*sdc_dis_host_caps = <0x180>;*/
            	};
            
            	rfkill: rfkill@0 {
            		compatible    = "allwinner,sunxi-rfkill";
            		chip_en;
            		power_en;
            		pinctrl-0 = <&wlan_pins_a>;
            		pinctrl-names = "default";
            		status        = "okay";
            
            		wlan: wlan@0 {
            			compatible    = "allwinner,sunxi-wlan";
            			clock-names = "32k-fanout1";
            			clocks = <&ccu CLK_FANOUT1_OUT>;
            			wlan_busnum    = <0x1>;
            			wlan_regon    = <&pio PG 12 GPIO_ACTIVE_HIGH>;
            			wlan_hostwake  = <&pio PG 10 GPIO_ACTIVE_HIGH>;
            			/*wlan_power    = "VCC-3V3";*/
            			/*wlan_power_vol = <3300000>;*/
            			/*interrupt-parent = <&pio>;
            			interrupts = < PG 10 IRQ_TYPE_LEVEL_HIGH>;*/
            			wakeup-source;
            
            		};
            
            		bt: bt@0 {
            			compatible    = "allwinner,sunxi-bt";
            			clock-names = "32k-fanout1";
            			clocks = <&ccu CLK_FANOUT1_OUT>;
            			/*bt_power_num = <0x01>;*/
            			/*bt_power      = "axp803-dldo1";*/
            			/*bt_io_regulator = "axp803-dldo1";*/
            			/*bt_io_vol = <3300000>;*/
            			/*bt_power_vol = <330000>;*/
            			bt_rst_n      = <&pio PG 18 GPIO_ACTIVE_LOW>;
            			status        = "okay";
            		};
            	};
            
            	btlpm: btlpm@0 {
            		compatible  = "allwinner,sunxi-btlpm";
            		uart_index  = <0x1>;
            		bt_wake     = <&pio PG 16 GPIO_ACTIVE_HIGH>;
            		bt_hostwake = <&pio PG 17 GPIO_ACTIVE_HIGH>;
            		status      = "okay";
            	};
            
            	addr_mgt: addr_mgt@0 {
            		compatible     = "allwinner,sunxi-addr_mgt";
            		type_addr_wifi = <0x0>;
            		type_addr_bt   = <0x0>;
            		type_addr_eth  = <0x0>;
            		status         = "okay";
            	};
            };
            
            &sdc2 {
            	non-removable;
            	bus-width = <4>;
            	mmc-ddr-1_8v;
            	mmc-hs200-1_8v;
            	no-sdio;
            	no-sd;
            	ctl-spec-caps = <0x308>;
            	cap-mmc-highspeed;
            	sunxi-power-save-mode;
            	sunxi-dis-signal-vol-sw;
            	mmc-bootpart-noacc;
            	max-frequency = <150000000>;
            	/*vmmc-supply = <&reg_dcdc1>;*/
            	/*emmc io vol 3.3v*/
            	/*vqmmc-supply = <&reg_aldo1>;*/
            	/*emmc io vol 1.8v*/
            	/*vqmmc-supply = <&reg_eldo1>;*/
            	status = "disabled";
            };
            
            &sdc0 {
            	bus-width = <4>;
            	cd-gpios = <&pio PF 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
            	/*non-removable;*/
            	/*broken-cd;*/
            	cd-inverted;
            	/*data3-detect;*/
            	/*card-pwr-gpios = <&pio PH 14 1 1 2 0xffffffff>;*/
            	cd-used-24M;
            	cap-sd-highspeed;
            	/*sd-uhs-sdr50;*/
            	/*sd-uhs-ddr50;*/
            	/*sd-uhs-sdr104;*/
            	no-sdio;
            	no-mmc;
            	sunxi-power-save-mode;
            	/*sunxi-dis-signal-vol-sw;*/
            	max-frequency = <150000000>;
            	ctl-spec-caps = <0x8>;
            	/*vmmc-supply = <&reg_dcdc1>;*/
            	/*vqmmc33sw-supply = <&reg_dcdc1>;*/
            	/*vdmmc33sw-supply = <&reg_dcdc1>;*/
            	/*vqmmc18sw-supply = <&reg_eldo1>;*/
            	/*vdmmc18sw-supply = <&reg_eldo1>;*/
            	status = "okay";
            };
            
            &sdc1 {
            	bus-width = <4>;
            	no-mmc;
            	no-sd;
            	cap-sd-highspeed;
            	/*sd-uhs-sdr12*/
            	/*sd-uhs-sdr25;*/
            	/*sd-uhs-sdr50;*/
            	/*sd-uhs-ddr50;*/
            	/*sd-uhs-sdr104;*/
            	/*sunxi-power-save-mode;*/
            	/*sunxi-dis-signal-vol-sw;*/
            	cap-sdio-irq;
            	keep-power-in-suspend;
            	ignore-pm-notify;
            	max-frequency = <150000000>;
            	ctl-spec-caps = <0x8>;
            	status = "okay";
            };
            
            
            /*
            tvd configuration
            used                   (create device, 0: do not create device, 1: create device)
            agc_auto_enable        (0: agc manual mode,agc_manual_value is valid; 1: agc auto mode)
            agc_manual_value       (agc manual value, default value is 64)
            cagc_enable            (cagc        0: disable, 1: enable)
            fliter_used            (3d fliter   0: disable, 1: enable)
            support two PMU power  (tvd_power0, tvd_power1)
            support two GPIO power (tvd_gpio0, tvd_gpio1)
            NOTICE: If tvd need pmu power or gpio power,params need be configured under [tvd]
            tvd_sw                 (the switch of all tvd driver.)
            tvd_interface          (0: cvbs, 1: ypbpr,)
            tvd_format             (0:TVD_PL_YUV420 , 1: MB_YUV420, 2: TVD_PL_YUV422)
            tvd_system             (0:ntsc, 1:pal)
            tvd_row                (total row number in multi channel mode 1-2)
            tvd_column             (total column number in multi channel mode 1-2)
            tvd_channelx_en        (0:disable, 1~4:position in multi channel mode,In single channel
                                   mode,mean enable)
            tvd_row*tvd_column is the total tvd channel number to be used in multichannel mode
            +--------------------+--------------------+
            |                    |                    |
            |                    |                    |
            |         1          |         2          |
            |                    |                    |
            |                    |                    |
            +--------------------+--------------------+
            |                    |                    |
            |                    |                    |
            |         3          |         4          |
            |                    |                    |
            |                    |                    |
            +--------------------+--------------------+
            */
            
            &tvd {
            	tvd_sw          = <1>;
            	tvd_interface   = <0>;
            	tvd_format      = <0>;
            	tvd_system      = <1>;
            	tvd_row         = <1>;
            	tvd_column      = <1>;
            	tvd_channel0_en = <1>;
            	tvd_channel1_en = <0>;
            	tvd_channel2_en = <0>;
            	tvd_channel3_en = <0>;
            	/*tvd_gpio0 = <&pio PD 22 GPIO_ACTIVE_HIGH>;*/
            	/*tvd_gpio1 = <&pio PD 23 GPIO_ACTIVE_HIGH>;*/
            	/*tvd_gpio2 = <&pio PD 24 GPIO_ACTIVE_HIGH>;*/
            	/*	dc1sw-supply = <&reg_dc1sw>;*/
            	/*	eldo3-supply = <&reg_eldo3>;*/
            	/*tvd_power0      = "dc1sw"*/
            	/*tvd_power1      = "eldo3"*/
            };
            
            &tvd0 {
            	used                    = <1>;
            	agc_auto_enable         = <1>;
            	agc_manual_value        = <64>;
            	cagc_enable             = <1>;
            	fliter_used             = <1>;
            };
            
            /* Audio Driver modules */
            &sunxi_rpaf_dsp0 {
            	status = "okay";
            };
            
            /* if audiocodec is used, sdc0 and uart0 should be closed to enable PA. */
            &codec {
            	/* MIC and headphone gain setting */
            	mic1gain 	= <0x13>;
            	mic2gain 	= <0x13>;
            	mic3gain 	= <0x13>;
            	/* ADC/DAC DRC/HPF func enabled */
                    /* 0x1:DAP_HP_EN; 0x2:DAP_SPK_EN; 0x3:DAP_HPSPK_EN */
            	adcdrc_cfg 	= <0x0>;
            	adchpf_cfg 	= <0x1>;
            	dacdrc_cfg 	= <0x0>;
            	dachpf_cfg 	= <0x0>;
            	/* Volume about */
            	digital_vol 	= <0x00>;
            	lineout_vol 	= <0x1a>;
            	headphonegain	= <0x03>;
            	/* Pa enabled about */
            	pa_level 	= <0x01>;
            	pa_pwr_level 	= <0x01>;
            	pa_msleep_time 	= <0x78>;
            	/* gpio-spk	= <&pio PF 2 GPIO_ACTIVE_HIGH>; */
            	/* gpio-spk-pwr	= <&pio PF 4 GPIO_ACTIVE_HIGH>; */
            	/* regulator about */
            	/* avcc-supply	= <&reg_aldo1>; */
            	/* hpvcc-supply	= <&reg_eldo1>; */
            	status = "okay";
            };
            
            &sndcodec {
            	hp_detect_case	= <0x01>;
            	jack_enable	= <0x01>;
            	status = "okay";
            };
            
            &dummy_cpudai {
            	/* CMA config about */
            	playback_cma	= <128>;
            	capture_cma	= <256>;
            	status = "okay";
            };
            
            &dmic {
            	pinctrl-names   = "default","sleep";
            	pinctrl-0       = <&dmic_pins_a>;
            	pinctrl-1       = <&dmic_pins_b>;
            	status = "okay";
            };
            
            &sounddmic {
            	status = "okay";
            };
            
            &dmic_codec {
            	status = "okay";
            };
            
            /*-----------------------------------------------------------------------------
             * pcm_lrck_period	16/32/64/128/256
             *			(set 0x20 for HDMI audio out)
             * slot_width_select	16bits/20bits/24bits/32bits
             *			(set 0x20 for HDMI audio out)
             * frametype		0 --> short frame = 1 clock width;
             *			1 --> long frame = 2 clock width;
             * tdm_config		0 --> pcm
             *			1 --> i2s
             *			(set 0x01 for HDMI audio out)
             * mclk_div		0 --> not output
             *			1/2/4/6/8/12/16/24/32/48/64/96/128/176/192
             *			(set mclk as external codec clk source, freq is pll_audio/mclk_div)
             * pinctrl_used		0 --> I2S/PCM use for internal (e.g. HDMI)
             *			1 --> I2S/PCM use for external audio
             * daudio_type:		0 --> external audio type
             *			1 --> HDMI audio type
             *---------------------------------------------------------------------------*/
            &daudio0 {
            	mclk_div 	= <0x01>;
            	frametype 	= <0x00>;
            	tdm_config 	= <0x01>;
            	sign_extend 	= <0x00>;
            	msb_lsb_first 	= <0x00>;
            	pcm_lrck_period = <0x80>;
            	slot_width_select = <0x20>;
            	pinctrl-names   = "default", "sleep";
            	pinctrl-0       = <&daudio0_pins_a &daudio0_pins_b &daudio0_pins_c>;
            	pinctrl-1       = <&daudio0_pins_d>;
            	pinctrl_used	= <0x0>;
            	status = "disabled";
            };
            
            /*-----------------------------------------------------------------------------
             * simple-audio-card,name	name of sound card, e.g.
             *				"snddaudio0" --> use for external audio
             *				"sndhdmi" --> use for HDMI audio
             * sound-dai			"snd-soc-dummy" --> use for I2S
             *				"hdmiaudio" --> use for HDMI audio
             *				"ac108" --> use for external audio of ac108
             *---------------------------------------------------------------------------*/
            &sounddaudio0 {
            	/* simple-audio-card,format = "i2s"; */
            	/* simple-audio-card,frame-master = <&daudio0_master>; */
            	/* simple-audio-card,bitclock-master = <&daudio0_master>; */
            	/* simple-audio-card,bitclock-inversion; */
            	/* simple-audio-card,frame-inversion; */
            	status = "disabled";
            	daudio0_master: simple-audio-card,codec {
            		/* sound-dai = <&ac108>; */
            	};
            };
            
            &daudio1 {
            	mclk_div 	= <0x01>;
            	frametype 	= <0x00>;
            	tdm_config 	= <0x01>;
            	sign_extend 	= <0x00>;
            	msb_lsb_first 	= <0x00>;
            	pcm_lrck_period = <0x80>;
            	slot_width_select = <0x20>;
            	pinctrl-names   = "default", "sleep";
            	pinctrl-0       = <&daudio1_pins_a &daudio1_pins_b &daudio1_pins_c>;
            	pinctrl-1       = <&daudio1_pins_d>;
            	pinctrl_used	= <0x0>;
            	status = "disabled";
            };
            
            &sounddaudio1 {
            	status = "disabled";
            	daudio1_master: simple-audio-card,codec {
            		/* sound-dai = <&ac108>; */
            	};
            };
            
            &daudio2 {
            	mclk_div 	= <0x00>;
            	frametype 	= <0x00>;
            	tdm_config 	= <0x01>;
            	sign_extend 	= <0x00>;
            	tx_data_mode 	= <0x00>;
            	rx_data_mode 	= <0x00>;
            	msb_lsb_first 	= <0x00>;
            	pcm_lrck_period = <0x20>;
            	slot_width_select = <0x20>;
            	asrc_function_en  = <0x00>;
            	pinctrl-names   = "default", "sleep";
            	/*pinctrl-0       = <&daudio2_pins_a &daudio2_pins_b &daudio2_pins_c>;*/
            	/*pinctrl-1       = <&daudio2_pins_d>;*/
            	/* HDMI audio, no need pin */
            	pinctrl-0;
            	pinctrl-1;
            	pinctrl_used	= <0x0>;
            	daudio_type	= <0x1>;
            	status = "okay";
            };
            
            /* if HDMI audio is used, daudio2 should be enable. */
            &hdmiaudio {
            	status = "okay";
            };
            
            &sounddaudio2 {
            	status = "okay";
            	simple-audio-card,name = "sndhdmi";
            	daudio2_master: simple-audio-card,codec {
            		sound-dai = <&hdmiaudio>;
            	};
            };
            
            &spdif {
            	pinctrl-names   = "default","sleep";
            	pinctrl-0       = <&spdif_pins_a>;
            	pinctrl-1       = <&spdif_pins_b>;
            	status = "disabled";
            };
            
            &soundspdif {
            	status = "disabled";
            };
            
            /*
             *usb_port_type: usb mode. 0-device, 1-host, 2-otg.
             *usb_detect_type: usb hotplug detect mode. 0-none, 1-vbus/id detect, 2-id/dpdm detect.
             *usb_detect_mode: 0-thread scan, 1-id gpio interrupt.
             *usb_id_gpio: gpio for id detect.
             *usb_det_vbus_gpio: gpio for id detect. gpio or "axp_ctrl";
             *usb_wakeup_suspend:0-SUPER_STANDBY, 1-USB_STANDBY.
             */
            &usbc0 {
            	device_type = "usbc0";
            	usb_port_type = <0x2>;
            	usb_detect_type = <0x1>;
            	usb_detect_mode = <0>;
            	usb_id_gpio = <&pio PD 21 GPIO_ACTIVE_HIGH>;
            	enable-active-high;
            	usb_det_vbus_gpio = <&pio PD 20 GPIO_ACTIVE_HIGH>;
            	usb_wakeup_suspend = <0>;
            	usb_serial_unique = <0>;
            	usb_serial_number = "20080411";
            	rndis_wceis = <1>;
            	status = "okay";
            };
            
            &ehci0 {
            	drvvbus-supply = <&reg_usb1_vbus>;
            };
            
            &ohci0 {
            	drvvbus-supply = <&reg_usb1_vbus>;
            };
            
            &usbc1 {
            	device_type = "usbc1";
            	usb_regulator_io = "nocare";
            	usb_wakeup_suspend = <0>;
            	status = "okay";
            };
            
            &ehci1 {
            	status = "okay";
            };
            
            &ohci1 {
            	status = "okay";
            };
            
            &twi0 {
            	clock-frequency = <400000>;
            	pinctrl-0 = <&twi0_pins_a>;
            	pinctrl-1 = <&twi0_pins_b>;
            	pinctrl-names = "default", "sleep";
            	status = "disabled";
            
            	eeprom@50 {
            		compatible = "atmel,24c16";
            		reg = <0x50>;
            		status = "disabled";
            	};
            };
            
            &twi1 {
            	clock-frequency = <400000>;
            	pinctrl-0 = <&twi1_pins_a>;
            	pinctrl-1 = <&twi1_pins_b>;
            	pinctrl-names = "default", "sleep";
            	status = "disabled";
            };
            
            &twi2 {
            	clock-frequency = <400000>;
            	pinctrl-0 = <&twi2_pins_a>;
            	pinctrl-1 = <&twi2_pins_b>;
            	pinctrl-names = "default", "sleep";
            	dmas = <&dma 45>, <&dma 45>;
            	dma-names = "tx", "rx";
            	status = "okay";
            
            	/* pcf8574-usage:
            	 * only use gpio0~7, 0 means PP0.
            	 * pin set:
            	 * gpios = <&pcf8574 0 GPIO_ACTIVE_LOW>;
            	 * interrupt set:
            	 * interrupt-parent = <&pcf8574>;
            	 * interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
            	 */
            	pcf8574: gpio@38 {
            		compatible = "nxp,pcf8574";
            		reg = <0x38>;
            		gpio_base = <2020>;
            		gpio-controller;
            		#gpio-cells = <2>;
            		interrupt-controller;
            		#interrupt-cells = <2>;
            		interrupt-parent = <&pio>;
            		interrupts = <PB 2 IRQ_TYPE_EDGE_FALLING>;
            		status = "okay";
            	};
            
            	ctp@14 {
            		compatible = "allwinner,goodix";
            		device_type = "ctp";
            		reg = <0x14>;
            		status = "disabled";
            		ctp_name = "gt9xxnew_ts";
            		ctp_twi_id = <0x2>;
            		ctp_twi_addr = <0x14>;
            		ctp_screen_max_x = <0x320>;
            		ctp_screen_max_y = <0x500>;
            		ctp_revert_x_flag = <0x0>;
            		ctp_revert_y_flag = <0x1>;
            		ctp_exchange_x_y_flag = <0x0>;
            		ctp_int_port = <&pio PG 14 GPIO_ACTIVE_HIGH>;
            		ctp_wakeup = <&pio PG 15 GPIO_ACTIVE_HIGH>;
            	};
            };
            
            &twi3 {
            	clock-frequency = <400000>;
            	pinctrl-0 = <&twi3_pins_a>;
            	pinctrl-1 = <&twi3_pins_b>;
            	pinctrl-names = "default", "sleep";
            	status = "disabled";
            };
            
            &gmac0 {
            	phy-mode = "rgmii";
            	use_ephy25m = <1>;
            	pinctrl-0 = <&gmac_pins_a>;
            	pinctrl-1 = <&gmac_pins_b>;
            	pinctrl-names = "default", "sleep";
            	phy-rst = <&pio PE 16 GPIO_ACTIVE_HIGH>;
            	tx-delay = <3>; /*2~4*/
            	rx-delay = <0>;
            	status = "okay";
            };
            
            &spi0 {
            	clock-frequency = <100000000>;
            	pinctrl-0 = <&spi0_pins_a &spi0_pins_b>;
            	pinctrl-1 = <&spi0_pins_c>;
            	pinctrl-names = "default", "sleep";
            	/*spi-supply = <&reg_dcdc1>;*/
            	spi_slave_mode = <0>;
            	spi0_cs_number = <1>;
                    spi0_cs_bitmap = <1>;
            	status = "disabled";
            
            	spi-nand@0 {
            		compatible = "spi-nand";
            		spi-max-frequency=<0x5F5E100>;
            		reg = <0x0>;
            		spi-rx-bus-width=<0x04>;
            		spi-tx-bus-width=<0x04>;
            		status="disabled";
            	};
            };
            
            &spi1 {
            	clock-frequency = <100000000>;
            	pinctrl-0 = <&spi1_pins_a &spi1_pins_b>;
            	pinctrl-1 = <&spi1_pins_c>;
            	pinctrl-names = "default", "sleep";
            	spi_slave_mode = <0>;
            	spi1_cs_number = <1>;
            	spi1_cs_bitmap = <1>;
            	spi_dbi_enable = <1>;
            	status = "disabled";
            
            	spi_board1@0 {
            		device_type = "spi-dbi";
            		compatible = "sunxi,spidbi";
            		spi-max-frequency = <0x5f5e100>;
            		reg = <0x0>;
            		spi-rx-bus-width = <0x4>;
            		spi-tx-bus-width = <0x4>;
            		status = "okay";
            	};
            	/* spi_board1@0 {
            		device_type = "spi_board1";
            		compatible = "rohm,dh2228fv";
            		spi-max-frequency = <0x5f5e100>;
            		reg = <0x0>;
            		spi-rx-bus-width = <0x4>;
            		spi-tx-bus-width = <0x4>;
            		status = "disabled";
            	}; */
            };
            
            &ledc {
            	pinctrl-names = "default", "sleep";
            	pinctrl-0 = <&ledc_pins_a>;
            	pinctrl-1 = <&ledc_pins_b>;
            	led_count = <12>;
            	output_mode = "GRB";
            	reset_ns = <84>;
            	t1h_ns = <800>;
            	t1l_ns = <320>;
            	t0h_ns = <300>;
            	t0l_ns = <800>;
            	wait_time0_ns = <84>;
            	wait_time1_ns = <84>;
            	wait_data_time_ns = <600000>;
            	status	= "okay";
            };
            
            &keyboard0 {
            	key0 = <210 0x160>;
            	wakeup-source;
            	status = "okay";
            };
            
            /*----------------------------------------------------------------------------------
            disp init configuration
            
            disp_mode             (0:screen0<screen0,fb0>)
            screenx_output_type   (0:none; 1:lcd; 2:tv; 3:hdmi;5:vdpo)
            screenx_output_mode   (used for hdmi output, 0:480i 1:576i 2:480p 3:576p 4:720p50)
                                  (5:720p60 6:1080i50 7:1080i60 8:1080p24 9:1080p50 10:1080p60)
            screenx_output_format (for hdmi, 0:RGB 1:yuv444 2:yuv422 3:yuv420)
            screenx_output_bits   (for hdmi, 0:8bit 1:10bit 2:12bit 2:16bit)
            screenx_output_eotf   (for hdmi, 0:reserve 4:SDR 16:HDR10 18:HLG)
            screenx_output_cs     (for hdmi, 0:undefined  257:BT709 260:BT601  263:BT2020)
            screenx_output_dvi_hdmi (for hdmi, 0:undefined 1:dvi mode 2:hdmi mode)
            screen0_output_range   (for hdmi, 0:default 1:full 2:limited)
            screen0_output_scan    (for hdmi, 0:no data 1:overscan 2:underscan)
            screen0_output_aspect_ratio  (for hdmi, 8-same as original picture 9-4:3 10-16:9 11-14:9)
            fbx format            (4:RGB655 5:RGB565 6:RGB556 7:ARGB1555 8:RGBA5551 9:RGB888 10:ARGB8888 12:ARGB4444)
            fbx pixel sequence    (0:ARGB 1:BGRA 2:ABGR 3:RGBA)
            fb0_scaler_mode_enable(scaler mode enable, used FE)
            fbx_width,fbx_height  (framebuffer horizontal/vertical pixels, fix to output resolution while equal 0)
            lcdx_backlight        (lcd init backlight,the range:[0,256],default:197
            lcdx_yy               (lcd init screen bright/contrast/saturation/hue, value:0~100, default:50/50/57/50)
            lcd0_contrast         (LCD contrast, 0~100)
            lcd0_saturation       (LCD saturation, 0~100)
            lcd0_hue              (LCD hue, 0~100)
            framebuffer software rotation setting:
            disp_rotation_used:   (0:disable; 1:enable,you must set fbX_width to lcd_y,
            set fbX_height to lcd_x)
            degreeX:              (X:screen index; 0:0 degree; 1:90 degree; 3:270 degree)
            degreeX_Y:            (X:screen index; Y:layer index 0~15; 0:0 degree; 1:90 degree; 3:270 degree)
            devX_output_type : config output type in bootGUI framework in UBOOT-2018.
            				   (0:none; 1:lcd; 2:tv; 4:hdmi;)
            devX_output_mode : config output resolution(see include/video/sunxi_display2.h) of bootGUI framework in UBOOT-2018
            devX_screen_id   : config display index of bootGUI framework in UBOOT-2018
            devX_do_hpd      : whether do hpd detectation or not in UBOOT-2018
            chn_cfg_mode     : Hardware DE channel allocation config. 0:single display with 6
            				   channel, 1:dual display with 4 channel in main display and 2 channel in second
                               display, 2:dual display with 3 channel in main display and 3 channel in second
                               in display.
            ----------------------------------------------------------------------------------*/
            &disp {
            	disp_init_enable         = <1>;
            	disp_mode                = <0>;
            
            	screen0_output_type      = <1>;
            	screen0_output_mode      = <4>;
            
            	screen1_output_type      = <3>;
            	screen1_output_mode      = <10>;
            
            	screen1_output_format    = <0>;
            	screen1_output_bits      = <0>;
            	screen1_output_eotf      = <4>;
            	screen1_output_cs        = <257>;
            	screen1_output_dvi_hdmi  = <2>;
            	screen1_output_range     = <2>;
            	screen1_output_scan      = <0>;
            	screen1_output_aspect_ratio = <8>;
            
            	dev0_output_type         = <1>;
            	dev0_output_mode         = <4>;
            	dev0_screen_id           = <0>;
            	dev0_do_hpd              = <0>;
            
            	dev1_output_type         = <4>;
            	dev1_output_mode         = <10>;
            	dev1_screen_id           = <1>;
            	dev1_do_hpd              = <1>;
            
            	def_output_dev           = <0>;
            	hdmi_mode_check          = <1>;
            
            	fb0_format               = <0>;
            	fb0_width                = <0>;
            	fb0_height               = <0>;
            
            	fb1_format               = <0>;
            	fb1_width                = <0>;
            	fb1_height               = <0>;
            	chn_cfg_mode             = <1>;
            
            	disp_para_zone           = <1>;
            	/*VCC-LCD*/
            /*	dc1sw-supply = <&reg_dc1sw>;*/
            	/*VCC-DSI*/
            /*	eldo3-supply = <&reg_eldo3>;*/
            	/*VCC-PD*/
            /*	dcdc1-supply = <&reg_dcdc1>;*/
            };
            
            /*----------------------------------------------------------------------------------
            ;lcd0 configuration
            
            ;lcd_if:               0:hv(sync+de); 1:8080; 2:ttl; 3:lvds; 4:dsi; 5:edp; 6:extend dsi
            ;lcd_hv_if             0:Parallel RGB; 8:Serial RGB; 10:Dummy RGB; 11: RGB Dummy;12:CCIR656
            ;lcd_hv_clk_phase      0:0 degree;1:90 degree;2:180 degree;3:270 degree
            ;lcd_hv_sync_polarity  0:vs low,hs low; 1:vs high,hslow; 2:vs low,hs high; 3:vs high,hs high
            ;lcd_hv_syuv_seq       0:YUYV; 1:YVYU; 2:UYVY; 3:VYUY
            ;lcd_cpu_if            0:18bit/1 cycle parallel(RGB666); 4:16bit/1cycle parallel (RGB565)
            ;                      6:18bit/3 cycle parallel(RGB666); 7:16bit/2cycle parallel (RGB565)
            ;lcd_cpu_te            0:frame auto trigger; 1:frame triggered by te rising edge; 2:frame triggered by te falling edge;
            ;lcd_dsi_if            0:video mode; 1: Command mode; 2:video burst mode
            ;lcd_dsi_te            0:frame auto trigger; 1:frame triggered by te rising edge; 2:frame triggered by te falling edge;
            ;lcd_x:                lcd horizontal resolution
            ;lcd_y:                lcd vertical resolution
            ;lcd_width:            width of lcd in mm
            ;lcd_height:           height of lcd in mm
            ;lcd_dclk_freq:        in MHZ unit
            ;lcd_pwm_freq:         in HZ unit
            ;lcd_pwm_pol:          lcd backlight PWM polarity
            ;lcd_pwm_max_limit     lcd backlight PWM max limit(<=255)
            ;lcd_hbp:              hsync back porch(pixel) + hsync plus width(pixel);
            ;lcd_ht:               hsync total cycle(pixel)
            ;lcd_vbp:              vsync back porch(line) + vysnc plus width(line)
            ;lcd_vt:               vysnc total cycle(line)
            ;lcd_hspw:             hsync plus width(pixel)
            ;lcd_vspw:             vysnc plus width(pixel)
            ;lcd_lvds_if:          0:single link;  1:dual link
            ;lcd_lvds_colordepth:  0:8bit; 1:6bit
            ;lcd_lvds_mode:        0:NS mode; 1:JEIDA mode
            ;lcd_frm:              0:disable; 1:enable rgb666 dither; 2:enable rgb656 dither
            ;lcd_io_phase:         0:noraml; 1:intert phase(0~3bit: vsync phase; 4~7bit:hsync phase;
            ;                      8~11bit:dclk phase; 12~15bit:de phase)
            ;lcd_gamma_en          lcd gamma correction enable
            ;lcd_bright_curve_en   lcd bright curve correction enable
            ;lcd_cmap_en           lcd color map function enable
            ;deu_mode              0:smoll lcd screen; 1:large lcd screen(larger than 10inch)
            ;lcdgamma4iep:         Smart Backlight parameter, lcd gamma vale * 10;
            ;                      decrease it while lcd is not bright enough; increase while lcd is too bright
            ;smart_color           90:normal lcd screen 65:retina lcd screen(9.7inch)
            ;Pin setting for special function ie.LVDS, RGB data or vsync
            ;   name(donot care) = port:PD12<pin function><pull up or pull down><drive ability><output level>
            ;Pin setting for gpio:
            ;   lcd_gpio_X     = port:PD12<pin function><pull up or pull down><drive ability><output level>
            ;Pin setting for backlight enable pin
            ;   lcd_bl_en     = port:PD12<pin function><pull up or pull down><drive ability><output level>
            ;fsync setting, pulse to csi
            ;lcd_fsync_en          (0:disable fsync,1:enable)
            ;lcd_fsync_act_time    (active time of fsync, unit:pixel)
            ;lcd_fsync_dis_time    (disactive time of fsync, unit:pixel)
            ;lcd_fsync_pol         (0:positive;1:negative)
            ;gpio config: <&pio for cpu or &r_pio for cpus, port, port num, pio function,
            pull up or pull down(default 0), driver level(default 1), data>
            ;For dual link lvds: use lvds2link_pins_a  and lvds2link_pins_b instead
            ;For rgb24: use rgb24_pins_a  and rgb24_pins_b instead
            ;For lvds1: use lvds1_pins_a  and lvds1_pins_b instead
            ;For lvds0: use lvds0_pins_a  and lvds0_pins_b instead
            ;----------------------------------------------------------------------------------*/
            &lcd0 {
            	lcd_used            = <1>;
            
            	lcd_driver_name     = "tft08006";
            	lcd_backlight       = <100>;
            	lcd_if              = <4>;
            
            	lcd_x               = <800>;
            	lcd_y               = <1280>;
            	lcd_width           = <52>;
            	lcd_height          = <52>;
            	lcd_dclk_freq       = <70>;
            
            	lcd_pwm_used        = <1>;
            	lcd_pwm_ch          = <2>;
            	lcd_pwm_freq        = <1000>;
            	lcd_pwm_pol         = <0>;
            	lcd_pwm_max_limit   = <255>;
            
            	lcd_hbp             = <32>;
            	lcd_ht              = <868>;
            	lcd_hspw            = <4>;
            	lcd_vbp             = <12>;
            	lcd_vt              = <1311>;
            	lcd_vspw            = <4>;
            
            	lcd_dsi_if          = <0>;
            	lcd_dsi_lane        = <4>;
            	lcd_lvds_if         = <0>;
            	lcd_lvds_colordepth = <0>;
            	lcd_lvds_mode       = <0>;
            	lcd_frm             = <0>;
            	lcd_hv_clk_phase    = <0>;
            	lcd_hv_sync_polarity= <0>;
            	lcd_io_phase        = <0x0000>;
            	lcd_gamma_en        = <0>;
            	lcd_bright_curve_en = <0>;
            	lcd_cmap_en         = <0>;
            	lcd_fsync_en        = <0>;
            	lcd_fsync_act_time  = <1000>;
            	lcd_fsync_dis_time  = <1000>;
            	lcd_fsync_pol       = <0>;
            
            	deu_mode            = <0>;
            	lcdgamma4iep        = <22>;
            	smart_color         = <90>;
            
            	lcd_gpio_0 =  <&pio PG 13 GPIO_ACTIVE_HIGH>;
            	pinctrl-0 = <&dsi4lane_pins_a>;
            	pinctrl-1 = <&dsi4lane_pins_b>;
            };
            
            &hdmi {
            	hdmi_used = <1>;
            	hdmi_power_cnt = <0>;
            	hdmi_cts_compatibility = <1>;
            	hdmi_hdcp_enable = <1>;
            	hdmi_hdcp22_enable = <0>;
            	hdmi_cec_support = <1>;
            	hdmi_cec_super_standby = <0>;
            
            	ddc_en_io_ctrl = <0>;
            	power_io_ctrl = <0>;
            };
            
            &pwm0 {
            	pinctrl-names = "active", "sleep";
            	pinctrl-0 = <&pwm0_pin_a>;
            	pinctrl-1 = <&pwm0_pin_b>;
            	status = "okay";
            };
            
            &pwm2 {
            	pinctrl-names = "active", "sleep";
            	pinctrl-0 = <&pwm2_pin_a>;
            	pinctrl-1 = <&pwm2_pin_b>;
            	status = "okay";
            };
            
            /*
            &pwm7 {
            	pinctrl-names = "active", "sleep";
            	pinctrl-0 = <&pwm7_pin_a>;
            	pinctrl-1 = <&pwm7_pin_b>;
            	status = "okay";
            };
            */
            
            &rtp {
            	allwinner,tp-sensitive-adjust = <0xf>;
            	allwinner,filter-type = <0x1>;
            	allwinner,ts-attached;
            	status = "disabled";
            };
            
            &gpadc {
            	channel_num = <2>;
            	channel_select = <3>;
            	channel_data_select = <3>;
            	channel_compare_select = <3>;
            	channel_cld_select = <3>;
            	channel_chd_select = <3>;
            	channel0_compare_lowdata = <1700000>;
            	channel0_compare_higdata = <1200000>;
            	channel1_compare_lowdata = <460000>;
            	channel1_compare_higdata = <1200000>;
            	status = "disabled";
            };
            
            &s_cir0 {
            	pinctrl-names = "default", "sleep";
            	pinctrl-0 = <&s_cir0_pins_a>;
            	pinctrl-1 = <&s_cir0_pins_b>;
            	status = "disabled";
            };
            
            &ir1 {
            	pinctrl-names = "default", "sleep";
            	pinctrl-0 = <&ir1_pins_a>;
            	pinctrl-1 = <&ir1_pins_b>;
            	status = "disabled";
            };
            
            /* &lcd_fb0 {
            	lcd_used = <1>;
            	lcd_driver_name = "kld35512";
            	lcd_if = <1>;
            	lcd_dbi_if = <4>;
            	lcd_data_speed = <60>;
            	lcd_spi_bus_num = <1>;
            	lcd_x = <320>;
            	lcd_y = <480>;
            	lcd_pixel_fmt = <10>;
            	lcd_dbi_fmt = <2>;
            	lcd_rgb_order = <0>;
            	lcd_width = <60>;
            	lcd_height = <95>;
            	lcd_pwm_used = <1>;
            	lcd_pwm_ch = <7>;
            	lcd_pwm_freq = <5000>;
            	lcd_pwm_pol = <1>;
            	lcd_frm = <1>;
            	lcd_gamma_en = <1>;
            	fb_buffer_num = <2>;
            	lcd_backlight = <100>;
            	lcd_fps = <40>;
            	lcd_dbi_te = <1>;
            	lcd_dbi_clk_mode = <1>;
            	lcd_gpio_0 = <&pio PC 0 GPIO_ACTIVE_HIGH>;
            	status = "okay";
            }; */
            
            /* &lcd_fb0 {
            	lcd_used = <1>;
            	lcd_driver_name = "kld2844b";
            	lcd_if = <1>;
            	lcd_dbi_if = <4>;
            	lcd_data_speed = <60>;
            	lcd_spi_bus_num = <1>;
            	lcd_x = <240>;
            	lcd_y = <320>;
            	lcd_width = <60>;
            	lcd_height = <95>;
            	lcd_pwm_used = <1>;
            	lcd_pwm_ch = <7>;
            	lcd_pwm_freq = <5000>;
            	lcd_pwm_pol = <0>;
            	lcd_pixel_fmt = <0>;
            	lcd_dbi_fmt = <3>;
            	lcd_rgb_order = <0>;
            	lcd_frm = <1>;
            	lcd_gamma_en = <1>;
            	fb_buffer_num = <2>;
            	lcd_backlight = <100>;
            	lcd_dbi_te = <1>;
            	lcd_fps = <60>;
            	lcd_gpio_0 = <&pio PC 0 GPIO_ACTIVE_HIGH>;
            	status = "okay";
            }; */
            
            

            然后 env.cfg

            
            #kernel command arguments
            earlyprintk=sunxi-uart,0x02500000
            initcall_debug=0
            console=ttyS0,115200
            nand_root=/dev/ubiblock0_5
            mmc_root=/dev/mmcblk0p5
            mtd_name=sys
            rootfstype=squashfs
            root_partition=rootfs
            boot_partition=boot
            init=/sbin/init
            loglevel=8
            cma=8M
            mac=
            wifi_mac=
            bt_mac=
            specialstr=
            keybox_list=widevine,ec_key,ec_cert1,ec_cert2,ec_cert3,rsa_key,rsa_cert1,rsa_cert2,rsa_cert3
            dsp0_partition=dsp0
            #set kernel cmdline if boot.img or recovery.img has no cmdline we will use this
            setargs_nand=setenv bootargs ubi.mtd=${mtd_name} ubi.block=0,${root_partition} earlyprintk=${earlyprintk} clk_ignore_unused initcall_debug=${initcall_debug} console=${console} loglevel=${loglevel} root=${nand_root} rootfstype=${rootfstype} init=${init} partitions=${partitions} cma=${cma} snum=${snum} mac_addr=${mac} wifi_mac=${wifi_mac} bt_mac=${bt_mac} specialstr=${specialstr} gpt=1
            setargs_nand_ubi=setenv bootargs ubi.mtd=${mtd_name} ubi.block=0,${root_partition} earlyprintk=${earlyprintk} clk_ignore_unused initcall_debug=${initcall_debug} console=${console} loglevel=${loglevel} root=${nand_root} rootfstype=${rootfstype} init=${init} partitions=${partitions} cma=${cma} snum=${snum} mac_addr=${mac} wifi_mac=${wifi_mac} bt_mac=${bt_mac} specialstr=${specialstr} gpt=1
            setargs_mmc=setenv  bootargs earlyprintk=${earlyprintk} clk_ignore_unused initcall_debug=${initcall_debug} console=${console} loglevel=${loglevel} root=${mmc_root}  init=${init} partitions=${partitions} cma=${cma} snum=${snum} mac_addr=${mac} wifi_mac=${wifi_mac} bt_mac=${bt_mac} specialstr=${specialstr} gpt=1
            #nand command syntax: sunxi_flash read address partition_name read_bytes
            #0x4007f800 = 0x40080000(kernel entry) - 0x800(boot.img header 2k)
            boot_dsp0=sunxi_flash read 45000000 ${dsp0_partition};bootr 45000000 0 0
            boot_normal=sunxi_flash read 45000000 ${boot_partition};bootm 45000000
            boot_recovery=sunxi_flash read 45000000 recovery;bootm 45000000
            boot_fastboot=fastboot
            
            #uboot system env config
            bootdelay=0
            #default bootcmd, will change at runtime according to key press
            #default nand boot
            bootcmd=run setargs_nand boot_dsp0 boot_normal
            
            
            D 2 条回复 最后回复 回复 引用 分享 0
            • D
              daMing123 LV 5 @YuzukiTsuru 最后由 编辑

              @yuzukitsuru 不行,修改了env.cfg ,和设备树,直接uboot宕机

              [171]HELLO! BOOT0 is starting!
              [174]BOOT0 commit : 88480af
              [177]set pll start
              [179]fix vccio detect value:0xc0
              [182]periph0 has been enabled
              [185]set pll end
              [186][pmu]: bus read error
              [189]board init ok
              [191]ZQ value = 0x30
              [193]get_pmu_exist() = -1
              [195]ddr_efuse_type: 0xa
              [198]trefi:7.8ms
              [200][AUTO DEBUG] single rank and full DQ!
              [204]ddr_efuse_type: 0xa
              [206]trefi:7.8ms
              [208][AUTO DEBUG] rank 0 row = 13
              [211][AUTO DEBUG] rank 0 bank = 4
              [215][AUTO DEBUG] rank 0 page size = 2 KB
              [218]DRAM BOOT DRIVE INFO: V0.33
              [221]DRAM CLK = 528 MHz
              [224]DRAM Type = 2 (2:DDR2,3:DDR3)
              [227]DRAMC read ODT off.
              [229]DRAM ODT off.
              [231]ddr_efuse_type: 0xa
              [234]DRAM SIZE =64 M
              [236]dram_tpr4:0x0
              [238]PLL_DDR_CTRL_REG:0xf8002b00
              [241]DRAM_CLK_REG:0xc0000000
              [243][TIMING DEBUG] MR2= 0x0
              [248]DRAM simple test OK.
              [250]dram size =64
              [252]card no is 0
              [254]sdcard 0 line count 4
              [256][mmc]: mmc driver ver 2021-04-2 16:45
              [266][mmc]: Wrong media type 0x0
              [268][mmc]: Try SD card 0
              [279][mmc]: HSSDR52/SDR25 4 bit
              [281][mmc]: 50000000 Hz
              [284][mmc]: 7681 MB
              [285][mmc]: SD/MMC 0 init OK!!!
              [337]Loading boot-pkg Succeed(index=0).
              [341]Entry_name = opensbi
              [344]Entry_name = u-boot
              [348]Entry_name = dtb
              [350]mmc not para

              U-Boot 2018.05-g24521d6 (Feb 11 2022 - 08:52:39 +0000) Allwinner Technology

              [00.361]DRAM: 64 MiB
              [00.364]Relocation Offset is: 01ee7000
              [00.368]secure enable bit: 0
              [00.371]CPU=720 MHz,PLL6=600 Mhz,AHB=200 Mhz, APB1=100Mhz MBus=300Mhz
              [00.377]flash init start
              [00.380]workmode = 0,storage type = 1
              [00.383][mmc]: mmc driver ver uboot2018:2021-11-19 15:38:00
              [00.389][mmc]: get sdc_type fail and use default host:tm1.
              [00.395][mmc]: can't find node "mmc0",will add new node
              [00.400][mmc]: fdt err returned <no error>
              [00.404][mmc]: Using default timing para
              [00.408][mmc]: SUNXI SDMMC Controller Version:0x50310
              [00.426][mmc]: card_caps:0x3000000a
              [00.429][mmc]: host_caps:0x3000003f
              [00.433]sunxi flash init ok
              [00.436]line:703 init_clocks
              [00.439]drv_disp_init
              request pwm success, pwm7:pwm7:0x2000c00.
              [00.460]drv_disp_init finish
              [00.463]boot_gui_init:start
              [00.466]set disp.dev2_output_type fail. using defval=0
              [00.473]boot_gui_init:finish
              partno erro : can't find partition bootloader
              54 bytes read in 2 ms (26.4 KiB/s)
              [00.511]bmp_name=bootlogo.bmp size 38454
              38454 bytes read in 5 ms (7.3 MiB/s)
              [00.552]Loading Environment from SUNXI_FLASH... OK
              [00.576]out of usb burn from boot: not need burn key
              [00.611]Item0 (Map) magic is bad
              [00.614]the secure storage item0 copy0 magic is bad
              [00.649]Item0 (Map) magic is bad
              [00.[00.654]LCD open finish
              652]the secure storage item0 copy1 magic is bad
              [00.660]Item0 (Map) magic is bad
              partno erro : can't find partition private
              root_partition is rootfs
              set root to /dev/mmcblk0p5
              [00.676]update part info
              [00.681]update bootcmd
              [00.686]change working_fdt 0x42aa6da0 to 0x42a86da0
              disable nand error: FDT_ERR_BADPATH
              No reserved memory region found in source FDT
              [00.723]update dts
              noncached_alloc(): addr = 0x42b12b80
              noncached_alloc(): addr = 0x42b12bc0
              noncached_alloc(): addr = 0x42c8a040
              noncached_alloc(): addr = 0x42c8a880

              1 条回复 最后回复 回复 引用 分享 0
              • D
                daMing123 LV 5 @YuzukiTsuru 最后由 编辑

                @yuzukitsuru 试试,我已经解决了,在board.dts中,有个引脚占用了,我修改了下,就行了。

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