【求助】LCD RGB18 部分引脚被占用应该如何释放
-
这个是rgb18的引脚定义：
rgb18_pins_a: rgb18@0 { pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", \ "PD6", "PD7", "PD8", "PD9", "PD10", "PD11", \ "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", \ "PD18", "PD19", "PD20", "PD21"; function = "lcd0"; drive-strength = <30>; bias-disable; };在系统启动时LCD驱动程序报错如下：主要是因为PD19引脚被占用导致引脚申请失败
[ 5.809429] [DISP]disp_module_init [ 5.814103] disp 5000000.disp: Adding to iommu group 0 [ 5.845304] disp 5000000.disp: 5000000.disp supply vcc-lcd not found, using dummy regulator [ 5.855057] disp 5000000.disp: 5000000.disp supply vcc-pd not found, using dummy regulator [ 5.875786] display_fb_request,fb_id:0 [ 5.886234] [DISP] Fb_copy_boot_fb,line:1443: [ 5.886240] no boot_fb0 [ 5.894393] disp_al_manager_apply ouput_type:0 [ 5.900737] [DISP]disp_module_init finish [ 5.905298] [DISP] lcd_clk_config,line:732: [ 5.905310] disp 0, clk: pll(114000000),clk(114000000),dclk(19000000) dsi_rate(114000000) [ 5.905310] clk real:pll(288000000),clk(288000000),dclk(48000000) dsi_rate(0) [ 5.963933] =====================LCD_open_flow [ 5.968892] =====================LCD_power_on [ 5.974983] sun8iw20-pinctrl 2000000.pinctrl: pin PD19 already requested by 2000000.pinctrl:115; cannot claim for 1c0c000.lcd0 [ 6.031543] sun8iw20-pinctrl 2000000.pinctrl: pin-115 (1c0c000.lcd0) status -22 [ 6.039701] sun8iw20-pinctrl 2000000.pinctrl: could not request pin 115 (PD19) from group PD19 on device 2000000.pinctrl [ 6.091538] platform 1c0c000.lcd0: Error applying setting, reverse things back [ 6.099618] [DISP] disp_sys_pin_set_state,line:395: [ 6.099622] pinctrl_select_state(active) for allwinner,sunxi-lcd0 fail [ 6.181549] =====================LCD_panel_init这个是进入系统后打印的引脚信息：
root@TinaLinux:/# cat /sys/kernel/debug/pinctrl/2000000.pinctrl/pinmux-pins Pinmux settings per pin Format: pin (name): mux_owner|gpio_owner (strict) hog? pin 32 (PB0): device 2502800.twi function gpio_in group PB0 pin 33 (PB1): device 2502800.twi function gpio_in group PB1 pin 34 (PB2): UNCLAIMED pin 35 (PB3): UNCLAIMED pin 36 (PB4): UNCLAIMED pin 37 (PB5): UNCLAIMED pin 38 (PB6): UNCLAIMED pin 39 (PB7): UNCLAIMED pin 40 (PB8): device 2500000.uart function uart0 group PB8 pin 41 (PB9): device 2500000.uart function uart0 group PB9 pin 42 (PB10): device 2031000.dmic function io_disabled group PB10 pin 43 (PB11): device 2031000.dmic function io_disabled group PB11 pin 44 (PB12): UNCLAIMED pin 64 (PC0): device 2008000.ledc function ledc group PC0 pin 65 (PC1): UNCLAIMED pin 66 (PC2): UNCLAIMED pin 67 (PC3): UNCLAIMED pin 68 (PC4): UNCLAIMED pin 69 (PC5): UNCLAIMED pin 70 (PC6): UNCLAIMED pin 71 (PC7): UNCLAIMED pin 96 (PD0): UNCLAIMED pin 97 (PD1): UNCLAIMED pin 98 (PD2): UNCLAIMED pin 99 (PD3): UNCLAIMED pin 100 (PD4): UNCLAIMED pin 101 (PD5): UNCLAIMED pin 102 (PD6): UNCLAIMED pin 103 (PD7): UNCLAIMED pin 104 (PD8): UNCLAIMED pin 105 (PD9): UNCLAIMED pin 106 (PD10): UNCLAIMED pin 107 (PD11): UNCLAIMED pin 108 (PD12): UNCLAIMED pin 109 (PD13): UNCLAIMED pin 110 (PD14): UNCLAIMED pin 111 (PD15): UNCLAIMED pin 112 (PD16): UNCLAIMED pin 113 (PD17): UNCLAIMED pin 114 (PD18): UNCLAIMED pin 115 (PD19): GPIO 2000000.pinctrl:115 pin 116 (PD20): GPIO 2000000.pinctrl:116 pin 117 (PD21): GPIO 2000000.pinctrl:117 pin 118 (PD22): UNCLAIMED pin 128 (PE0): UNCLAIMED pin 129 (PE1): UNCLAIMED pin 130 (PE2): UNCLAIMED pin 131 (PE3): UNCLAIMED pin 132 (PE4): UNCLAIMED pin 133 (PE5): UNCLAIMED pin 134 (PE6): UNCLAIMED pin 135 (PE7): UNCLAIMED pin 136 (PE8): UNCLAIMED pin 137 (PE9): UNCLAIMED pin 138 (PE10): UNCLAIMED pin 139 (PE11): UNCLAIMED pin 140 (PE12): UNCLAIMED pin 141 (PE13): UNCLAIMED pin 142 (PE14): device 2031000.dmic function io_disabled group PE14 pin 143 (PE15): UNCLAIMED pin 144 (PE16): UNCLAIMED pin 145 (PE17): device 2031000.dmic function io_disabled group PE17 pin 160 (PF0): device 4020000.sdmmc function sdc0 group PF0 pin 161 (PF1): device 4020000.sdmmc function sdc0 group PF1 pin 162 (PF2): device 4020000.sdmmc function sdc0 group PF2 pin 163 (PF3): device 4020000.sdmmc function sdc0 group PF3 pin 164 (PF4): device 4020000.sdmmc function sdc0 group PF4 pin 165 (PF5): device 4020000.sdmmc function sdc0 group PF5 pin 166 (PF6): GPIO 2000000.pinctrl:166 pin 192 (PG0): device 4021000.sdmmc function gpio_in group PG0 pin 193 (PG1): device 4021000.sdmmc function gpio_in group PG1 pin 194 (PG2): device 4021000.sdmmc function gpio_in group PG2 pin 195 (PG3): device 4021000.sdmmc function gpio_in group PG3 pin 196 (PG4): device 4021000.sdmmc function gpio_in group PG4 pin 197 (PG5): device 4021000.sdmmc function gpio_in group PG5 pin 198 (PG6): device 2500400.uart function uart1 group PG6 pin 199 (PG7): device 2500400.uart function uart1 group PG7 pin 200 (PG8): device 2500400.uart function uart1 group PG8 pin 201 (PG9): device 2500400.uart function uart1 group PG9 pin 202 (PG10): GPIO 2000000.pinctrl:202 pin 203 (PG11): device soc@3000000:rfkill@0 function clk_fanout1 group PG11 pin 204 (PG12): GPIO 2000000.pinctrl:204 pin 205 (PG13): UNCLAIMED pin 206 (PG14): UNCLAIMED pin 207 (PG15): UNCLAIMED pin 208 (PG16): GPIO 2000000.pinctrl:208 pin 209 (PG17): GPIO 2000000.pinctrl:209 pin 210 (PG18): GPIO 2000000.pinctrl:210打印信息没显示PD19、PD20、PD21三个引脚是被哪个设备占用了，dts文件里除了rgb使用了PD19、PD20、PD21，别的地方都没再使用
文件：lichee/linux-5.4/arch/riscv/boot/dts/sunxi/sun20iw1p1.dtsi/* * Allwinner Technology CO., Ltd. sun20iw1p1 platform. * */ /memreserve/ 0x41fc0000 0x020000; /* opensbi */ #include <dt-bindings/clock/sun8iw20-ccu.h> #include <dt-bindings/clock/sun8iw20-r-ccu.h> #include <dt-bindings/clock/sun8iw20-rtc.h> #include <dt-bindings/reset/sun8iw20-ccu.h> #include <dt-bindings/reset/sun8iw20-r-ccu.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/gpio/sun4i-gpio.h> #include <dt-bindings/thermal/thermal.h> / { model = "sun20iw1p1"; compatible = "allwinner,sun20iw1p1"; #address-cells = <2>; #size-cells = <2>; aliases { serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; serial3 = &uart3; serial4 = &uart4; serial5 = &uart5; spi0 = &spi0; spi1 = &spi1; twi0 = &twi0; twi1 = &twi1; twi2 = &twi2; twi3 = &twi3; mmc2 = &sdc2; pwm0 = &pwm0; pwm1 = &pwm1; pwm2 = &pwm2; pwm3 = &pwm3; pwm4 = &pwm4; pwm5 = &pwm5; pwm6 = &pwm6; pwm7 = &pwm7; ir0 = &s_cir0; ir1 = &ir1; mmc0 = &sdc0; ve0 = &ve; tvd = &tvd; tvd0 = &tvd0; } ; chosen { bootargs = "console=ttyS0,115200n8 debug loglevel=7,initcall_debug=1 init=/init earlycon=sbi"; stdout-path = "serial0:115200n8"; linux,initrd-start = <0x42000000>; linux,initrd-end = <0x43000000>; }; cpus { #address-cells = <1>; #size-cells = <0>; timebase-frequency = <24000000>; idle-states { CPU_SLEEP: cpu-sleep { compatible = "riscv,idle-state"; local-timer-stop; entry-latency-us = <59>; exit-latency-us = <59>; min-residency-us = <5000>; }; }; CPU0: cpu@0 { device_type = "cpu"; reg = <0>; status = "okay"; compatible = "riscv"; riscv,isa = "rv64imafdcvsu"; /* riscv,priv-major = <1>;*/ /* riscv,priv-minor = <10>;*/ mmu-type = "riscv,sv39"; clocks = <&ccu CLK_RISCV>; clock-frequency = <24000000>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP>; #cooling-cells = <2>; /* d-cache-size = <0x8000>;*/ /* d-cache-line-size = <32>;*/ CPU0_intc: interrupt-controller { #interrupt-cells = <1>; interrupt-controller; compatible = "riscv,cpu-intc"; }; }; }; dram: dram { device_type = "dram"; compatible = "allwinner,dram"; clocks = <&ccu CLK_PLL_DDR0>; clock-names = "pll_ddr"; }; memory@40000000 { device_type = "memory"; reg = <0x0 0x40000000 0x0 0x8000000>; }; dump_reg: dump_reg@20000 { compatible = "allwinner,sunxi-dump-reg"; reg = <0x0 0x00020000 0x0 0x0004>; /* 0x00020000: dump_reg test addr, 0x0004: dump_reg test size */ }; cpu_opp_table: cpu-opp-table { compatible = "allwinner,sun50i-operating-points"; nvmem-cells = <&speedbin_efuse>, <&cpubin_efuse>; nvmem-cell-names = "speed", "bin"; opp-shared; opp@1008000000 { opp-hz = /bits/ 64 <1008000000>; clock-latency-ns = <244144>; /* 8 32k periods */ opp-microvolt-a0 = <1100000>; opp-microvolt-a1 = <950000>; opp-microvolt-b1 = <950000>; opp-supported-hw = <0x1>; }; }; dcxo24M: dcxo24M_clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; clock-output-names = "dcxo24M"; }; rc_16m: rc16m_clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <16000000>; clock-accuracy = <300000000>; clock-output-names = "rc-16m"; }; ext_32k: ext32k_clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; clock-output-names = "ext-32k"; }; reg_pio1_8: pio-18 { compatible = "regulator-fixed"; regulator-name = "pio-18"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; reg_pio3_3: pio-33 { compatible = "regulator-fixed"; regulator-name = "pio-33"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; thermal-zones { cpu_thermal_zone { polling-delay-passive = <500>; polling-delay = <1000>; thermal-sensors = <&ths 0>; sustainable-power = <1200>; cpu_trips: trips { cpu_threshold: trip-point@0 { temperature = <70000>; type = "passive"; hysteresis = <0>; }; cpu_target: trip-point@1 { temperature = <90000>; type = "passive"; hysteresis = <0>; }; cpu_crit: cpu_crit@0 { temperature = <110000>; type = "critical"; hysteresis = <0>; }; }; cooling-maps { map0 { trip = <&cpu_target>; cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; contribution = <1024>; }; }; }; }; mmu_aw: iommu@2010000 { compatible = "allwinner,sunxi-iommu"; reg = <0x0 0x02010000 0x0 0x1000>; interrupts-extended = <&plic0 80 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "iommu-irq"; clocks = <&ccu CLK_BUS_IOMMU>; clock-names = "iommu"; #iommu-cells = <2>; status = "okay"; }; soc: soc@3000000 { #address-cells = <2>; #size-cells = <2>; compatible = "simple-bus"; ranges; sram_ctrl: sram_ctrl@3000000 { compatible = "allwinner,sram_ctrl"; reg = <0x0 0x3000000 0 0x16C>; soc_ver { offset = <0x24>; mask = <0x7>; shift = <0>; ver_a = <0x18590000>; ver_b = <0x18590002>; ver_d = <0x18590003>; }; soc_id { offset = <0x200>; mask = <0x1>; shift = <22>; }; soc_bin { offset = <0x0>; mask = <0x3ff>; shift = <0x0>; }; }; rtc_ccu: rtc_ccu@7090000 { compatible = "allwinner,sun20iw1-rtc-ccu"; device_type = "rtc-ccu"; reg = <0x0 0x07090000 0x0 0x320>; /* The same as rtc */ #clock-cells = <1>; }; ccu: clock@2001000 { compatible = "allwinner,sun20iw1-ccu"; reg = <0x0 0x02001000 0x0 0x1000>; clocks = <&dcxo24M>, <&rtc_ccu CLK_OSC32K>, <&rtc_ccu CLK_IOSC>; clock-names = "hosc", "losc", "iosc"; #clock-cells = <1>; #reset-cells = <1>; }; r_ccu: clock@7010000 { compatible = "allwinner,sun20iw1-r-ccu"; reg = <0x0 0x07010000 0x0 0x240>; clocks = <&dcxo24M>, <&rtc_ccu CLK_OSC32K>, <&rtc_ccu CLK_IOSC>, <&ccu CLK_PLL_PERIPH0>; clock-names = "hosc", "losc", "iosc", "pll-periph0"; #clock-cells = <1>; #reset-cells = <1>; }; plic0: interrupt-controller@10000000 { compatible = "riscv,plic0"; #address-cells = <2>; #interrupt-cells = <2>; interrupt-controller; reg = <0x0 0x10000000 0x0 0x4000000>; interrupts-extended = <&CPU0_intc 0xffffffff &CPU0_intc 9>; reg-names = "control"; riscv,max-priority = <7>; riscv,ndev=<200>; }; uart0: uart@2500000 { compatible = "allwinner,sun20i-uart"; device_type = "uart0"; reg = <0x0 0x02500000 0x0 0x400>; interrupts-extended = <&plic0 18 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_UART0>; clock-names = "uart0"; resets = <&ccu RST_BUS_UART0>; sunxi,uart-fifosize = <64>; uart0_port = <0>; uart0_type = <2>; status = "okay"; }; uart1: uart@2500400 { compatible = "allwinner,sun20i-uart"; device_type = "uart1"; reg = <0x0 0x02500400 0x0 0x400>; interrupts-extended = <&plic0 19 IRQ_TYPE_LEVEL_HIGH>; sunxi,uart-fifosize = <256>; clocks = <&ccu CLK_BUS_UART1>; clock-names = "uart1"; resets = <&ccu RST_BUS_UART1>; uart1_port = <1>; uart1_type = <4>; status = "disabled"; }; uart2: uart@2500800 { compatible = "allwinner,sun20i-uart"; device_type = "uart2"; reg = <0x0 0x02500800 0x0 0x400>; interrupts-extended = <&plic0 20 IRQ_TYPE_LEVEL_HIGH>; sunxi,uart-fifosize = <256>; clocks = <&ccu CLK_BUS_UART2>; clock-names = "uart2"; resets = <&ccu RST_BUS_UART2>; uart2_port = <2>; uart2_type = <4>; status = "disabled"; }; uart3: uart@2500c00 { compatible = "allwinner,sun20i-uart"; device_type = "uart3"; reg = <0x0 0x02500c00 0x0 0x400>; interrupts-extended = <&plic0 21 IRQ_TYPE_LEVEL_HIGH>; sunxi,uart-fifosize = <256>; clocks = <&ccu CLK_BUS_UART3>; clock-names = "uart3"; resets = <&ccu RST_BUS_UART3>; uart3_port = <3>; uart3_type = <4>; status = "disabled"; }; uart4: uart@2501000 { compatible = "allwinner,sun20i-uart"; device_type = "uart4"; reg = <0x0 0x02501000 0x0 0x400>; interrupts-extended = <&plic0 22 IRQ_TYPE_LEVEL_HIGH>; sunxi,uart-fifosize = <256>; clocks = <&ccu CLK_BUS_UART4>; clock-names = "uart4"; resets = <&ccu RST_BUS_UART4>; uart4_port = <4>; uart4_type = <2>; status = "disabled"; }; uart5: uart@2501400 { compatible = "allwinner,sun20i-uart"; device_type = "uart5"; reg = <0x0 0x02501400 0x0 0x400>; interrupts-extended = <&plic0 23 IRQ_TYPE_LEVEL_HIGH>; sunxi,uart-fifosize = <256>; clocks = <&ccu CLK_BUS_UART5>; clock-names = "uart5"; resets = <&ccu RST_BUS_UART5>; uart5_port = <5>; uart5_type = <2>; status = "disabled"; }; cryptoengine: ce@03040000 { compatible = "allwinner,sunxi-ce"; device_name = "ce"; reg = <0x0 0x03040000 0x0 0xa0>, /* non-secure space */ <0x0 0x03040800 0x0 0xa0>; /* secure space */ interrupts-extended = <&plic0 68 IRQ_TYPE_EDGE_RISING>, /*non-secure*/ <&plic0 69 IRQ_TYPE_EDGE_RISING>; /* secure*/ clock-frequency = <400000000>; /* 400MHz */ clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>, <&ccu CLK_MBUS_CE>, <&ccu CLK_PLL_PERIPH0_2X>; clock-names = "bus_ce", "ce_clk", "mbus_ce", "pll_periph0_2x"; resets = <&ccu RST_BUS_CE>; status = "okay"; }; s_cir0: s_cir@7040000 { compatible = "allwinner,s_cir"; reg = <0x0 0x07040000 0x0 0x400>; interrupts-extended = <&plic0 167 IRQ_TYPE_LEVEL_HIGH>; clocks = <&r_ccu CLK_R_APB0_BUS_IRRX>, <&dcxo24M>, <&r_ccu CLK_R_APB0_IRRX>; clock-names = "bus", "pclk", "mclk"; resets = <&r_ccu RST_R_APB0_BUS_IRRX>; supply = ""; supply_vol = ""; status = "disabled"; }; ir1: ir@2003000 { compatible = "allwinner,irtx"; reg = <0x0 0x02003000 0x0 0x400>; interrupts-extended = <&plic0 35 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_IR_TX>, <&dcxo24M>, <&ccu CLK_IR_TX>; clock-names = "bus", "pclk", "mclk"; resets = <&ccu RST_BUS_IR_TX>; status = "disabled"; }; di: deinterlace@5400000 { compatible = "allwinner,sunxi-deinterlace"; reg = <0x0 0x05400000 0x0 0x0000ffff>; interrupts-extended = <&plic0 104 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_DI>, <&ccu CLK_BUS_DI>, <&ccu CLK_PLL_PERIPH0_2X>; clock-names = "clk_di", "pll_periph", "clk_bus_di"; resets = <&ccu RST_BUS_DI>; reset-names = "rst_bus_di"; assigned-clocks = <&ccu CLK_DI>; assigned-clock-parents = <&ccu CLK_PLL_PERIPH0_2X>; assigned-clock-rates = <300000000>; iommus = <&mmu_aw 4 1>; status = "okay"; }; gmac0: eth@4500000 { compatible = "allwinner,sunxi-gmac"; reg = <0x0 0x04500000 0x0 0x10000>, <0x0 0x03000030 0x0 0x4>; interrupts-extended = <&plic0 62 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "gmacirq"; clocks = <&ccu CLK_BUS_EMAC0>, <&ccu CLK_EMAC0_25M>; clock-names = "gmac", "ephy"; resets = <&ccu RST_BUS_EMAC0>; device_type = "gmac0"; pinctrl-0 = <&gmac_pins_a>; pinctrl-1 = <&gmac_pins_b>; pinctrl-names = "default", "sleep"; phy-mode = "rgmii"; use_ephy25m = <1>; tx-delay = <7>; rx-delay = <31>; phy-rst = <&pio PA 14 GPIO_ACTIVE_LOW>; gmac-power0; gmac-power1; gmac-power2; status = "disabled"; }; rtc: rtc@7090000 { compatible = "allwinner,sun20iw1-rtc"; device_type = "rtc"; wakeup-source; interrupts-extended = <&plic0 160 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0x07090000 0x0 0x320>; clocks = <&r_ccu CLK_R_AHB_BUS_RTC>, <&rtc_ccu CLK_RTC_SPI>, <&rtc_ccu CLK_RTC_1K>; clock-names = "r-ahb-rtc", "rtc-spi", "rtc-1k"; resets = <&r_ccu RST_R_AHB_BUS_RTC>; gpr_cur_pos = <6>; }; dma: dma-controller@3002000 { compatible = "allwinner,sun8i-riscv-dma"; reg = <0x0 0x03002000 0x0 0x1000>; interrupts-extended = <&plic0 66 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; clock-names = "bus", "mbus"; resets = <&ccu RST_BUS_DMA>; dma-channels = <8>; dma-requests = <48>; #dma-cells = <1>; status = "okay"; }; soc_timer0: timer@2050000 { compatible = "allwinner,sun4i-a10-timer"; device_type = "soc_timer"; reg = <0x0 0x02050000 0x0 0xA0>; interrupts-extended = <&plic0 75 IRQ_TYPE_LEVEL_HIGH>; clocks = <&dcxo24M>; status = "okay"; }; wdt: watchdog@6011000 { compatible = "allwinner,sun20i-wdt"; reg = <0x0 0x06011000 0x0 0x20>; interrupts-extended = <&plic0 147 IRQ_TYPE_LEVEL_HIGH>; }; mbus0:mbus-comtroller@3102000 { compatible = "allwinner,sun8i-mbus"; reg = <0x0 0x03102000 0x0 0x1000>; #mbus-cells = <1>; }; pmu: pmu { compatible = "riscv,c910_pmu"; }; ilde: idle { compatible = "riscv,idle"; }; pio: pinctrl@2000000 { compatible = "allwinner,sun20iw1-pinctrl"; reg = <0x0 0x02000000 0x0 0x500>; interrupts-extended = <&plic0 85 IRQ_TYPE_LEVEL_HIGH>, <&plic0 87 IRQ_TYPE_LEVEL_HIGH>, <&plic0 89 IRQ_TYPE_LEVEL_HIGH>, <&plic0 91 IRQ_TYPE_LEVEL_HIGH>, <&plic0 93 IRQ_TYPE_LEVEL_HIGH>, <&plic0 95 IRQ_TYPE_LEVEL_HIGH>; device_type = "pio"; clocks = <&ccu CLK_APB0>, <&dcxo24M>, <&rtc_ccu CLK_OSC32K>; clock-names = "apb", "hosc", "losc"; gpio-controller; #gpio-cells = <3>; interrupt-controller; #interrupt-cells = <3>; #size-cells = <0>; vcc-pf-supply = <®_pio1_8>; vcc-pfo-supply = <®_pio3_3>; test_pins_a: test_pins@0 { allwinner,pins = "PB0", "PB1"; allwinner,function = "test"; allwinner,muxsel = <0x7>; allwinner,drive = <1>; allwinner,pull = <1>; }; test_pins_b: test_pins@1 { pins = "PB0", "PB1"; function = "io_disabled"; allwinner,muxsel = <0xF>; allwinner,drive = <1>; allwinner,pull = <1>; }; gmac_pins_a: gmac@0 { pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7", "PA8", "PA10", "PA11", "PA12", "PA13", "PA17", "PA18", "PA28", "PA29", "PA30", "PA31"; function = "gmac0"; drive-strength = <10>; }; gmac_pins_b: gmac@1 { pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7", "PA8", "PA10", "PA11", "PA12", "PA13", "PA17", "PA18", "PA28", "PA29", "PA30", "PA31"; function = "gpio_in"; drive-strength = <10>; }; ir1_pins_a: ir1@0 { /* For FPGA board */ pins = "PG11"; function = "ir1"; drive-strength = <10>; }; csi_mclk0_pins_a: csi_mclk0@0 { pins = "PE3"; function = "csi0"; drive-strength = <10>; }; csi_mclk0_pins_b: csi_mclk0@1 { pins = "PE3"; function = "gpio_in"; }; csi0_pins_a: csi0@0 { pins = "PE2", "PE0", "PE1", "PE4", "PE5", "PE6", "PE7", "PE8", "PE9", "PE10", "PE11"; function = "ncsi0"; drive-strength = <10>; }; csi0_pins_b: csi0@1 { pins = "PE2", "PE0", "PE1", "PE4", "PE5", "PE6", "PE7", "PE8", "PE9", "PE10", "PE11"; function = "io_disabled"; drive-strength = <10>; }; lvds0_pins_a: lvds0@0 { pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9"; function = "lvds0"; drive-strength = <30>; bias-disable; }; lvds0_pins_b: lvds0@1 { pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9"; function = "io_disabled"; drive-strength = <30>; bias-disable; }; rgb24_pins_a: rgb24@0 { pins = "PB2", "PB3", "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", \ "PB4", "PB5", "PD6", "PD7", "PD8", "PD9", "PD10", "PD11", \ "PB6", "PB7", "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", \ "PD18", "PD19", "PD20", "PD21"; function = "lcd0"; drive-strength = <30>; bias-disable; }; rgb24_pins_b: rgb24@1 { pins = "PB2", "PB3", "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", \ "PB4", "PB5", "PD6", "PD7", "PD8", "PD9", "PD10", "PD11", \ "PB6", "PB7", "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", \ "PD18", "PD19", "PD20", "PD21"; function = "io_disabled"; bias-disable; }; rgb18_pins_a: rgb18@0 { pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", \ "PD6", "PD7", "PD8", "PD9", "PD10", "PD11", \ "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", \ "PD18", "PD19", "PD20", "PD21"; function = "lcd0"; drive-strength = <30>; bias-disable; }; rgb18_pins_b: rgb18@1 { pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", \ "PD6", "PD7", "PD8", "PD9", "PD10", "PD11", \ "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", \ "PD18", "PD19", "PD20", "PD21"; function = "io_disabled"; bias-disable; }; dsi2lane_pins_a: dsi2lane@0 { pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5"; function = "dsi"; drive-strength = <30>; bias-disable; }; dsi2lane_pins_b: dsi2lane@1 { pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5"; function = "io_disabled"; bias-disable; }; dsi4lane_pins_a: dsi4lane@0 { pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9"; function = "dsi"; drive-strength = <30>; bias-disable; }; dsi4lane_pins_b: dsi4lane@1 { pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9"; function = "io_disabled"; bias-disable; }; }; spi0: spi@4025000 { #address-cells = <1>; #size-cells = <0>; compatible = "allwinner,sun20i-spi"; device_type = "spi0"; reg = <0x0 0x04025000 0x0 0x300>; interrupts-extended = <&plic0 31 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_PLL_PERIPH0>, <&ccu CLK_SPI0>, <&ccu CLK_BUS_SPI0>; clock-names = "pll", "mod", "bus"; resets = <&ccu RST_BUS_SPI0>; clock-frequency = <100000000>; pinctrl-names = "default", "sleep"; spi0_cs_number = <1>; spi0_cs_bitmap = <1>; dmas = <&dma 22>, <&dma 22>; dma-names = "tx", "rx"; status = "disabled"; }; spi1: spi@4026000 { #address-cells = <1>; #size-cells = <0>; compatible = "allwinner,sun20i-spi"; reg = <0x0 0x04026000 0x0 0x1000>; interrupts-extended = <&plic0 32 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_PLL_PERIPH0>, <&ccu CLK_SPI1>, <&ccu CLK_BUS_SPI1>; clock-names = "pll", "mod", "bus"; resets = <&ccu RST_BUS_SPI1>; clock-frequency = <100000000>; spi1_cs_number = <1>; spi1_cs_bitmap = <1>; dmas = <&dma 23>, <&dma 23>; dma-names = "tx", "rx"; status = "disabled"; }; twi0: twi@2502000 { #address-cells = <1>; #size-cells = <0>; compatible = "allwinner,sun20i-twi"; device_type = "twi0"; reg = <0x0 0x02502000 0x0 0x400>; interrupts-extended= <&plic0 25 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_I2C0>; resets = <&ccu RST_BUS_I2C0>; clock-names = "bus"; clock-frequency = <400000>; dmas = <&dma 43>, <&dma 43>; dma-names = "tx", "rx"; status = "disabled"; }; twi1: twi@2502400 { #address-cells = <1>; #size-cells = <0>; compatible = "allwinner,sun20i-twi"; device_type = "twi1"; reg = <0x0 0x02502400 0x0 0x400>; interrupts-extended= <&plic0 26 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_I2C1>; resets = <&ccu RST_BUS_I2C1>; clock-names = "bus"; clock-frequency = <200000>; dmas = <&dma 44>, <&dma 44>; dma-names = "tx", "rx"; status = "disabled"; }; twi2: twi@2502800 { #address-cells = <1>; #size-cells = <0>; compatible = "allwinner,sun20i-twi"; device_type = "twi2"; reg = <0x0 0x02502800 0x0 0x400>; interrupts-extended = <&plic0 27 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_I2C2>; resets = <&ccu RST_BUS_I2C2>; clock-names = "bus"; clock-frequency = <100000>; dmas = <&dma 45>, <&dma 45>; dma-names = "tx", "rx"; status = "disabled"; }; twi3: twi@2502c00 { #address-cells = <1>; #size-cells = <0>; compatible = "allwinner,sun20i-twi"; device_type = "twi3"; reg = <0x0 0x02502c00 0x0 0x400>; interrupts-extended = <&plic0 28 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_I2C3>; resets = <&ccu RST_BUS_I2C3>; clock-names = "bus"; clock-frequency = <100000>; dmas = <&dma 46>, <&dma 46>; dma-names = "tx", "rx"; status = "disabled"; }; ledc: ledc@2008000 { #address-cells = <1>; #size-cells = <0>; compatible = "allwinner,sunxi-leds"; reg = <0x0 0x02008000 0x0 0x400>; interrupts-extended = <&plic0 36 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "ledcirq"; clocks = <&ccu CLK_LEDC>, <&ccu CLK_BUS_LEDC>; clock-names = "clk_ledc", "clk_cpuapb"; dmas = <&dma 42>, <&dma 42>; dma-names = "rx", "tx"; resets = <&ccu RST_BUS_LEDC>; reset-names = "ledc_reset"; status = "disable"; }; pwm: pwm@2000c00 { #pwm-cells = <0x3>; compatible = "allwinner,sunxi-pwm"; reg = <0x0 0x02000c00 0x0 0x3ff>; clocks = <&ccu CLK_BUS_PWM>; resets = <&ccu RST_BUS_PWM>; pwm-number = <8>; pwm-base = <0x0>; sunxi-pwms = <&pwm0>, <&pwm1>, <&pwm2>, <&pwm3>, <&pwm4>, <&pwm5>, <&pwm6>, <&pwm7>; }; keyboard0: keyboard@2009800 { compatible = "allwinner,keyboard_1350mv"; reg = <0x0 0x02009800 0x0 0x400>; interrupts-extended = <&plic0 77 IRQ_TYPE_EDGE_RISING>; clocks = <&ccu CLK_BUS_LRADC>; resets = <&ccu RST_BUS_LRADC>; key_cnt = <5>; key0 = <210 115>; key1 = <410 114>; key2 = <590 139>; key3 = <750 28>; key4 = <880 172>; status = "disabled"; }; sid@3006000 { compatible = "allwinner,sun20iw1p1-sid", "allwinner,sunxi-sid"; reg = <0x0 0x03006000 0 0x1000>; #address-cells = <1>; #size-cells = <1>; chipid { reg = <0x0 0>; offset = <0x200>; size = <0x10>; }; oem { reg = <0x0 0>; offset = <0x238>; size = <0x8>; }; secure_status { reg = <0x0 0>; offset = <0x210>; size = <0x4>; }; speedbin_efuse: speedbin@00 { reg = <0x00 2>; }; cpubin_efuse: cpubin@28 { reg = <0x28 2>; }; ths_calib: calib@14 { reg = <0x14 8>; }; }; gpadc: gpadc@2009000 { compatible = "allwinner,sunxi-gpadc"; reg = <0x0 0x02009000 0x0 0x400>; interrupts-extended = <&plic0 73 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_GPADC>; clock-names = "bus"; resets = <&ccu RST_BUS_GPADC>; status = "okay"; }; ths: ths@02009400 { compatible = "allwinner,sun20iw1p1-ths"; reg = <0x0 0x02009400 0x0 0x400>; clocks = <&ccu CLK_BUS_THS>; clock-names = "bus"; resets = <&ccu RST_BUS_THS>; nvmem-cells = <&ths_calib>; nvmem-cell-names = "calibration"; #thermal-sensor-cells = <1>; }; tpadc: tpadc@2009c00 { compatible = "allwinner,tp_key"; reg = <0x0 0x02009c00 0x0 0x400>; interrupts-extended = <&plic0 78 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_TPADC>, <&ccu CLK_BUS_TPADC>; clock-names = "mod", "bus"; clock-frequency = <1000000>; resets = <&ccu RST_BUS_TPADC>; status = "disabled"; }; rtp:rtp@2009c00 { compatible = "allwinner,sun8i-ts"; reg = <0x0 0x02009c00 0x0 0x400>; clocks = <&ccu CLK_TPADC>, <&ccu CLK_BUS_TPADC>; clock-names = "mod", "bus"; clock-frequency = <1000000>; resets = <&ccu RST_BUS_TPADC>; interrupts-extended = <&plic0 78 IRQ_TYPE_LEVEL_HIGH>; }; /* codec addr: 0x02030000, the others is invalid to avoid build warining */ codec:codec@2030000 { #sound-dai-cells = <0>; compatible = "allwinner,sunxi-internal-codec"; reg = <0x0 0x02030000 0x0 0x34c>; clocks = <&ccu CLK_PLL_AUDIO0>, <&ccu CLK_PLL_AUDIO1_DIV5>, <&ccu CLK_AUDIO_DAC>, <&ccu CLK_AUDIO_ADC>, <&ccu CLK_BUS_AUDIO_CODEC>; clock-names = "pll_audio0", "pll_audio1_div5", "audio_clk_dac", "audio_clk_adc", "audio_clk_bus"; resets = <&ccu RST_BUS_AUDIO_CODEC>; rx_sync_en = <0x00>; device_type = "codec"; status = "disabled"; }; dummy_cpudai:dummy_cpudai@203034c { compatible = "allwinner,sunxi-dummy-cpudai"; reg = <0x0 0x0203034c 0x0 0x4>; tx_fifo_size = <128>; rx_fifo_size = <256>; dac_txdata = <0x02030020>; adc_txdata = <0x02030040>; playback_cma = <128>; capture_cma = <256>; device_type = "cpudai"; dmas = <&dma 7>, <&dma 7>; dma-names = "tx", "rx"; status = "disabled"; }; sndcodec:sound@2030340 { compatible = "allwinner,sunxi-codec-machine"; reg = <0x0 0x02030340 0x0 0x4>; interrupts-extended = <&plic0 41 IRQ_TYPE_LEVEL_HIGH>; sunxi,audio-codec = <&codec>; sunxi,cpudai-controller = <&dummy_cpudai>; device_type = "sndcodec"; status = "disabled"; }; sunxi_rpaf_dsp0:rpaf-dsp@203034c { compatible = "allwinner,rpaf-dsp0"; device_type = "sunxi_rpaf_dsp0"; dsp_id = <0x0>; status = "okay"; }; /* dmic addr: 0x02031000, the others is invalid to avoid build warining */ dmic:dmic@2031000{ #sound-dai-cells = <0>; compatible = "allwinner,sunxi-dmic"; reg = <0x0 0x02031000 0x0 0x50>; clocks = <&ccu CLK_PLL_AUDIO0>, <&ccu CLK_DMIC>, <&ccu CLK_BUS_DMIC>; clock-names = "pll_audio", "dmic", "dmic_bus"; resets = <&ccu RST_BUS_DMIC>; dmas = <&dma 8>; dma-names = "rx"; interrupts-extended = <&plic0 40 IRQ_TYPE_LEVEL_HIGH>; clk_parent = <0x1>; capture_cma = <256>; data_vol = <0xB0>; rx_chmap = <0x76543210>; rx_sync_en = <0x00>; device_type = "dmic"; status = "disabled"; }; dmic_codec:sound@2031050{ #sound-dai-cells = <0>; compatible = "dmic-codec"; reg = <0x0 0x02031050 0x0 0x4>; num-channels = <8>; status = "disabled"; }; sounddmic:sounddmic@2031060 { reg = <0x0 0x02031060 0x0 0x4>; compatible = "sunxi,simple-audio-card"; simple-audio-card,name = "snddmic"; simple-audio-card,capture_only; status = "disabled"; /* simple-audio-card,format = "i2s"; */ simple-audio-card,cpu { sound-dai = <&dmic>; }; simple-audio-card,codec { sound-dai = <&dmic_codec>; }; }; /* daudio0 addr: 0x02032000, the others is invalid to avoid build warining */ daudio0:daudio@2032000 { #sound-dai-cells = <0>; compatible = "allwinner,sunxi-daudio"; reg = <0x0 0x02032000 0x0 0xa0>; clocks = <&ccu CLK_PLL_AUDIO0>, <&ccu CLK_I2S0>, <&ccu CLK_BUS_I2S0>; clock-names = "pll_audio", "i2s0", "i2s0_bus"; resets = <&ccu RST_BUS_I2S0>; dmas = <&dma 3>, <&dma 3>; dma-names = "tx", "rx"; interrupts-extended = <&plic0 42 IRQ_TYPE_LEVEL_HIGH>; sign_extend = <0x00>; tx_data_mode = <0x00>; rx_data_mode = <0x00>; msb_lsb_first = <0x00>; pcm_lrck_period = <0x80>; slot_width_select = <0x20>; frametype = <0x00>; tdm_config = <0x01>; tdm_num = <0x00>; mclk_div = <0x00>; clk_parent = <0x01>; capture_cma = <128>; playback_cma = <128>; tx_num = <4>; tx_chmap1 = <0x76543210>; tx_chmap0 = <0xFEDCBA98>; rx_num = <4>; rx_chmap3 = <0x03020100>; rx_chmap2 = <0x07060504>; rx_chmap1 = <0x0B0A0908>; rx_chmap0 = <0x0F0E0D0C>; asrc_function_en = <0x00>; rx_sync_en = <0x00>; device_type = "daudio0"; status = "disabled"; }; sounddaudio0: sounddaudio0@20320a0 { reg = <0x0 0x020320a0 0x0 0x4>; compatible = "sunxi,simple-audio-card"; simple-audio-card,name = "snddaudio0"; simple-audio-card,format = "i2s"; status = "disabled"; /* simple-audio-card,frame-master = <&daudio0_master>; */ /* simple-audio-card,bitclock-master = <&daudio0_master>; */ /* simple-audio-card,bitclock-inversion; */ /* simple-audio-card,frame-inversion; */ simple-audio-card,cpu { sound-dai = <&daudio0>; }; }; /* daudio1 addr: 0x02033000, the others is invalid to avoid build warining */ daudio1:daudio@2033000 { #sound-dai-cells = <0>; compatible = "allwinner,sunxi-daudio"; reg = <0x0 0x02033000 0x0 0xa0>; clocks = <&ccu CLK_PLL_AUDIO0>, <&ccu CLK_I2S1>, <&ccu CLK_BUS_I2S1>; clock-names = "pll_audio", "i2s1", "i2s1_bus"; resets = <&ccu RST_BUS_I2S1>; dmas = <&dma 4>, <&dma 4>; dma-names = "tx", "rx"; interrupts-extended = <&plic0 43 IRQ_TYPE_LEVEL_HIGH>; sign_extend = <0x00>; tx_data_mode = <0x00>; rx_data_mode = <0x00>; msb_lsb_first = <0x00>; pcm_lrck_period = <0x80>; slot_width_select = <0x20>; frametype = <0x00>; tdm_config = <0x01>; tdm_num = <0x01>; mclk_div = <0x00>; clk_parent = <0x01>; capture_cma = <128>; playback_cma = <128>; tx_num = <4>; tx_chmap1 = <0x76543210>; tx_chmap0 = <0xFEDCBA98>; rx_num = <4>; rx_chmap3 = <0x03020100>; rx_chmap2 = <0x07060504>; rx_chmap1 = <0x0B0A0908>; rx_chmap0 = <0x0F0E0D0C>; asrc_function_en = <0x00>; rx_sync_en = <0x00>; device_type = "daudio1"; status = "disabled"; }; sounddaudio1: sounddaudio1@20330a0 { reg = <0x0 0x020330a0 0x0 0x4>; compatible = "sunxi,simple-audio-card"; simple-audio-card,name = "snddaudio1"; simple-audio-card,format = "i2s"; status = "disabled"; simple-audio-card,cpu { sound-dai = <&daudio1>; }; }; /* daudio2 addr: 0x02034000, the others is invalid to avoid build warining */ daudio2:daudio@2034000 { #sound-dai-cells = <0>; compatible = "allwinner,sunxi-daudio"; reg = <0x0 0x02034000 0x0 0xa0>; clocks = <&ccu CLK_PLL_AUDIO0>, <&ccu CLK_I2S2>, <&ccu CLK_BUS_I2S2>, <&ccu CLK_PLL_AUDIO0_4X>, <&ccu CLK_I2S2_ASRC>; resets = <&ccu RST_BUS_I2S2>; dmas = <&dma 5>, <&dma 5>; dma-names = "tx", "rx"; interrupts-extended = <&plic0 44 IRQ_TYPE_LEVEL_HIGH>; sign_extend = <0x00>; tx_data_mode = <0x00>; rx_data_mode = <0x00>; msb_lsb_first = <0x00>; pcm_lrck_period = <0x80>; slot_width_select = <0x20>; frametype = <0x00>; tdm_config = <0x01>; tdm_num = <0x02>; mclk_div = <0x01>; clk_parent = <0x01>; capture_cma = <128>; playback_cma = <128>; tx_num = <4>; tx_chmap1 = <0x76543210>; tx_chmap0 = <0xFEDCBA98>; rx_num = <4>; rx_chmap3 = <0x03020100>; rx_chmap2 = <0x07060504>; rx_chmap1 = <0x0B0A0908>; rx_chmap0 = <0x0F0E0D0C>; asrc_function_en = <0x00>; rx_sync_en = <0x00>; device_type = "daudio2"; status = "disabled"; }; sounddaudio2: sounddaudio2@20340a0 { reg = <0x0 0x020340a0 0x0 0x4>; compatible = "sunxi,simple-audio-card"; simple-audio-card,name = "snddaudio2"; simple-audio-card,format = "i2s"; status = "disabled"; simple-audio-card,cpu { sound-dai = <&daudio2>; }; }; hdmiaudio: hdmiaudio@20340a4 { #sound-dai-cells = <0>; reg = <0x0 0x020340a4 0x0 0x4>; compatible = "allwinner,sunxi-hdmiaudio"; status = "disabled"; }; /* spdif addr: 0x02036000, the others is invalid to avoid build warining */ spdif:spdif@2036000 { #sound-dai-cells = <0>; compatible = "allwinner,sunxi-spdif"; reg = <0x0 0x02036000 0x0 0x58>; clocks = <&ccu CLK_PLL_AUDIO0_4X>, <&ccu CLK_SPDIF_TX>, <&ccu CLK_BUS_SPDIF>, <&ccu CLK_PLL_AUDIO1>, <&ccu CLK_PLL_AUDIO1_DIV5>, <&ccu CLK_PLL_PERIPH0>, <&ccu CLK_SPDIF_RX>; clock-names = "pll_audio0", "spdif", "spdif_bus", "pll_audio1", "pll_audio1_div5", "pll_periph","spdif_rx"; resets = <&ccu RST_BUS_SPDIF>; dmas = <&dma 2>, <&dma 2>; dma-names = "tx", "rx"; interrupts-extended = <&plic0 41 IRQ_TYPE_LEVEL_HIGH>; clk_parent = <0x1>; playback_cma = <128>; capture_cma = <128>; rx_sync_en = <0>; device_type = "spdif"; status = "disabled"; }; soundspdif:soundspdif@2036040 { reg = <0x0 0x02036040 0x0 0x4>; compatible = "sunxi,simple-audio-card"; simple-audio-card,name = "sndspdif"; status = "disabled"; /* simple-audio-card,format = "i2s"; */ simple-audio-card,cpu { sound-dai = <&spdif>; }; simple-audio-card,codec { /*snd-soc-dummy*/ }; }; g2d: g2d@5410000 { compatible = "allwinner,sunxi-g2d"; reg = <0x0 0x05410000 0x0 0x3ffff>; /* interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;*/ interrupts-extended = <&plic0 105 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_G2D>, <&ccu CLK_G2D>, <&ccu CLK_MBUS_G2D>; clock-names = "bus", "g2d", "mbus_g2d"; resets = <&ccu RST_BUS_G2D>; iommus = <&mmu_aw 3 1>; status = "okay"; }; disp: disp@5000000 { compatible = "allwinner,sunxi-disp"; reg = <0x0 0x05000000 0x0 0x3fffff>, /* de0 */ <0x0 0x05460000 0x0 0xfff>, /*display_if_top*/ <0x0 0x05461000 0x0 0xfff>, /* tcon-lcd0 */ <0x0 0x05470000 0x0 0xfff>, /* tcon-tv */ <0x0 0x05450000 0x0 0x1fff>; /* dsi0*/ /* interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,tcon-lcd0 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,tcon-tv <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;dsi*/ interrupts-extended = <&plic0 106 IRQ_TYPE_LEVEL_HIGH>, <&plic0 107 IRQ_TYPE_LEVEL_HIGH>, <&plic0 108 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_DE0>, <&ccu CLK_DE0>, <&ccu CLK_BUS_DE0>, <&ccu CLK_BUS_DE0>, <&ccu CLK_BUS_DPSS_TOP0>, <&ccu CLK_BUS_DPSS_TOP0>, <&ccu CLK_MIPI_DSI>, <&ccu CLK_BUS_MIPI_DSI>, <&ccu CLK_TCON_LCD0>, <&ccu CLK_TCON_TV>, <&ccu CLK_BUS_TCON_LCD0>, <&ccu CLK_BUS_TCON_TV>, <&ccu CLK_MIPI_DSI>, <&ccu CLK_BUS_MIPI_DSI>; clock-names = "clk_de0", "clk_de1", "clk_bus_de0", "clk_bus_de1", "clk_bus_dpss_top0", "clk_bus_dpss_top1", "clk_mipi_dsi0", "clk_bus_mipi_dsi0", "clk_tcon0", "clk_tcon1",/*tcon-tv actually*/ "clk_bus_tcon0", "clk_bus_tcon1",/*tcon-tv actually*/ "clk_mipi_dsi0", "clk_bus_mipi_dsi0"; resets = <&ccu RST_BUS_DE0>, <&ccu RST_BUS_DE0>, <&ccu RST_BUS_DPSS_TOP0>, <&ccu RST_BUS_DPSS_TOP0>, <&ccu RST_BUS_MIPI_DSI>, <&ccu RST_BUS_TCON_LCD0>, <&ccu RST_BUS_TCON_TV>, <&ccu RST_BUS_LVDS0>; reset-names = "rst_bus_de0", "rst_bus_de1", "rst_bus_dpss_top0", "rst_bus_dpss_top1", "rst_bus_mipi_dsi0", "rst_bus_tcon0", "rst_bus_tcon1", "rst_bus_lvds0"; assigned-clocks = <&ccu CLK_DE0>, <&ccu CLK_MIPI_DSI>, <&ccu CLK_TCON_LCD0>, <&ccu CLK_TCON_TV>; assigned-clock-parents = <&ccu CLK_PLL_PERIPH0_2X>, <&ccu CLK_PLL_PERIPH0>, <&ccu CLK_PLL_VIDEO0_4X>, <&ccu CLK_PLL_VIDEO1_4X>; assigned-clock-rates = <300000000>, <150000000>, <0>, <0>; boot_disp = <0>; boot_disp1 = <0>; boot_disp2 = <0>; fb_base = <0>; iommus = <&mmu_aw 2 0>; status = "okay"; }; ve: ve@1c0e000 { compatible = "allwinner,sunxi-cedar-ve"; reg = <0x0 0x01c0e000 0x0 0x1000>, <0x0 0x03000000 0x0 0x10>, <0x0 0x03001000 0x0 0x1000>; interrupts-extended = <&plic0 82 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, <&ccu CLK_MBUS_VE>; clock-names = "bus_ve", "ve", "mbus_ve"; resets = <&ccu RST_BUS_VE>; iommus = <&mmu_aw 0 1>; status = "okay"; }; msgbox: msgbox@0601f000 { compatible = "sunxi,msgbox-amp"; reg = <0x0 0x03003000 0x0 0x1000>, <0x0 0x01701000 0x0 0x1000>, <0x0 0x0601f000 0x0 0x1000>; interrupts-extended = <&plic0 144 IRQ_TYPE_LEVEL_HIGH>, <&plic0 102 IRQ_TYPE_LEVEL_HIGH>, <&plic0 140 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_MSGBOX2>; rpmsg_id = "sunxi,dsp-msgbox","sunxi,dsp-power-msgbox"; resets = <&ccu RST_BUS_MSGBOX2>; reset-names = "rst"; msgbox_amp_counts = <3>; msgbox_amp_local = <2>; rpmsg_amp_remote-0 = <1>; rpmsg_read_channel-0 = <2>; rpmsg_write_channel-0 = <2>; rpmsg_amp_remote-1 = <1>; rpmsg_read_channel-1 = <0>; rpmsg_write_channel-1 = <0>; }; lcd0: lcd0@1c0c000 { compatible = "allwinner,sunxi-lcd0"; reg = <0x0 0x1c0c000 0x0 0x0>; /* Fake registers to avoid dtc compiling warnings */ pinctrl-names = "active","sleep"; status = "okay"; }; sdc2: sdmmc@4022000 { compatible = "allwinner,sunxi-mmc-v4p6x"; device_type = "sdc2"; reg = <0x0 0x04022000 0x0 0x1000>; interrupts-extended = <&plic0 58 IRQ_TYPE_LEVEL_HIGH>; clocks = <&dcxo24M>, <&ccu CLK_PLL_PERIPH0_2X>, <&ccu CLK_MMC2>, <&ccu CLK_BUS_MMC2>; clock-names = "osc24m","pll_periph","mmc","ahb"; resets = <&ccu RST_BUS_MMC2>; reset-names = "rst"; pinctrl-names = "default","sleep"; pinctrl-0 = <&sdc2_pins_a>; pinctrl-1 = <&sdc2_pins_b>; bus-width = <4>; req-page-count = <2>; cap-mmc-highspeed; cap-cmd23; mmc-cache-ctrl; non-removable; /*max-frequency = <200000000>;*/ max-frequency = <50000000>; cap-erase; mmc-high-capacity-erase-size; no-sdio; no-sd; /*-- speed mode --*/ /*sm0: DS26_SDR12*/ /*sm1: HSSDR52_SDR25*/ /*sm2: HSDDR52_DDR50*/ /*sm3: HS200_SDR104*/ /*sm4: HS400*/ /*-- frequency point --*/ /*f0: CLK_400K*/ /*f1: CLK_25M*/ /*f2: CLK_50M*/ /*f3: CLK_100M*/ /*f4: CLK_150M*/ /*f5: CLK_200M*/ sdc_tm4_sm0_freq0 = <0>; sdc_tm4_sm0_freq1 = <0>; sdc_tm4_sm1_freq0 = <0x00000000>; sdc_tm4_sm1_freq1 = <0>; sdc_tm4_sm2_freq0 = <0x00000000>; sdc_tm4_sm2_freq1 = <0>; sdc_tm4_sm3_freq0 = <0x05000000>; sdc_tm4_sm3_freq1 = <0x00000005>; sdc_tm4_sm4_freq0 = <0x00050000>; sdc_tm4_sm4_freq1 = <0x00000004>; sdc_tm4_sm4_freq0_cmd = <0>; sdc_tm4_sm4_freq1_cmd = <0>; /*vmmc-supply = <®_3p3v>;*/ /*vqmc-supply = <®_3p3v>;*/ /*vdmc-supply = <®_3p3v>;*/ /*vmmc = "vcc-card";*/ /*vqmc = "";*/ /*vdmc = "";*/ /*sunxi-power-save-mode;*/ }; sdc0: sdmmc@4020000 { compatible = "allwinner,sunxi-mmc-v5p3x"; device_type = "sdc0"; reg = <0x0 0x04020000 0x0 0x1000>; interrupts-extended = <&plic0 56 IRQ_TYPE_LEVEL_HIGH>; clocks = <&dcxo24M>, <&ccu CLK_PLL_PERIPH0_2X>, <&ccu CLK_MMC0>, <&ccu CLK_BUS_MMC0>; clock-names = "osc24m","pll_periph","mmc","ahb"; resets = <&ccu RST_BUS_MMC0>; reset-names = "rst"; pinctrl-names = "default","mmc_1v8","sleep","uart_jtag"; pinctrl-0 = <&sdc0_pins_a>; pinctrl-1 = <&sdc0_pins_b>; pinctrl-2 = <&sdc0_pins_c>; pinctrl-3 = <&sdc0_pins_d &sdc0_pins_e>; max-frequency = <50000000>; bus-width = <4>; req-page-count = <2>; /*non-removable;*/ /*broken-cd;*/ /*cd-inverted*/ /*cd-gpios = <&pio PF 6 GPIO_ACTIVE_LOW>;*/ /* vmmc-supply = <®_3p3v>;*/ /* vqmc-supply = <®_3p3v>;*/ /* vdmc-supply = <®_3p3v>;*/ /*vmmc = "vcc-card";*/ /*vqmc = "";*/ /*vdmc = "";*/ cap-sd-highspeed; cap-wait-while-busy; no-sdio; no-mmc; /*sd-uhs-sdr50;*/ /*sd-uhs-ddr50;*/ /*cap-sdio-irq;*/ /*keep-power-in-suspend;*/ /*ignore-pm-notify;*/ /*sunxi-power-save-mode;*/ /*sunxi-dly-400k = <1 0 0 0>; */ /*sunxi-dly-26M = <1 0 0 0>;*/ /*sunxi-dly-52M = <1 0 0 0>;*/ /*sunxi-dly-52M-ddr4 = <1 0 0 0>;*/ /*sunxi-dly-52M-ddr8 = <1 0 0 0>;*/ /*sunxi-dly-104M = <1 0 0 0>;*/ /*sunxi-dly-208M = <1 0 0 0>;*/ /*sunxi-dly-104M-ddr = <1 0 0 0>;*/ /*sunxi-dly-208M-ddr = <1 0 0 0>;*/ status = "okay"; }; sdc1: sdmmc@4021000 { compatible = "allwinner,sunxi-mmc-v5p3x"; device_type = "sdc1"; reg = <0x0 0x04021000 0x0 0x1000>; interrupts-extended = <&plic0 57 IRQ_TYPE_LEVEL_HIGH>; clocks = <&dcxo24M>, <&ccu CLK_PLL_PERIPH0_2X>, <&ccu CLK_MMC1>, <&ccu CLK_BUS_MMC1>; clock-names = "osc24m","pll_periph","mmc","ahb"; resets = <&ccu RST_BUS_MMC1>; reset-names = "rst"; pinctrl-names = "default","sleep"; pinctrl-0 = <&sdc1_pins_a>; pinctrl-1 = <&sdc1_pins_b>; max-frequency = <50000000>; bus-width = <4>; /*broken-cd;*/ /*cd-inverted*/ /*cd-gpios = <&pio PG 6 6 1 2 0>;*/ /* vmmc-supply = <®_3p3v>;*/ /* vqmc-supply = <®_3p3v>;*/ /* vdmc-supply = <®_3p3v>;*/ /*vmmc = "vcc-card";*/ /*vqmc = "";*/ /*vdmc = "";*/ cap-sd-highspeed; no-mmc; /*sd-uhs-sdr50;*/ /*sd-uhs-ddr50;*/ /*sd-uhs-sdr104;*/ /*cap-sdio-irq;*/ keep-power-in-suspend; /*ignore-pm-notify;*/ /*sunxi-power-save-mode;*/ /*sunxi-dly-400k = <1 0 0 0 0>; */ /*sunxi-dly-26M = <1 0 0 0 0>;*/ /*sunxi-dly-52M = <1 0 0 0 0>;*/ sunxi-dly-52M-ddr4 = <1 0 0 0 2>; /*sunxi-dly-52M-ddr8 = <1 0 0 0 0>;*/ sunxi-dly-104M = <1 0 0 0 1>; /*sunxi-dly-208M = <1 1 0 0 0>;*/ sunxi-dly-208M = <1 0 0 0 1>; /*sunxi-dly-104M-ddr = <1 0 0 0 0>;*/ /*sunxi-dly-208M-ddr = <1 0 0 0 0>;*/ status = "disabled"; }; hdmi: hdmi@5500000 { compatible = "allwinner,sunxi-hdmi"; reg = <0x0 0x05500000 0x0 0xfffff>; interrupts-extended = <&plic0 93 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_24M>, <&ccu CLK_HDMI_CEC>, <&ccu CLK_TCON_TV>; clock-names = "clk_bus_hdmi", "clk_ddc", "clk_cec", "clk_tcon_tv"; resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDMI_MAIN>; reset-names = "rst_bus_sub", "rst_bus_main"; assigned-clocks = <&ccu CLK_HDMI_CEC>; assigned-clock-parents = <&ccu CLK_HDMI_CEC_32K>; assigned-clock-rates = <0>; status = "okay"; }; usbc0:usbc0@0 { device_type = "usbc0"; compatible = "allwinner,sunxi-otg-manager"; usb_port_type = <2>; usb_detect_type = <1>; usb_id_gpio; usb_det_vbus_gpio; usb_regulator_io = "nocare"; usb_wakeup_suspend = <0>; usb_luns = <3>; usb_serial_unique = <0>; usb_serial_number = "20080411"; rndis_wceis = <1>; status = "okay"; }; udc:udc-controller@0x04100000 { compatible = "allwinner,sunxi-udc"; reg = <0x0 0x04100000 0x0 0x1000>, /*udc base*/ <0x0 0x00000000 0x0 0x100>; /*sram base*/ interrupts-extended = <&plic0 45 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_OTG>; clock-names = "bus_otg"; resets = <&ccu RST_BUS_OTG>, <&ccu RST_USB_PHY0>; reset-names = "otg", "phy"; status = "okay"; }; ehci0:ehci0-controller@0x04101000 { compatible = "allwinner,sunxi-ehci0"; reg = <0x0 0x04101000 0x0 0xFFF>, /*hci0 base*/ <0x0 0x00000000 0x0 0x100>, /*sram base*/ <0x0 0x04100000 0x0 0x1000>; /*otg base*/ interrupts-extended = <&plic0 46 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_EHCI0>; clock-names = "bus_hci"; resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_USB_PHY0>; reset-names = "hci", "phy"; hci_ctrl_no = <0>; status = "okay"; }; ohci0:ohci0-controller@0x04101400 { compatible = "allwinner,sunxi-ohci0"; reg = <0x0 0x04101400 0x0 0xFFF>, /*hci0 base*/ <0x0 0x00000000 0x0 0x100>, /*sram base*/ <0x0 0x04100000 0x0 0x1000>; /*otg base*/ interrupts-extended = <&plic0 47 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_OHCI0>, <&ccu CLK_USB_OHCI0>; clock-names = "bus_hci", "ohci"; resets = <&ccu RST_BUS_OHCI0>, <&ccu RST_USB_PHY0>; reset-names = "hci", "phy"; hci_ctrl_no = <0>; status = "okay"; }; usbc1:usbc1@0 { device_type = "usbc1"; usb_regulator_io = "nocare"; usb_wakeup_suspend = <0>; status = "disable"; }; ehci1:ehci1-controller@0x04200000 { compatible = "allwinner,sunxi-ehci1"; reg = <0x0 0x04200000 0x0 0xFFF>, /*ehci1 base*/ <0x0 0x00000000 0x0 0x100>, /*sram base*/ <0x0 0x04100000 0x0 0x1000>; /*otg base*/ interrupts-extended = <&plic0 49 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_EHCI1>; clock-names = "bus_hci"; resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_USB_PHY1>; reset-names = "hci", "phy"; hci_ctrl_no = <1>; status = "disable"; }; ohci1:ohci1-controller@0x04200400 { compatible = "allwinner,sunxi-ohci1"; reg = <0x0 0x04200400 0x0 0xFFF>, /*ohci1 base*/ <0x0 0x00000000 0x0 0x100>, /*sram base*/ <0x0 0x04100000 0x0 0x1000>; /*otg base*/ interrupts-extended = <&plic0 50 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_OHCI1>, <&ccu CLK_USB_OHCI1>; clock-names = "bus_hci", "ohci"; resets = <&ccu RST_BUS_OHCI1>, <&ccu RST_USB_PHY1>; reset-names = "hci", "phy"; hci_ctrl_no = <1>; status = "disable"; }; pwm0: pwm0@2000c10 { compatible = "allwinner,sunxi-pwm0"; reg = <0x0 0x02000c10 0x0 0x4>; reg_base = <0x02000c00>; }; pwm1: pwm1@2000c11 { compatible = "allwinner,sunxi-pwm1"; reg = <0x0 0x02000c11 0x0 0x4>; reg_base = <0x02000c00>; }; pwm2: pwm2@2000c12 { compatible = "allwinner,sunxi-pwm2"; reg = <0x0 0x02000c12 0x0 0x4>; reg_base = <0x02000c00>; }; pwm3: pwm3@2000c13 { compatible = "allwinner,sunxi-pwm3"; reg = <0x0 0x02000c13 0x0 0x4>; reg_base = <0x02000c00>; }; pwm4: pwm4@2000c14 { compatible = "allwinner,sunxi-pwm4"; reg = <0x0 0x02000c14 0x0 0x4>; reg_base = <0x02000c00>; }; pwm5: pwm5@2000c15 { compatible = "allwinner,sunxi-pwm5"; reg = <0x0 0x02000c15 0x0 0x4>; reg_base = <0x02000c00>; }; pwm6: pwm6@2000c16 { compatible = "allwinner,sunxi-pwm6"; reg = <0x0 0x02000c16 0x0 0x4>; reg_base = <0x02000c00>; }; pwm7: pwm7@2000c17 { compatible = "allwinner,sunxi-pwm7"; reg = <0x0 0x02000c17 0x0 0x4>; reg_base = <0x02000c00>; }; lcd_fb0: lcd_fb0@0 { compatible = "allwinner,sunxi-lcd_fb0"; pinctrl-names = "active","sleep"; status = "disabled"; }; vind0: vind@5800800 { compatible = "allwinner,sunxi-vin-media", "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; device_id = <0>; csi_top = <336000000>; csi_isp = <327000000>; reg = <0x0 0x05800800 0x0 0x200>, <0x0 0x05800000 0x0 0x800>; clocks = <&ccu CLK_CSI_TOP>, <&ccu CLK_PLL_VIDEO1_2X>, <&ccu CLK_CSI0_MCLK>, <&dcxo24M>, <&ccu CLK_PLL_VIDEO1>, <&ccu CLK_BUS_CSI>, <&ccu CLK_MBUS_CSI>; clock-names = "csi_top", "csi_top_src", "csi_mclk0", "csi_mclk0_24m", "csi_mclk0_pll", "csi_bus", "csi_mbus"; resets = <&ccu RST_BUS_CSI>; reset-names = "csi_ret"; pinctrl-names = "mclk0-default", "mclk0-sleep"; pinctrl-0 = <&csi_mclk0_pins_a>; pinctrl-1 = <&csi_mclk0_pins_b>; status = "okay"; csi0: csi@5801000{ compatible = "allwinner,sunxi-csi"; reg = <0x0 0x05801000 0x0 0x1000>; interrupts-extended = <&plic0 116 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default","sleep"; pinctrl-0 = <&csi0_pins_a>; pinctrl-1 = <&csi0_pins_b>; device_id = <0>; iommus = <&mmu_aw 1 1>; status = "okay"; }; isp0: isp@5809410 { compatible = "allwinner,sunxi-isp"; reg = <0x0 0x05809410 0x0 0x10>; device_id = <0xfe>; status = "okay"; }; isp1: isp@5809420 { compatible = "allwinner,sunxi-isp"; reg = <0x0 0x05809420 0x0 0x10>; device_id = <0xff>; status = "okay"; }; scaler0: scaler@5809430 { compatible = "allwinner,sunxi-scaler"; reg = <0x0 0x05809430 0x0 0x10>; device_id = <0xfe>; status = "okay"; }; scaler1: scaler@5809440 { compatible = "allwinner,sunxi-scaler"; reg = <0x0 0x05809440 0x0 0x10>; device_id = <0xff>; status = "okay"; }; actuator0: actuator@5809450 { compatible = "allwinner,sunxi-actuator"; device_type = "actuator0"; reg = <0x0 0x05809450 0x0 0x10>; actuator0_name = "ad5820_act"; actuator0_slave = <0x18>; actuator0_af_pwdn = <>; actuator0_afvdd = "afvcc-csi"; actuator0_afvdd_vol = <2800000>; status = "disabled"; }; flash0: flash@5809460 { device_type = "flash0"; compatible = "allwinner,sunxi-flash"; reg = <0x0 0x05809460 0x0 0x10>; flash0_type = <2>; flash0_en = <>; flash0_mode = <>; flash0_flvdd = ""; flash0_flvdd_vol = <>; device_id = <0>; status = "disabled"; }; sensor0: sensor@5809470 { reg = <0x0 0x05809470 0x0 0x10>; device_type = "sensor0"; compatible = "allwinner,sunxi-sensor"; sensor0_mname = "ov5640"; sensor0_twi_cci_id = <2>; sensor0_twi_addr = <0x78>; sensor0_mclk_id = <0>; sensor0_pos = "rear"; sensor0_isp_used = <0>; sensor0_fmt = <0>; sensor0_stby_mode = <0>; sensor0_vflip = <0>; sensor0_hflip = <0>; sensor0_iovdd-supply = <>; sensor0_iovdd_vol = <>; sensor0_avdd-supply = <>; sensor0_avdd_vol = <>; sensor0_dvdd-supply = <>; sensor0_dvdd_vol = <>; sensor0_power_en = <>; sensor0_reset = <&pio PE 9 GPIO_ACTIVE_LOW>; sensor0_pwdn = <&pio PE 8 GPIO_ACTIVE_LOW>; sensor0_sm_vs = <>; flash_handle = <&flash0>; act_handle = <&actuator0>; device_id = <0>; status = "okay"; }; sensor1: sensor@5809480 { reg = <0x0 0x05809480 0x0 0x10>; device_type = "sensor1"; compatible = "allwinner,sunxi-sensor"; sensor1_mname = "ov5647"; sensor1_twi_cci_id = <3>; sensor1_twi_addr = <0x6c>; sensor1_mclk_id = <1>; sensor1_pos = "front"; sensor1_isp_used = <0>; sensor1_fmt = <0>; sensor1_stby_mode = <0>; sensor1_vflip = <0>; sensor1_hflip = <0>; sensor1_iovdd-supply = <>; sensor1_iovdd_vol = <>; sensor1_avdd-supply = <>; sensor1_avdd_vol = <>; sensor1_dvdd-supply = <>; sensor1_dvdd_vol = <>; sensor1_power_en = <>; sensor1_reset = <&pio PE 7 GPIO_ACTIVE_LOW>; sensor1_pwdn = <&pio PE 6 GPIO_ACTIVE_LOW>; sensor1_sm_vs = <>; flash_handle = <>; act_handle = <>; device_id = <1>; status = "okay"; }; vinc0: vinc@5809000 { compatible = "allwinner,sunxi-vin-core"; device_type = "vinc0"; reg = <0x0 0x05809000 0x0 0x200>; interrupts-extended = <&plic0 111 IRQ_TYPE_LEVEL_HIGH>; vinc0_csi_sel = <0>; vinc0_mipi_sel = <0xff>; vinc0_isp_sel = <0>; vinc0_tdm_rx_sel = <0xff>; vinc0_rear_sensor_sel = <0>; vinc0_front_sensor_sel = <0>; vinc0_sensor_list = <0>; device_id = <0>; iommus = <&mmu_aw 1 1>; status = "okay"; }; vinc1: vinc@5809200 { device_type = "vinc1"; compatible = "allwinner,sunxi-vin-core"; reg = <0x0 0x05809200 0x0 0x200>; interrupts-extended = <&plic0 112 IRQ_TYPE_LEVEL_HIGH>; vinc1_csi_sel = <0>; vinc1_mipi_sel = <0xff>; vinc1_isp_sel = <1>; vinc1_tdm_rx_sel = <0xff>; vinc1_rear_sensor_sel = <0>; vinc1_front_sensor_sel = <0>; vinc1_sensor_list = <0>; device_id = <1>; iommus = <&mmu_aw 1 1>; status = "okay"; }; }; tvd: tvd@05c00000 { compatible = "allwinner,sunxi-tvd"; reg = <0x0 0x05c00000 0x0 0x00010000>;/*tvd_top*/ interrupts-extended = <&plic0 123 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_TVD_TOP>, <&ccu CLK_MBUS_TVIN>; clock-names = "clk_bus_tvd_top", "clk_mbus_tvd"; resets = <&ccu RST_BUS_TVD_TOP>; reset-names = "rst_bus_tvd_top"; tvd-number = <1>; tvds = <&tvd0>; status = "okay"; }; tvd0: tvd0@05c01000 { compatible = "allwinner,sunxi-tvd0"; reg = <0x0 0x05c01000 0x0 0x00010000>; interrupts-extended = <&plic0 123 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_TVD>, <&ccu CLK_BUS_TVD>; clock-names = "clk_tvd0","clk_bus_tvd0"; resets = <&ccu RST_BUS_TVD>; reset-names = "rst_bus_tvd0"; assigned-clocks = <&ccu CLK_TVD>; assigned-clock-parents = <&ccu CLK_PLL_VIDEO1>; tvd_used = <1>; tvd_if = <0>; status = "okay"; }; }; };文件：device/config/chips/d1-h/configs/nezha/linux-5.4/board.dts
/* * Allwinner Technology CO., Ltd. sun20iw1p1 fpga. * * fpga support. */ /dts-v1/; /memreserve/ 0x42000000 0x100000; /* dsp used 1MB */ #include "sun20iw1p1.dtsi" /{ compatible = "allwinner,d1-h", "arm,sun20iw1p1", "allwinner,sun20iw1p1"; aliases { dsp0 = &dsp0; dsp0_gpio_int= &dsp0_gpio_int; gmac0 = &gmac0; }; dsp0: dsp0 { compatible = "allwinner,sun20iw1-dsp"; status = "okay"; }; dsp0_gpio_int: dsp0_gpio_int { compatible = "allwinner,sun20iw1-dsp-gpio-int"; pin-group = "PB", "PC", "PD", "PE"; status = "disabled"; }; reg_vdd_cpu: vdd-cpu { compatible = "sunxi-pwm-regulator"; pwms = <&pwm 0 5000 1>; regulator-name = "vdd_cpu"; regulator-min-microvolt = <810000>; regulator-max-microvolt = <1160000>; regulator-ramp-delay = <25>; regulator-always-on; regulator-boot-on; status = "okay"; }; reg_usb1_vbus: usb1-vbus { compatible = "regulator-fixed"; regulator-name = "usb1-vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; regulator-enable-ramp-delay = <1000>; gpio = <&pio PD 19 GPIO_ACTIVE_HIGH>; enable-active-high; }; }; &CPU0 { cpu-supply = <®_vdd_cpu>; }; &pio { sdc0_pins_a: sdc0@0 { allwinner,pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; allwinner,function = "sdc0"; allwinner,muxsel = <2>; allwinner,drive = <3>; allwinner,pull = <1>; pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; function = "sdc0"; drive-strength = <30>; bias-pull-up; power-source = <3300>; }; sdc0_pins_b: sdc0@1 { pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; function = "sdc0"; drive-strength = <30>; bias-pull-up; power-source = <1800>; }; sdc0_pins_c: sdc0@2 { pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; function = "gpio_in"; }; /* TODO: add jtag pin */ sdc0_pins_d: sdc0@3 { pins = "PF2", "PF4"; function = "uart0"; drive-strength = <10>; bias-pull-up; }; sdc0_pins_e: sdc0@4 { pins = "PF0", "PF1", "PF3", "PF5"; function = "jtag"; drive-strength = <10>; bias-pull-up; }; sdc1_pins_a: sdc1@0 { pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5"; function = "sdc1"; drive-strength = <30>; bias-pull-up; }; sdc1_pins_b: sdc1@1 { pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5"; function = "gpio_in"; }; sdc2_pins_a: sdc2@0 { allwinner,pins = "PC2", "PC3", "PC4", "PC5", "PC6", "PC7"; allwinner,function = "sdc2"; allwinner,muxsel = <3>; allwinner,drive = <3>; allwinner,pull = <1>; pins = "PC2", "PC3", "PC4", "PC5", "PC6", "PC7"; function = "sdc2"; drive-strength = <30>; bias-pull-up; }; sdc2_pins_b: sdc2@1 { pins = "PC2", "PC3", "PC4", "PC5", "PC6", "PC7"; function = "gpio_in"; }; wlan_pins_a:wlan@0 { pins = "PG11"; function = "clk_fanout1"; }; uart0_pins_a: uart0_pins@0 { /* For nezha board */ pins = "PB8", "PB9"; function = "uart0"; drive-strength = <10>; bias-pull-up; }; uart0_pins_b: uart0_pins@1 { /* For nezha board */ pins = "PB8", "PB9"; function = "gpio_in"; }; uart1_pins_a: uart1_pins@0 { /* For EVB1 board */ pins = "PG6", "PG7", "PG8", "PG9"; function = "uart1"; drive-strength = <10>; bias-pull-up; }; uart1_pins_b: uart1_pins { /* For EVB1 board */ pins = "PG6", "PG7", "PG8", "PG9"; function = "gpio_in"; }; uart2_pins_a: uart2_pins@0 { /* For EVB1 board */ pins = "PC0", "PC1"; function = "uart2"; drive-strength = <10>; bias-pull-up; }; uart2_pins_b: uart2_pins@1 { /* For EVB1 board */ pins = "PC0", "PC1"; function = "gpio_in"; }; uart3_pins_a: uart3_pins@0 { /* For EVB1 board */ pins = "PD10", "PD11"; function = "uart3"; muxsel = <5>; drive-strength = <10>; bias-pull-up; }; twi0_pins_a: twi0@0 { pins = "PB10", "PB11"; /*sck sda*/ function = "twi0"; drive-strength = <10>; }; twi0_pins_b: twi0@1 { pins = "PB10", "PB11"; function = "gpio_in"; }; twi1_pins_a: twi1@0 { pins = "PB4", "PB5"; function = "twi1"; drive-strength = <10>; }; twi1_pins_b: twi1@1 { pins = "PB4", "PB5"; function = "gpio_in"; }; twi2_pins_a: twi2@0 { pins = "PB0", "PB1"; function = "twi2"; drive-strength = <10>; }; twi2_pins_b: twi2@1 { pins = "PB0", "PB1"; function = "gpio_in"; }; twi3_pins_a: twi3@0 { pins = "PB6", "PB7"; function = "twi3"; drive-strength = <10>; }; twi3_pins_b: twi3@1 { pins = "PB6", "PB7"; function = "gpio_in"; }; gmac_pins_a: gmac@0 { pins = "PE0", "PE1", "PE2", "PE3", "PE4", "PE5", "PE6", "PE7", "PE8", "PE9", "PE10", "PE11", "PE12", "PE13", "PE14", "PE15"; function = "gmac0"; muxsel = <8>; /* for uboot driver */ drive-strength = <10>; }; gmac_pins_b: gmac@1 { pins = "PE0", "PE1", "PE2", "PE3", "PE4", "PE5", "PE6", "PE7", "PE8", "PE9", "PE10", "PE11", "PE12", "PE13", "PE14", "PE15"; function = "gpio_in"; }; dmic_pins_a: dmic@0 { /* DMIC_PIN: CLK, DATA0, DATA1, DATA2 */ pins = "PE17", "PB11", "PB10", "PE14"; function = "dmic"; drive-strength = <20>; bias-disable; }; dmic_pins_b: dmic@1 { pins = "PE17", "PB11", "PB10", "PE14"; function = "io_disabled"; drive-strength = <20>; bias-disable; }; daudio0_pins_a: daudio0@0 { /* MCLK, BCLK, LRCK */ pins = "PE17", "PE16", "PE15"; function = "i2s0"; drive-strength = <20>; bias-disable; }; daudio0_pins_b: daudio0@1 { /* DIN0 */ pins = "PE14"; function = "i2s0_din"; drive-strength = <20>; bias-disable; }; daudio0_pins_c: daudio0@2 { /* DOUT0 */ pins = "PE13"; function = "i2s0_dout"; drive-strength = <20>; bias-disable; }; daudio0_pins_d: daudio0_sleep@0 { pins = "PE17", "PE16", "PE15", "PE14", "PE13"; function = "io_disabled"; drive-strength = <20>; bias-disable; }; daudio1_pins_a: daudio1@0 { /* MCLK, LRCK, BCLK */ pins = "PG11", "PG12", "PG13"; function = "i2s1"; drive-strength = <20>; bias-disable; }; daudio1_pins_b: daudio1@1 { /* DIN0 */ pins = "PG14"; function = "i2s1_din"; drive-strength = <20>; bias-disable; }; daudio1_pins_c: daudio1@2 { /* DOUT0 */ pins = "PG15"; function = "i2s1_dout"; drive-strength = <20>; bias-disable; }; daudio1_pins_d: daudio1_sleep@0 { pins = "PG11", "PG12", "PG13", "PG14", "PG15"; function = "io_disabled"; drive-strength = <20>; bias-disable; }; daudio2_pins_a: daudio2@0 { /* I2S_PIN: MCLK, BCLK, LRCK */ pins = "PB7", "PB5", "PB6"; function = "i2s2"; drive-strength = <20>; bias-disable; }; daudio2_pins_b: daudio2@1 { /* I2S_PIN: DOUT0 */ pins = "PB4"; function = "i2s2_dout"; drive-strength = <20>; bias-disable; }; daudio2_pins_c: daudio2@2 { /* I2S_PIN: DIN0 */ pins = "PB3"; function = "i2s2_din"; drive-strength = <20>; bias-disable; }; daudio2_pins_d: daudio2_sleep@0 { pins = "PB7", "PB5", "PB6", "PB4", "PB3"; function = "io_disabled"; drive-strength = <20>; bias-disable; }; spdif_pins_a: spdif@0 { /* SPDIF_PIN: SPDIF_OUT */ pins = "PB0"; function = "spdif"; drive-strength = <20>; bias-disable; }; spdif_pins_b: spdif_sleep@0 { pins = "PB0"; function = "io_disabled"; drive-strength = <20>; bias-disable; }; spi0_pins_a: spi0@0 { pins = "PC2", "PC4", "PC5"; /* clk, mosi, miso */ function = "spi0"; muxsel = <2>; drive-strength = <10>; }; spi0_pins_b: spi0@1 { pins = "PC3", "PC7", "PC6"; function = "spi0"; muxsel = <2>; drive-strength = <10>; bias-pull-up; /* cs, hold, wp should be pulled up */ }; spi0_pins_c: spi0@2 { pins = "PC2", "PC3", "PC4", "PC5","PC6", "PC7"; function = "gpio_in"; muxsel = <0>; drive-strength = <10>; }; spi1_pins_a: spi1@0 { pins = "PD11", "PD12", "PD13"; /* clk, mosi, miso */ function = "spi1"; drive-strength = <10>; }; spi1_pins_b: spi1@1 { pins = "PD10", "PD14", "PD15"; function = "spi1"; drive-strength = <10>; bias-pull-up; /* cs, hold, wp should be pulled up */ }; spi1_pins_c: spi1@2 { pins = "PD10", "PD11", "PD12", "PD13","PD14", "PD15"; function = "gpio_in"; drive-strength = <10>; }; ledc_pins_a: ledc@0 { pins = "PC0"; function = "ledc"; drive-strength = <10>; }; ledc_pins_b: ledc@1 { pins = "PC0"; function = "gpio_in"; }; pwm0_pin_a: pwm0@0 { pins = "PD16"; function = "pwm0"; drive-strength = <10>; bias-pull-up; }; pwm0_pin_b: pwm0@1 { pins = "PD16"; function = "gpio_in"; bias-disable; }; pwm2_pin_a: pwm2@0 { pins = "PD18"; function = "pwm2"; drive-strength = <10>; bias-pull-up; }; pwm2_pin_b: pwm2@1 { pins = "PD18"; function = "gpio_out"; }; pwm7_pin_a: pwm7@0 { pins = "PD22"; function = "pwm7"; drive-strength = <10>; bias-pull-up; }; pwm7_pin_b: pwm7@1 { pins = "PD22"; function = "gpio_in"; }; s_cir0_pins_a: s_cir@0 { pins = "PB12"; function = "ir"; drive-strength = <10>; bias-pull-up; }; s_cir0_pins_b: s_cir@1 { pins = "PB12"; function = "gpio_in"; }; ir1_pins_a: ir1@0 { pins = "PB0"; function = "ir"; drive-strength = <10>; bias-pull-up; }; ir1_pins_b: ir1@1 { pins = "PB0"; function = "gpio_in"; }; }; &uart0 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&uart0_pins_a>; pinctrl-1 = <&uart0_pins_b>; status = "okay"; }; &uart1 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&uart1_pins_a>; pinctrl-1 = <&uart1_pins_b>; status = "okay"; }; &uart2 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&uart2_pins_a>; pinctrl-1 = <&uart2_pins_b>; status = "disabled"; }; &uart3 { compatible = "allwinner,sun20iw1-dsp-uart"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&uart3_pins_a>; pinctrl-1 = <&uart3_pins_a>; status = "okay"; }; &soc { card0_boot_para@2 { /* * Avoid dtc compiling warnings. * @TODO: Developer should modify this to the actual value */ reg = <0x0 0x2 0x0 0x0>; device_type = "card0_boot_para"; card_ctrl = <0x0>; card_high_speed = <0x1>; card_line = <0x4>; pinctrl-0 = <&sdc0_pins_a>; }; card2_boot_para@3 { /* * Avoid dtc compiling warnings. * @TODO: Developer should modify this to the actual value */ reg = <0x0 0x3 0x0 0x0>; device_type = "card2_boot_para"; card_ctrl = <0x2>; card_high_speed = <0x1>; card_line = <0x4>; pinctrl-0 = <&sdc2_pins_a>; /*pinctrl-0 = <&sdc0_pins_a>;*/ /*sdc_ex_dly_used = <0x2>;*/ sdc_io_1v8 = <0x1>; /*sdc_type = "tm4";*/ sdc_tm4_hs200_max_freq = <150>; sdc_tm4_hs400_max_freq = <100>; sdc_ex_dly_used = <2>; /*sdc_tm4_win_th = <8>;*/ /*sdc_dis_host_caps = <0x180>;*/ }; rfkill: rfkill@0 { compatible = "allwinner,sunxi-rfkill"; chip_en; power_en; pinctrl-0 = <&wlan_pins_a>; pinctrl-names = "default"; status = "okay"; wlan: wlan@0 { compatible = "allwinner,sunxi-wlan"; clock-names = "32k-fanout1"; clocks = <&ccu CLK_FANOUT1_OUT>; wlan_busnum = <0x1>; wlan_regon = <&pio PG 12 GPIO_ACTIVE_HIGH>; wlan_hostwake = <&pio PG 10 GPIO_ACTIVE_HIGH>; /*wlan_power = "VCC-3V3";*/ /*wlan_power_vol = <3300000>;*/ /*interrupt-parent = <&pio>; interrupts = < PG 10 IRQ_TYPE_LEVEL_HIGH>;*/ wakeup-source; }; bt: bt@0 { compatible = "allwinner,sunxi-bt"; clock-names = "32k-fanout1"; clocks = <&ccu CLK_FANOUT1_OUT>; /*bt_power_num = <0x01>;*/ /*bt_power = "axp803-dldo1";*/ /*bt_io_regulator = "axp803-dldo1";*/ /*bt_io_vol = <3300000>;*/ /*bt_power_vol = <330000>;*/ bt_rst_n = <&pio PG 18 GPIO_ACTIVE_LOW>; status = "okay"; }; }; btlpm: btlpm@0 { compatible = "allwinner,sunxi-btlpm"; uart_index = <0x1>; bt_wake = <&pio PG 16 GPIO_ACTIVE_HIGH>; bt_hostwake = <&pio PG 17 GPIO_ACTIVE_HIGH>; status = "okay"; }; addr_mgt: addr_mgt@0 { compatible = "allwinner,sunxi-addr_mgt"; type_addr_wifi = <0x0>; type_addr_bt = <0x0>; type_addr_eth = <0x0>; status = "okay"; }; }; &sdc2 { non-removable; bus-width = <4>; mmc-ddr-1_8v; mmc-hs200-1_8v; no-sdio; no-sd; ctl-spec-caps = <0x308>; cap-mmc-highspeed; sunxi-power-save-mode; sunxi-dis-signal-vol-sw; mmc-bootpart-noacc; max-frequency = <150000000>; /*vmmc-supply = <®_dcdc1>;*/ /*emmc io vol 3.3v*/ /*vqmmc-supply = <®_aldo1>;*/ /*emmc io vol 1.8v*/ /*vqmmc-supply = <®_eldo1>;*/ status = "disabled"; }; &sdc0 { bus-width = <4>; cd-gpios = <&pio PF 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /*non-removable;*/ /*broken-cd;*/ cd-inverted; /*data3-detect;*/ /*card-pwr-gpios = <&pio PH 14 1 1 2 0xffffffff>;*/ cd-used-24M; cap-sd-highspeed; /*sd-uhs-sdr50;*/ /*sd-uhs-ddr50;*/ /*sd-uhs-sdr104;*/ no-sdio; no-mmc; sunxi-power-save-mode; /*sunxi-dis-signal-vol-sw;*/ max-frequency = <150000000>; ctl-spec-caps = <0x8>; /*vmmc-supply = <®_dcdc1>;*/ /*vqmmc33sw-supply = <®_dcdc1>;*/ /*vdmmc33sw-supply = <®_dcdc1>;*/ /*vqmmc18sw-supply = <®_eldo1>;*/ /*vdmmc18sw-supply = <®_eldo1>;*/ status = "okay"; }; &sdc1 { bus-width = <4>; no-mmc; no-sd; cap-sd-highspeed; /*sd-uhs-sdr12*/ /*sd-uhs-sdr25;*/ /*sd-uhs-sdr50;*/ /*sd-uhs-ddr50;*/ /*sd-uhs-sdr104;*/ /*sunxi-power-save-mode;*/ /*sunxi-dis-signal-vol-sw;*/ cap-sdio-irq; keep-power-in-suspend; ignore-pm-notify; max-frequency = <150000000>; ctl-spec-caps = <0x8>; status = "okay"; }; /* tvd configuration used (create device, 0: do not create device, 1: create device) agc_auto_enable (0: agc manual mode,agc_manual_value is valid; 1: agc auto mode) agc_manual_value (agc manual value, default value is 64) cagc_enable (cagc 0: disable, 1: enable) fliter_used (3d fliter 0: disable, 1: enable) support two PMU power (tvd_power0, tvd_power1) support two GPIO power (tvd_gpio0, tvd_gpio1) NOTICE: If tvd need pmu power or gpio power,params need be configured under [tvd] tvd_sw (the switch of all tvd driver.) tvd_interface (0: cvbs, 1: ypbpr,) tvd_format (0:TVD_PL_YUV420 , 1: MB_YUV420, 2: TVD_PL_YUV422) tvd_system (0:ntsc, 1:pal) tvd_row (total row number in multi channel mode 1-2) tvd_column (total column number in multi channel mode 1-2) tvd_channelx_en (0:disable, 1~4:position in multi channel mode,In single channel mode,mean enable) tvd_row*tvd_column is the total tvd channel number to be used in multichannel mode +--------------------+--------------------+ | | | | | | | 1 | 2 | | | | | | | +--------------------+--------------------+ | | | | | | | 3 | 4 | | | | | | | +--------------------+--------------------+ */ &tvd { tvd_sw = <1>; tvd_interface = <0>; tvd_format = <0>; tvd_system = <1>; tvd_row = <1>; tvd_column = <1>; tvd_channel0_en = <1>; tvd_channel1_en = <0>; tvd_channel2_en = <0>; tvd_channel3_en = <0>; /*tvd_gpio0 = <&pio PD 22 GPIO_ACTIVE_HIGH>;*/ /*tvd_gpio1 = <&pio PD 23 GPIO_ACTIVE_HIGH>;*/ /*tvd_gpio2 = <&pio PD 24 GPIO_ACTIVE_HIGH>;*/ /* dc1sw-supply = <®_dc1sw>;*/ /* eldo3-supply = <®_eldo3>;*/ /*tvd_power0 = "dc1sw"*/ /*tvd_power1 = "eldo3"*/ }; &tvd0 { used = <1>; agc_auto_enable = <1>; agc_manual_value = <64>; cagc_enable = <1>; fliter_used = <1>; }; /* Audio Driver modules */ &sunxi_rpaf_dsp0 { status = "okay"; }; /* if audiocodec is used, sdc0 and uart0 should be closed to enable PA. */ &codec { /* MIC and headphone gain setting */ mic1gain = <0x13>; mic2gain = <0x13>; mic3gain = <0x13>; /* ADC/DAC DRC/HPF func enabled */ /* 0x1:DAP_HP_EN; 0x2:DAP_SPK_EN; 0x3:DAP_HPSPK_EN */ adcdrc_cfg = <0x0>; adchpf_cfg = <0x1>; dacdrc_cfg = <0x0>; dachpf_cfg = <0x0>; /* Volume about */ digital_vol = <0x00>; lineout_vol = <0x1a>; headphonegain = <0x03>; /* Pa enabled about */ pa_level = <0x01>; pa_pwr_level = <0x01>; pa_msleep_time = <0x78>; /* gpio-spk = <&pio PF 2 GPIO_ACTIVE_HIGH>; */ /* gpio-spk-pwr = <&pio PF 4 GPIO_ACTIVE_HIGH>; */ /* regulator about */ /* avcc-supply = <®_aldo1>; */ /* hpvcc-supply = <®_eldo1>; */ status = "okay"; }; &sndcodec { hp_detect_case = <0x01>; jack_enable = <0x01>; status = "okay"; }; &dummy_cpudai { /* CMA config about */ playback_cma = <128>; capture_cma = <256>; status = "okay"; }; &dmic { pinctrl-names = "default","sleep"; pinctrl-0 = <&dmic_pins_a>; pinctrl-1 = <&dmic_pins_b>; status = "okay"; }; &sounddmic { status = "okay"; }; &dmic_codec { status = "okay"; }; /*----------------------------------------------------------------------------- * pcm_lrck_period 16/32/64/128/256 * (set 0x20 for HDMI audio out) * slot_width_select 16bits/20bits/24bits/32bits * (set 0x20 for HDMI audio out) * frametype 0 --> short frame = 1 clock width; * 1 --> long frame = 2 clock width; * tdm_config 0 --> pcm * 1 --> i2s * (set 0x01 for HDMI audio out) * mclk_div 0 --> not output * 1/2/4/6/8/12/16/24/32/48/64/96/128/176/192 * (set mclk as external codec clk source, freq is pll_audio/mclk_div) * pinctrl_used 0 --> I2S/PCM use for internal (e.g. HDMI) * 1 --> I2S/PCM use for external audio * daudio_type: 0 --> external audio type * 1 --> HDMI audio type *---------------------------------------------------------------------------*/ &daudio0 { mclk_div = <0x01>; frametype = <0x00>; tdm_config = <0x01>; sign_extend = <0x00>; msb_lsb_first = <0x00>; pcm_lrck_period = <0x80>; slot_width_select = <0x20>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&daudio0_pins_a &daudio0_pins_b &daudio0_pins_c>; pinctrl-1 = <&daudio0_pins_d>; pinctrl_used = <0x0>; status = "disabled"; }; /*----------------------------------------------------------------------------- * simple-audio-card,name name of sound card, e.g. * "snddaudio0" --> use for external audio * "sndhdmi" --> use for HDMI audio * sound-dai "snd-soc-dummy" --> use for I2S * "hdmiaudio" --> use for HDMI audio * "ac108" --> use for external audio of ac108 *---------------------------------------------------------------------------*/ &sounddaudio0 { /* simple-audio-card,format = "i2s"; */ /* simple-audio-card,frame-master = <&daudio0_master>; */ /* simple-audio-card,bitclock-master = <&daudio0_master>; */ /* simple-audio-card,bitclock-inversion; */ /* simple-audio-card,frame-inversion; */ status = "disabled"; daudio0_master: simple-audio-card,codec { /* sound-dai = <&ac108>; */ }; }; &daudio1 { mclk_div = <0x01>; frametype = <0x00>; tdm_config = <0x01>; sign_extend = <0x00>; msb_lsb_first = <0x00>; pcm_lrck_period = <0x80>; slot_width_select = <0x20>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&daudio1_pins_a &daudio1_pins_b &daudio1_pins_c>; pinctrl-1 = <&daudio1_pins_d>; pinctrl_used = <0x0>; status = "disabled"; }; &sounddaudio1 { status = "disabled"; daudio1_master: simple-audio-card,codec { /* sound-dai = <&ac108>; */ }; }; &daudio2 { mclk_div = <0x00>; frametype = <0x00>; tdm_config = <0x01>; sign_extend = <0x00>; tx_data_mode = <0x00>; rx_data_mode = <0x00>; msb_lsb_first = <0x00>; pcm_lrck_period = <0x20>; slot_width_select = <0x20>; asrc_function_en = <0x00>; pinctrl-names = "default", "sleep"; /*pinctrl-0 = <&daudio2_pins_a &daudio2_pins_b &daudio2_pins_c>;*/ /*pinctrl-1 = <&daudio2_pins_d>;*/ /* HDMI audio, no need pin */ pinctrl-0; pinctrl-1; pinctrl_used = <0x0>; daudio_type = <0x1>; status = "okay"; }; /* if HDMI audio is used, daudio2 should be enable. */ &hdmiaudio { status = "okay"; }; &sounddaudio2 { status = "okay"; simple-audio-card,name = "sndhdmi"; daudio2_master: simple-audio-card,codec { sound-dai = <&hdmiaudio>; }; }; &spdif { pinctrl-names = "default","sleep"; pinctrl-0 = <&spdif_pins_a>; pinctrl-1 = <&spdif_pins_b>; status = "disabled"; }; &soundspdif { status = "disabled"; }; /* *usb_port_type: usb mode. 0-device, 1-host, 2-otg. *usb_detect_type: usb hotplug detect mode. 0-none, 1-vbus/id detect, 2-id/dpdm detect. *usb_detect_mode: 0-thread scan, 1-id gpio interrupt. *usb_id_gpio: gpio for id detect. *usb_det_vbus_gpio: gpio for id detect. gpio or "axp_ctrl"; *usb_wakeup_suspend：0-SUPER_STANDBY, 1-USB_STANDBY. */ &usbc0 { device_type = "usbc0"; usb_port_type = <0x2>; usb_detect_type = <0x1>; usb_detect_mode = <0>; usb_id_gpio = <&pio PD 21 GPIO_ACTIVE_HIGH>; enable-active-high; usb_det_vbus_gpio = <&pio PD 20 GPIO_ACTIVE_HIGH>; usb_wakeup_suspend = <0>; usb_serial_unique = <0>; usb_serial_number = "20080411"; rndis_wceis = <1>; status = "okay"; }; &ehci0 { drvvbus-supply = <®_usb1_vbus>; }; &ohci0 { drvvbus-supply = <®_usb1_vbus>; }; &usbc1 { device_type = "usbc1"; usb_regulator_io = "nocare"; usb_wakeup_suspend = <0>; status = "okay"; }; &ehci1 { status = "okay"; }; &ohci1 { status = "okay"; }; &twi0 { clock-frequency = <400000>; pinctrl-0 = <&twi0_pins_a>; pinctrl-1 = <&twi0_pins_b>; pinctrl-names = "default", "sleep"; status = "disabled"; eeprom@50 { compatible = "atmel,24c16"; reg = <0x50>; status = "disabled"; }; }; &twi1 { clock-frequency = <400000>; pinctrl-0 = <&twi1_pins_a>; pinctrl-1 = <&twi1_pins_b>; pinctrl-names = "default", "sleep"; status = "disabled"; }; &twi2 { clock-frequency = <400000>; pinctrl-0 = <&twi2_pins_a>; pinctrl-1 = <&twi2_pins_b>; pinctrl-names = "default", "sleep"; dmas = <&dma 45>, <&dma 45>; dma-names = "tx", "rx"; status = "okay"; /* pcf8574-usage: * only use gpio0~7, 0 means PP0. * pin set: * gpios = <&pcf8574 0 GPIO_ACTIVE_LOW>; * interrupt set: * interrupt-parent = <&pcf8574>; * interrupts = <0 IRQ_TYPE_EDGE_FALLING>; */ pcf8574: gpio@38 { compatible = "nxp,pcf8574"; reg = <0x38>; gpio_base = <2020>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; interrupt-parent = <&pio>; interrupts = <PB 2 IRQ_TYPE_EDGE_FALLING>; status = "okay"; }; ctp@14 { compatible = "allwinner,goodix"; device_type = "ctp"; reg = <0x14>; status = "disabled"; ctp_name = "gt9xxnew_ts"; ctp_twi_id = <0x2>; ctp_twi_addr = <0x14>; ctp_screen_max_x = <0x320>; ctp_screen_max_y = <0x500>; ctp_revert_x_flag = <0x0>; ctp_revert_y_flag = <0x1>; ctp_exchange_x_y_flag = <0x0>; ctp_int_port = <&pio PG 14 GPIO_ACTIVE_HIGH>; ctp_wakeup = <&pio PG 15 GPIO_ACTIVE_HIGH>; }; }; &twi3 { clock-frequency = <400000>; pinctrl-0 = <&twi3_pins_a>; pinctrl-1 = <&twi3_pins_b>; pinctrl-names = "default", "sleep"; status = "disabled"; }; &gmac0 { phy-mode = "rgmii"; use_ephy25m = <1>; pinctrl-0 = <&gmac_pins_a>; pinctrl-1 = <&gmac_pins_b>; pinctrl-names = "default", "sleep"; phy-rst = <&pio PE 16 GPIO_ACTIVE_HIGH>; tx-delay = <3>; /*2~4*/ rx-delay = <0>; status = "disable"; }; &spi0 { clock-frequency = <100000000>; pinctrl-0 = <&spi0_pins_a &spi0_pins_b>; pinctrl-1 = <&spi0_pins_c>; pinctrl-names = "default", "sleep"; /*spi-supply = <®_dcdc1>;*/ spi_slave_mode = <0>; spi0_cs_number = <1>; spi0_cs_bitmap = <1>; status = "disabled"; spi-nand@0 { compatible = "spi-nand"; spi-max-frequency=<0x5F5E100>; reg = <0x0>; spi-rx-bus-width=<0x04>; spi-tx-bus-width=<0x04>; status="disabled"; }; }; &spi1 { clock-frequency = <100000000>; pinctrl-0 = <&spi1_pins_a &spi1_pins_b>; pinctrl-1 = <&spi1_pins_c>; pinctrl-names = "default", "sleep"; spi_slave_mode = <0>; spi1_cs_number = <1>; spi1_cs_bitmap = <1>; spi_dbi_enable = <1>; status = "disabled"; spi_board1@0 { device_type = "spi-dbi"; compatible = "sunxi,spidbi"; spi-max-frequency = <0x5f5e100>; reg = <0x0>; spi-rx-bus-width = <0x4>; spi-tx-bus-width = <0x4>; status = "okay"; }; /* spi_board1@0 { device_type = "spi_board1"; compatible = "rohm,dh2228fv"; spi-max-frequency = <0x5f5e100>; reg = <0x0>; spi-rx-bus-width = <0x4>; spi-tx-bus-width = <0x4>; status = "disabled"; }; */ }; &ledc { pinctrl-names = "default", "sleep"; pinctrl-0 = <&ledc_pins_a>; pinctrl-1 = <&ledc_pins_b>; led_count = <12>; output_mode = "GRB"; reset_ns = <84>; t1h_ns = <800>; t1l_ns = <320>; t0h_ns = <300>; t0l_ns = <800>; wait_time0_ns = <84>; wait_time1_ns = <84>; wait_data_time_ns = <600000>; status = "okay"; }; &keyboard0 { key0 = <210 0x160>; wakeup-source; status = "okay"; }; /*---------------------------------------------------------------------------------- disp init configuration disp_mode (0:screen0<screen0,fb0>) screenx_output_type (0:none; 1:lcd; 2:tv; 3:hdmi;5:vdpo) screenx_output_mode (used for hdmi output, 0:480i 1:576i 2:480p 3:576p 4:720p50) (5:720p60 6:1080i50 7:1080i60 8:1080p24 9:1080p50 10:1080p60) screenx_output_format (for hdmi, 0:RGB 1:yuv444 2:yuv422 3:yuv420) screenx_output_bits (for hdmi, 0:8bit 1:10bit 2:12bit 2:16bit) screenx_output_eotf (for hdmi, 0:reserve 4:SDR 16:HDR10 18:HLG) screenx_output_cs (for hdmi, 0:undefined 257:BT709 260:BT601 263:BT2020) screenx_output_dvi_hdmi (for hdmi, 0:undefined 1:dvi mode 2:hdmi mode) screen0_output_range (for hdmi, 0:default 1:full 2:limited) screen0_output_scan (for hdmi, 0:no data 1:overscan 2:underscan) screen0_output_aspect_ratio (for hdmi, 8-same as original picture 9-4:3 10-16:9 11-14:9) fbx format (4:RGB655 5:RGB565 6:RGB556 7:ARGB1555 8:RGBA5551 9:RGB888 10:ARGB8888 12:ARGB4444) fbx pixel sequence (0:ARGB 1:BGRA 2:ABGR 3:RGBA) fb0_scaler_mode_enable(scaler mode enable, used FE) fbx_width,fbx_height (framebuffer horizontal/vertical pixels, fix to output resolution while equal 0) lcdx_backlight (lcd init backlight,the range:[0,256],default:197 lcdx_yy (lcd init screen bright/contrast/saturation/hue, value:0~100, default:50/50/57/50) lcd0_contrast (LCD contrast, 0~100) lcd0_saturation (LCD saturation, 0~100) lcd0_hue (LCD hue, 0~100) framebuffer software rotation setting: disp_rotation_used: (0:disable; 1:enable,you must set fbX_width to lcd_y, set fbX_height to lcd_x) degreeX: (X:screen index; 0:0 degree; 1:90 degree; 3:270 degree) degreeX_Y: (X:screen index; Y:layer index 0~15; 0:0 degree; 1:90 degree; 3:270 degree) devX_output_type : config output type in bootGUI framework in UBOOT-2018. (0:none; 1:lcd; 2:tv; 4:hdmi;) devX_output_mode : config output resolution(see include/video/sunxi_display2.h) of bootGUI framework in UBOOT-2018 devX_screen_id : config display index of bootGUI framework in UBOOT-2018 devX_do_hpd : whether do hpd detectation or not in UBOOT-2018 chn_cfg_mode : Hardware DE channel allocation config. 0:single display with 6 channel, 1:dual display with 4 channel in main display and 2 channel in second display, 2:dual display with 3 channel in main display and 3 channel in second in display. ----------------------------------------------------------------------------------*/ &disp { disp_init_enable = <1>; disp_mode = <0>; screen0_output_type = <1>; screen0_output_mode = <4>; screen1_output_type = <3>; screen1_output_mode = <10>; screen1_output_format = <0>; screen1_output_bits = <0>; screen1_output_eotf = <4>; screen1_output_cs = <257>; screen1_output_dvi_hdmi = <2>; screen1_output_range = <2>; screen1_output_scan = <0>; screen1_output_aspect_ratio = <8>; dev0_output_type = <1>; dev0_output_mode = <4>; dev0_screen_id = <0>; dev0_do_hpd = <0>; dev1_output_type = <4>; dev1_output_mode = <10>; dev1_screen_id = <1>; dev1_do_hpd = <1>; def_output_dev = <0>; hdmi_mode_check = <1>; fb0_format = <0>; fb0_width = <0>; fb0_height = <0>; fb1_format = <0>; fb1_width = <0>; fb1_height = <0>; chn_cfg_mode = <1>; disp_para_zone = <1>; /*VCC-LCD*/ /* dc1sw-supply = <®_dc1sw>;*/ /*VCC-DSI*/ /* eldo3-supply = <®_eldo3>;*/ /*VCC-PD*/ /* dcdc1-supply = <®_dcdc1>;*/ }; /*---------------------------------------------------------------------------------- ;lcd0 configuration ;lcd_if: 0:hv(sync+de); 1:8080; 2:ttl; 3:lvds; 4:dsi; 5:edp; 6:extend dsi ;lcd_hv_if 0:Parallel RGB; 8:Serial RGB; 10:Dummy RGB; 11: RGB Dummy;12:CCIR656 ;lcd_hv_clk_phase 0:0 degree;1:90 degree;2:180 degree;3:270 degree ;lcd_hv_sync_polarity 0:vs low,hs low; 1:vs high,hslow; 2:vs low,hs high; 3:vs high,hs high ;lcd_hv_syuv_seq 0:YUYV; 1:YVYU; 2:UYVY; 3:VYUY ;lcd_cpu_if 0:18bit/1 cycle parallel(RGB666); 4:16bit/1cycle parallel (RGB565) ; 6:18bit/3 cycle parallel(RGB666); 7:16bit/2cycle parallel (RGB565) ;lcd_cpu_te 0:frame auto trigger; 1:frame triggered by te rising edge; 2:frame triggered by te falling edge; ;lcd_dsi_if 0:video mode; 1: Command mode; 2:video burst mode ;lcd_dsi_te 0:frame auto trigger; 1:frame triggered by te rising edge; 2:frame triggered by te falling edge; ;lcd_x: lcd horizontal resolution ;lcd_y: lcd vertical resolution ;lcd_width: width of lcd in mm ;lcd_height: height of lcd in mm ;lcd_dclk_freq: in MHZ unit ;lcd_pwm_freq: in HZ unit ;lcd_pwm_pol: lcd backlight PWM polarity ;lcd_pwm_max_limit lcd backlight PWM max limit(<=255) ;lcd_hbp: hsync back porch(pixel) + hsync plus width(pixel); ;lcd_ht: hsync total cycle(pixel) ;lcd_vbp: vsync back porch(line) + vysnc plus width(line) ;lcd_vt: vysnc total cycle(line) ;lcd_hspw: hsync plus width(pixel) ;lcd_vspw: vysnc plus width(pixel) ;lcd_lvds_if: 0:single link; 1:dual link ;lcd_lvds_colordepth: 0:8bit; 1:6bit ;lcd_lvds_mode: 0:NS mode; 1:JEIDA mode ;lcd_frm: 0:disable; 1:enable rgb666 dither; 2:enable rgb656 dither ;lcd_io_phase: 0:noraml; 1:intert phase(0~3bit: vsync phase; 4~7bit:hsync phase; ; 8~11bit:dclk phase; 12~15bit:de phase) ;lcd_gamma_en lcd gamma correction enable ;lcd_bright_curve_en lcd bright curve correction enable ;lcd_cmap_en lcd color map function enable ;deu_mode 0:smoll lcd screen; 1:large lcd screen(larger than 10inch) ;lcdgamma4iep: Smart Backlight parameter, lcd gamma vale * 10; ; decrease it while lcd is not bright enough; increase while lcd is too bright ;smart_color 90:normal lcd screen 65:retina lcd screen(9.7inch) ;Pin setting for special function ie.LVDS, RGB data or vsync ; name(donot care) = port:PD12<pin function><pull up or pull down><drive ability><output level> ;Pin setting for gpio: ; lcd_gpio_X = port:PD12<pin function><pull up or pull down><drive ability><output level> ;Pin setting for backlight enable pin ; lcd_bl_en = port:PD12<pin function><pull up or pull down><drive ability><output level> ;fsync setting, pulse to csi ;lcd_fsync_en (0:disable fsync,1:enable) ;lcd_fsync_act_time (active time of fsync, unit:pixel) ;lcd_fsync_dis_time (disactive time of fsync, unit:pixel) ;lcd_fsync_pol (0:positive;1:negative) ;gpio config: <&pio for cpu or &r_pio for cpus, port, port num, pio function, pull up or pull down(default 0), driver level(default 1), data> ;For dual link lvds: use lvds2link_pins_a and lvds2link_pins_b instead ;For rgb24: use rgb24_pins_a and rgb24_pins_b instead ;For lvds1: use lvds1_pins_a and lvds1_pins_b instead ;For lvds0: use lvds0_pins_a and lvds0_pins_b instead ;----------------------------------------------------------------------------------*/ &lcd0 { lcd_used = <1>; lcd_driver_name = "st7701s_rgb"; lcd_if = <0>; lcd_hv_if = <0>; lcd_width = <53>; lcd_height = <53>; lcd_x = <480>; lcd_y = <480>; lcd_dclk_freq = <19>; lcd_hbp = <60>; lcd_ht = <612>; lcd_hspw = <12>; lcd_vbp = <18>; lcd_vt = <520>; lcd_vspw = <4>; lcd_backlight = <100>; lcd_pwm_used = <1>; lcd_pwm_ch = <7>; lcd_pwm_freq = <1000>; lcd_pwm_pol = <1>; lcd_bright_curve_en = <0>; lcd_frm = <1>; lcd_io_phase = <0x0000>; lcd_gamma_en = <0>; lcd_cmap_en = <0>; lcd_hv_clk_phase= <0>; lcd_hv_sync_polarity= <0>; lcd_rb_swap = <0>; lcd_power = "vcc-lcd"; lcd_pin_power = "vcc-pd"; lcd_gpio_0 = <&pio PG 13 GPIO_ACTIVE_HIGH>; lcd_gpio_1 = <&pio PE 15 GPIO_ACTIVE_HIGH>; lcd_gpio_2 = <&pio PE 12 GPIO_ACTIVE_HIGH>; lcd_gpio_3 = <&pio PE 16 GPIO_ACTIVE_HIGH>; pinctrl-0 = <&rgb18_pins_a>; pinctrl-1 = <&rgb18_pins_b>; }; &hdmi { hdmi_used = <1>; hdmi_power_cnt = <0>; hdmi_cts_compatibility = <1>; hdmi_hdcp_enable = <1>; hdmi_hdcp22_enable = <0>; hdmi_cec_support = <1>; hdmi_cec_super_standby = <0>; ddc_en_io_ctrl = <0>; power_io_ctrl = <0>; }; &pwm0 { pinctrl-names = "active", "sleep"; pinctrl-0 = <&pwm0_pin_a>; pinctrl-1 = <&pwm0_pin_b>; status = "okay"; }; &pwm2 { pinctrl-names = "active", "sleep"; pinctrl-0 = <&pwm2_pin_a>; pinctrl-1 = <&pwm2_pin_b>; status = "okay"; }; &pwm7 { pinctrl-names = "active", "sleep"; pinctrl-0 = <&pwm7_pin_a>; pinctrl-1 = <&pwm7_pin_b>; status = "okay"; }; &rtp { allwinner,tp-sensitive-adjust = <0xf>; allwinner,filter-type = <0x1>; allwinner,ts-attached; status = "disabled"; }; &gpadc { channel_num = <2>; channel_select = <3>; channel_data_select = <3>; channel_compare_select = <3>; channel_cld_select = <3>; channel_chd_select = <3>; channel0_compare_lowdata = <1700000>; channel0_compare_higdata = <1200000>; channel1_compare_lowdata = <460000>; channel1_compare_higdata = <1200000>; status = "disabled"; }; &s_cir0 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&s_cir0_pins_a>; pinctrl-1 = <&s_cir0_pins_b>; status = "disabled"; }; &ir1 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&ir1_pins_a>; pinctrl-1 = <&ir1_pins_b>; status = "disabled"; }; /* &lcd_fb0 { lcd_used = <1>; lcd_driver_name = "kld35512"; lcd_if = <1>; lcd_dbi_if = <4>; lcd_data_speed = <60>; lcd_spi_bus_num = <1>; lcd_x = <320>; lcd_y = <480>; lcd_pixel_fmt = <10>; lcd_dbi_fmt = <2>; lcd_rgb_order = <0>; lcd_width = <60>; lcd_height = <95>; lcd_pwm_used = <1>; lcd_pwm_ch = <7>; lcd_pwm_freq = <5000>; lcd_pwm_pol = <1>; lcd_frm = <1>; lcd_gamma_en = <1>; fb_buffer_num = <2>; lcd_backlight = <100>; lcd_fps = <40>; lcd_dbi_te = <1>; lcd_dbi_clk_mode = <1>; lcd_gpio_0 = <&pio PC 0 GPIO_ACTIVE_HIGH>; status = "okay"; }; */ /* &lcd_fb0 { lcd_used = <1>; lcd_driver_name = "kld2844b"; lcd_if = <1>; lcd_dbi_if = <4>; lcd_data_speed = <60>; lcd_spi_bus_num = <1>; lcd_x = <240>; lcd_y = <320>; lcd_width = <60>; lcd_height = <95>; lcd_pwm_used = <1>; lcd_pwm_ch = <7>; lcd_pwm_freq = <5000>; lcd_pwm_pol = <0>; lcd_pixel_fmt = <0>; lcd_dbi_fmt = <3>; lcd_rgb_order = <0>; lcd_frm = <1>; lcd_gamma_en = <1>; fb_buffer_num = <2>; lcd_backlight = <100>; lcd_dbi_te = <1>; lcd_fps = <60>; lcd_gpio_0 = <&pio PC 0 GPIO_ACTIVE_HIGH>; status = "okay"; }; */求大佬指点这个可能是被哪个设备占用了，或者有什么方法能找到被占用的地方
-
你要不要再找找？我帮你找到了一个
-
@yuzukitsuru 非常感谢，没仔细看，按 PD19 搜了没搜到，没想到是分开写的
Copyright © 2022 深圳全志在线有限公司 粤ICP备2021084185号 粤公网安备44030502007680号