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    T113-S3 spinand的四线模式用不起来

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    • E
      eddylin LV 3 last edited by

      自己做的板,sd卡没问题,千兆网口都已经调通了,就是spinand有问题。使用四线模式的话,uboot连下载都成问题。uboot用单线,linux用四线,随机性死机(完全死掉,动都不动的那种)。spinand布在底部。看完了论坛的帖子,好像有大佬说可能会影响24MHz晶振?实在搞不懂了,第一次自己弄MPU的板,晶振这么脆弱么,我看其他板也不是很严格隔开晶振啊。有没有大佬有相关经验,可以提供一下建议?

      cb53b029-45cd-44ae-9ba4-de3bbd1c01dc-image.png

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        tivon LV 6 @eddylin last edited by

        @eddylin 网上看到的不知道行不行,你可以试一试
        uboot dts开启wp和hold的内部上拉,默认的只开启了CS的内部上拉
        &spi0_pins_b {
        allwinner,pins = "PC3", "PC7", "PC6";
        allwinner,pname = "spi0_cs0", "spi0_hold", "spi0_wp";
        allwinner,function = "spi0";
        allwinner,muxsel = <2>;
        allwinner,drive = <1>;
        allwinner,pull = <1>; /* cs, hold, wp should be pulled up */
        };

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          eddylin LV 3 @tivon last edited by

          @tivon 谢谢回复。这两个脚我看了一下,sdk默认有上拉了,而且我的硬件上也有电阻进行上拉。不过还是不行。

                  spi0_pins_a: spi0@0 {
                          pins = "PC2", "PC4", "PC5"; /* clk, mosi, miso */
                          function = "spi0";
                          muxsel = <2>;
                          drive-strength = <20>;
                  };
          
                  spi0_pins_b: spi0@1 {
                          pins = "PC3", "PC7", "PC6";
                          function = "spi0";
                          muxsel = <2>;
                          drive-strength = <20>;
                          bias-pull-up;   /* cs, hold, wp should be pulled up */
                  };
          
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            tivon LV 6 @eddylin last edited by

            @eddylin 有没有考虑过4线模式就是PC口的SDC2接口模式(应该是EMMC这样接),把spi-nand,按这种接法接不知道可行不,可以飞线试试
            SDC2.png

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            • T
              tivon LV 6 last edited by

              可以参考【FAQ2635】 spi-nand(HYF2GQ4UAACAE)-4线模式烧录失败 可能会有用

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                eddylin LV 3 @tivon last edited by

                @tivon 我没有这些文档……资料都是在论坛找的,实在没啥资料。

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                  tivon LV 6 @eddylin last edited by

                  @eddylin 全志客户服务平台,注册一个进去就能找到了

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                  • J
                    Jingyan LV 5 @tivon last edited by

                    @tivon 如果怀疑信号质量、干扰,或走线、等长、完整性的影响,尝试:

                    1. 降速
                    2. 提高IO驱动能力
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                      tivon LV 6 @eddylin last edited by

                      @eddylin 你好现在解决了吗?,我也遇到相同问题了,目前跑的1线模式。

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                        tivon LV 6 @tivon last edited by

                        @tivon 问题解决,开启wp和hold的内部上拉,把驱动能力改为10

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                          eddylin LV 3 @tivon last edited by

                          @tivon 你好,内部上来就是bias-pull-up;吧?drive-strength默认是10的,后来改大了也不行。
                          能提供一下你的设备树配置我参考一下么?还有就是,我的电路上这两个脚已经有电阻在外部上拉了,请问你的电路是怎样呢?有这些外部电阻么?

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                            tivon LV 6 @eddylin last edited by

                            修改内核设备树:

                            	spi0_pins_a: spi0@0 {
                            		pins = "PC2", "PC4", "PC5"; /*clk mosi miso hold wp*/
                            		function = "spi0";
                            		drive-strength = <10>;
                            	};
                            
                            	spi0_pins_b: spi0@1 {
                            		pins = "PC3", "PC7", "PC6";
                            		function = "spi0";
                            		drive-strength = <10>;
                            		bias-pull-up;   /* only CS should be pulled up */
                            	};
                            
                            
                            	spi0_pins_c: spi0@2 {
                            		pins = "PC2", "PC3", "PC4", "PC5","PC6", "PC7";
                            		function = "gpio_in";
                            		drive-strength = <10>;
                            	};
                            

                            修改uboot设备树:

                            &spi0_pins_a {
                            	allwinner,pins = "PC2", "PC4", "PC5";
                            	allwinner,pname = "spi0_sclk", "spi0_mosi","spi0_miso";
                            	allwinner,function = "spi0";
                            	allwinner,muxsel = <2>;
                            	allwinner,drive = <10>;
                            	allwinner,pull = <0>;
                            };
                            
                            &spi0_pins_b {
                              allwinner,pins = "PC3", "PC7", "PC6";
                              allwinner,pname = "spi0_cs0", "spi0_hold", "spi0_wp";
                              allwinner,function = "spi0";
                              allwinner,muxsel = <2>;
                              allwinner,drive = <10>;
                              allwinner,pull = <1>; /* cs, hold, wp should be pulled up */
                            };
                            
                            &spi0_pins_c {
                            	allwinner,pins = "PC2", "PC3", "PC4", "PC5",
                            			"PC6", "PC7";
                            	allwinner,function = "gpio_in";
                            	allwinner,muxsel = <0>;
                            	allwinner,drive = <1>;
                            	allwinner,pull = <0>;
                            };
                            
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                              tivon LV 6 @eddylin last edited by

                              @eddylin 电路上,clk串了个33欧电阻,其他都是直连,没有外部上拉电阻

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                                eddylin LV 3 @tivon last edited by

                                @tivon 谢谢回复,不过对我的板没用。都被气笑了,为了几根线改板了两次,线尽量短,而且远离其他晶振等东西,但是越改越差。真不知道怎么折腾了。我看开源硬件那里的人做的线比我随便多了 。不想再折腾它了。不过还是真的谢谢。

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