全志在线开发者论坛

awwwwa

@towel_roll rootfs空间太大了把UDSIK都占了

awwwwa

先确定挂载overlayfs

查看 pseudo_init 中 MOUNT_OVERLAY 是不是 1，如果不是配置为 1

package/busybox-init-base-files/files/pseudo_init

修改挂载分区

找到文件末尾，吧 rootfs_data 改成UDISK

awwwwa

@towel_roll dmesg看一下为什么没有挂载上

awwwwa

mount看看overlayfs挂载了吗

awwwwa

一、简介

tina 使用busybox init方式启动，首先调用执行pseudo_init（挂载文件系统，如/proc、/tmp、/sys /etc、/usr），接着会调用/sbin/init进程，而init进程调用的第一个启动脚本为/etc/init.d/rcS。

二、平台的自定义
不同的平台文件系统具有其共性与特殊性。tina/packge/busybox-init-base-files/files下提供了所有平台的基础文件。而在tina/target/allwinner/XXX/busybox-init-base-files下存放的是平台特性文件，其优先级高于前者,即当前者目录和后者存在有相同文件时，以后者为准。如有以下两个文件:

A：tina/target/allwinner/r11-R11_pref1/busybox-init-base-files/etc/banner
B：tina/package/busybox-init-base-files/files/etc/banner

最终拷贝到文件系统中的为A。

三、pseudo_init与rcS
pseudo_init与rcS文件中存在很多平台共性的代码，避免系统充斥大量冗余代码,以及方便基础文件的维护和开发。所以不允许在特定平台下自定义pseudo_init、rcS文件（必须使用tina/packge/busybox-init-base-files/files下的pseudo_init、rcS）。
如果需要添加平台特定配置（pseudo_init，rcS没有配置），可将其写到rc.preboot,rc.final中，参考第四节。

四、rcS脚本
1.功能描述
（1）执行/etc/init.d/rc.preboot。
为了满足开机快速启动的需求，提供了用户可自定义rc.preboot文件，即在tina/target/allwinner/XXX/busybox-init-base-files/etc/init.d/目录下创建rc.preboot脚本文件，将会被rcS最先调用执行。
（2）配置打印级别，主机名称。
（3）执行/etc/init.d/rc.log，配置系统log信息。
系统默认使用的是tina/package/busybox-init-base-files/files/etc/init.d/rc.log脚本进行配置系统log信息。用户可在tina/target/allwinner/XXX/busybox-init-base-files/etc/init.d/下创建rc.log，自定义rc.log。
如果需要使用默认rc.log，需要在make menuconfig配置。

	Base system  --->
	 busybox-init-base-files......................... Busybox init base system  --->
	  [*]   Use the rc.log

（4）挂载UDISK。
（5）执行/etc/init.d/rc.modules，加载内核模块。
系统默认使用的是tina/package/busybox-init-base-files/files/etc/init.d/rc.modules脚本进行内核模块自加载，用户可在tina/target/allwinner/XXX/busybox-init-base-files/etc/init.d/下创建rc.modules，自定义rc.modules。
如果需要使用默认rc.modules，需要在make menuconfig配置如下。

	Base system  --->
	 busybox-init-base-files......................... Busybox init base system  --->
	   [*]   Use the rc.modules

（6）启动/etc/rc.d下的脚本。

关于执行rc.d下的启动脚本，目的为兼容procd式的应用脚本。/etc/rc.d下的脚本是链接到/etc/init.d/下，默认情况下只执行adbd,如果需要执行其他脚本，需要在tina/target/allwinner/XXX/busybox-init-base-files/etc/init.d/下，自定义load_script.conf文件，文件内容中写上要启动的应用，如adbd（注意，每一个应用占一行）。可参考：tina/packge/busybox-init-base-files/files/etc/init.d/load_script.conf。

	如果需要执行rc.d下的启动脚本，需要在make menuconfig做如下配置。
	Base system  --->
	 busybox-init-base-files......................... Busybox init base system  --->
	   [*]   Auto load the script in /etc/rc.d

（7）ota初始化。

（8）执行/etc/init.d/rc.final,用户自定义启动脚本。
用户可在tina/packge/busybox-init-base-files/files/etc/init.d/下创建一个rc.final脚本，自定义启动应用程序,该脚本将会被rcS最后调用执行。

2.rc.preboot与rc.final的区别？
rc.preboot比rc.final先运行，在执行rc.preboot脚本的时候，系统的一些初始化操作还没完成，如挂载UDISK、内核模块自加载、ota等等操作。而rc.final执行的时候，以上的初始化操作已经完成。

五.如何写应用的启动脚本

example：开机自启动smartlinkd（tina/package/allwinner/smartlinkd/files/smartlinkd.init）
1.方法一（特定格式要求）

详细的格式参考：
https://wiki.openwrt.org/inbox/procd-init-scripts
https://wiki.openwrt.org/doc/techref/initscripts

（1）procd式

#!/bin/sh /etc/rc.common   #本质为script脚本,以#!开头, 之后执行/etc/rc.common
START=98		#开机启动优先级(序列) [数值越小, 越先启动]
STOP=98			#关机停止优先级(序列) [数值越小, 越先关闭]

USE_PROCD=1
PROG=smartlinkd

start_service() {    #启动函数
    procd_open_instance
    procd_set_param command $PROG -d
    procd_close_instance
}

shutdown() {
    echo shutdown
}

（2）Sys式

#!/bin/sh /etc/rc.common
START=98
STOP=98

PROG=smartlinkd

start() {
  smartlinkd -d &
}

使用上述procd式和sys式脚本，既能兼容procd init启动和busybox init的启动方式。
另外如果使用的是busybox init的启动方式，还需要在load_script.conf文件中换行添加内容：smartlinkd

2.方法二（无特定格式要求）
创建rc.preboot或者rc.final脚本，添加启动smartlinkd的内容。

awwwwa

@duanzhh 请问SDK是哪里获取的？据我所知CAN目前在T113-I的平台上有压测过，T113-S3的SDK里的驱动可能是很早期的版本

awwwwa

dmesg -n 1 再运行测试命令

awwwwa

可以，默认启动顺序其实就是从SD卡

awwwwa

在UBOOT和Linux注释掉 SUNXI_DISP2

awwwwa

@duanzhh 高速建议用SPI，IIC，CAN代替，3M以上串口稳定性较差对走线要求较高

awwwwa

@duanzhh

SPC是安全控制模块，这个模块不对外开放，且只有安全模式中的CPU才能访问，正常可以无视。如果需要开发安全方案，请联系原厂

CCU就是配置时钟的控制器，手册里有详细说明

awwwwa

awwwwa

@kanken6174 不建议编译gcc进入固件，首先这个gcc没有适配平台，其次v851s的64M内存也无法支持gcc的使用

awwwwa

@kanken6174 在 V851s buildroot openwrt 警告中说：

忽略这些警告

忽略这些警告即可，这些是openwrt提供的软件包，暂时不适配v851s平台，所以有警告

awwwwa

最高支持3.75M波特率

awwwwa

会对挂在APB0_CLK上的全部外设造成影响

awwwwa

    static lv_style_t style_scr_act;
    if (style_scr_act.prop_cnt == 0) {
        lv_style_init(&style_scr_act);
        lv_style_set_bg_opa(&style_scr_act, LV_OPA_COVER);
        lv_obj_add_style(lv_scr_act(), &style_scr_act, 0);
    }
    lv_disp_get_default()->driver->screen_transp = 1;
    lv_disp_set_bg_opa(lv_disp_get_default(), LV_OPA_TRANSP);
    /* Empty the buffer, not emptying will cause the UI to be opaque */
    lv_memset_00(lv_disp_get_default()->driver->draw_buf->buf_act,
    lv_disp_get_default()->driver->draw_buf->size * sizeof(lv_color32_t));
    lv_style_set_bg_opa(&style_scr_act, LV_OPA_TRANSP);
    lv_obj_report_style_change(&style_scr_act);

设置透明层

awwwwa

https://r128.docs.aw-ol.com/r128/chip_info/#gpio

awwwwa

@oneofzero 待正式版1.0SDK发布后会从论坛开放

awwwwa

@oneofzero 删除这两个文件可以用吗

awwwwa

@chrisvista 不可以用RT-Thread的HAL库吗？

awwwwa

@oneofzero 这个是，直接从其他sdk复制过来的吗？、

rm -rf out
rm -rf lichee/rtos/build/

awwwwa

先删除预解压的工具链，再重新解压。这是因为之前解压工具链解压未完成导致丢失文件。

rm -rf lichee/rtos/tools/riscv64-elf-x86_64-20201104

awwwwa

@chrisvista 在全志T113-i 或者V85X MIPI DSI 寻求控制器寄存器资料中说：

统定义里面不停更新，比如第一个就已经改变了：

A64的MIPI DSI是使用的 synopsys 的，T113的不是这个IP，所以有差异

awwwwa

芯片寄存器开放有很多因素制约，大部分外购的IP都不允许详细描述寄存器，需要提交申请审核后才能公开，法务流程很长索性不开放，开放了还会有潜在的法律风险和抄袭风险，再加上IP迭代和升级，勘误和修改。所以一般是需要定制化的客户有专门的对接。国外芯片自己自研的IP或者购买的IP走了审核流程的开放，也有很多芯片不开放，需要NDA后专门对接。

其实国外做的好的也就TI，NXP，ST那几家的芯片，博通高通一样没啥资料。

awwwwa

/*
 * Detail information of registers
 */
union dsi_ctl_reg_t {
	u32 dwval;
	struct {
		u32 dsi_en:1;
		u32 res0:31;
	} bits;
};

union dsi_gint0_reg_t {
	u32 dwval;
	struct {
		u32 dsi_irq_en:16;
		u32 dsi_irq_flag:16;
	} bits;
};

union dsi_gint1_reg_t {
	u32 dwval;
	struct {
		u32 video_line_int_num:13;
		u32 res0:19;
	} bits;
};

union dsi_basic_ctl_reg_t {
	u32 dwval;
	struct {
		u32 video_mode_burst:1;
		u32 hsa_hse_dis:1;
		u32 hbp_dis:1;
		u32 trail_fill:1;
		u32 trail_inv:4;
		u32 res0:8;
		u32 brdy_set:8;
		u32 brdy_l_sel:3;
		u32 res1:5;
	} bits;
};

union dsi_basic_ctl0_reg_t {
	u32 dwval;
	struct {
		u32 inst_st:1;
		u32 res0:3;
		u32 src_sel:2;
		u32 res1:4;
		u32 fifo_manual_reset:1;
		u32 res2:1;
		u32 fifo_gating:1;
		u32 res3:3;
		u32 ecc_en:1;
		u32 crc_en:1;
		u32 hs_eotp_en:1;
		u32 res4:13;
	} bits;
};

union dsi_basic_ctl1_reg_t {
	u32 dwval;
	struct {
		u32 dsi_mode:1;
		u32 video_frame_start:1;
		u32 video_precision_mode_align:1;
		u32 res0:1;
		u32 video_start_delay:13;
		u32 res1:15;
	} bits;
};

union dsi_basic_size0_reg_t {
	u32 dwval;
	struct {
		u32 vsa:12;
		u32 res0:4;
		u32 vbp:12;
		u32 res1:4;
	} bits;
};

union dsi_basic_size1_reg_t {
	u32 dwval;
	struct {
		u32 vact:12;
		u32 res0:4;
		u32 vt:13;
		u32 res1:3;
	} bits;
};

union dsi_basic_inst0_reg_t {
	u32 dwval;
	struct {
		u32 lane_den:4;
		u32 lane_cen:1;
		u32 res0:11;
		u32 trans_start_condition:4;
		u32 trans_packet:4;
		u32 escape_enrty:4;
		u32 instru_mode:4;
	} bits;
};

union dsi_basic_inst1_reg_t {
	u32 dwval;
	struct {
		u32 inst0_sel:4;
		u32 inst1_sel:4;
		u32 inst2_sel:4;
		u32 inst3_sel:4;
		u32 inst4_sel:4;
		u32 inst5_sel:4;
		u32 inst6_sel:4;
		u32 inst7_sel:4;
	} bits;
};

union dsi_basic_inst2_reg_t {
	u32 dwval;
	struct {
		u32 loop_n0:12;
		u32 res0:4;
		u32 loop_n1:12;
		u32 res1:4;
	} bits;
};

union dsi_basic_inst3_reg_t {
	u32 dwval;
	struct {
		u32 inst0_jump:4;
		u32 inst1_jump:4;
		u32 inst2_jump:4;
		u32 inst3_jump:4;
		u32 inst4_jump:4;
		u32 inst5_jump:4;
		u32 inst6_jump:4;
		u32 inst7_jump:4;
	} bits;
};

union dsi_basic_inst4_reg_t {
	u32 dwval;
	struct {
		u32 jump_cfg_num:16;
		u32 jump_cfg_point:4;
		u32 jump_cfg_to:4;
		u32 res0:4;
		u32 jump_cfg_en:1;
		u32 res1:3;
	} bits;
};

union dsi_basic_tran0_reg_t {
	u32 dwval;
	struct {
		u32 trans_start_set:13;
		u32 res0:19;
	} bits;
};

union dsi_basic_tran1_reg_t {
	u32 dwval;
	struct {
		u32 trans_size:16;
		u32 res0:12;
		u32 trans_end_condition:1;
		u32 res1:3;
	} bits;
};

union dsi_basic_tran2_reg_t {
	u32 dwval;
	struct {
		u32 trans_cycle_set:16;
		u32 res0:16;
	} bits;
};

union dsi_basic_tran3_reg_t {
	u32 dwval;
	struct {
		u32 trans_blank_set:16;
		u32 res0:16;
	} bits;
};

union dsi_basic_tran4_reg_t {
	u32 dwval;
	struct {
		u32 hs_zero_reduce_set:16;
		u32 res0:16;
	} bits;
};

union dsi_basic_tran5_reg_t {
	u32 dwval;
	struct {
		u32 drq_set:10;
		u32 res0:18;
		u32 drq_mode:1;
		u32 res1:3;
	} bits;
};

union dsi_pixel_ctl0_reg_t {
	u32 dwval;
	struct {
		u32 pixel_format:4;
		u32 pixel_endian:1;
		u32 res0:11;
		u32 pd_plug_dis:1;
		u32 res1:15;
	} bits;
};

union dsi_pixel_ctl1_reg_t {
	u32 dwval;
	struct {
		u32 res0;
	} bits;
};

union dsi_pixel_ph_reg_t {
	u32 dwval;
	struct {
		u32 dt:6;
		u32 vc:2;
		u32 wc:16;
		u32 ecc:8;
	} bits;
};

union dsi_pixel_pd_reg_t {
	u32 dwval;
	struct {
		u32 pd_tran0:8;
		u32 res0:8;
		u32 pd_trann:8;
		u32 res1:8;
	} bits;
};

union dsi_pixel_pf0_reg_t {
	u32 dwval;
	struct {
		u32 crc_force:16;
		u32 res0:16;
	} bits;
};

union dsi_pixel_pf1_reg_t {
	u32 dwval;
	struct {
		u32 crc_init_line0:16;
		u32 crc_init_linen:16;
	} bits;
};

union dsi_short_pkg_reg_t {
	u32 dwval;
	struct {
		u32 dt:6;
		u32 vc:2;
		u32 d0:8;
		u32 d1:8;
		u32 ecc:8;
	} bits;
};

union dsi_blk_pkg0_reg_t {
	u32 dwval;
	struct {
		u32 dt:6;
		u32 vc:2;
		u32 wc:16;
		u32 ecc:8;
	} bits;
};

union dsi_blk_pkg1_reg_t {
	u32 dwval;
	struct {
		u32 pd:8;
		u32 res0:8;
		u32 pf:16;
	} bits;
};

union dsi_burst_line_reg_t {
	u32 dwval;
	struct {
		u32 line_num:16;
		u32 line_syncpoint:16;
	} bits;
};

union dsi_burst_drq_reg_t {
	u32 dwval;
	struct {
		u32 drq_edge0:16;
		u32 drq_edge1:16;
	} bits;
};

union dsi_cmd_ctl_reg_t {
	u32 dwval;
	struct {
		u32 tx_size:8;
		u32 tx_status:1;
		u32 tx_flag:1;
		u32 res0:6;
		u32 rx_size:5;
		u32 res1:3;
		u32 rx_status:1;
		u32 rx_flag:1;
		u32 rx_overflow:1;
		u32 res2:5;
	} bits;
};

union dsi_cmd_data_reg_t {
	u32 dwval;
	struct {
		u32 byte0:8;
		u32 byte1:8;
		u32 byte2:8;
		u32 byte3:8;
	} bits;
};

union dsi_debug0_reg_t {
	u32 dwval;
	struct {
		u32 video_curr_line:13;
		u32 res0:19;
	} bits;
};

union dsi_debug1_reg_t {
	u32 dwval;
	struct {
		u32 video_curr_lp2hs:16;
		u32 res0:16;
	} bits;
};

union dsi_debug2_reg_t {
	u32 dwval;
	struct {
		u32 trans_low_flag:1;
		u32 trans_fast_flag:1;
		u32 res0:2;
		u32 curr_loop_num:16;
		u32 curr_instru_num:3;
		u32 res1:1;
		u32 instru_unknown_flag:8;
	} bits;
};

union dsi_debug3_reg_t {
	u32 dwval;
	struct {
		u32 res0:16;
		u32 curr_fifo_num:16;
	} bits;
};

union dsi_debug4_reg_t {
	u32 dwval;
	struct {
		u32 test_data:24;
		u32 res0:4;
		u32 dsi_fifo_bist_en:1;
		u32 res1:3;
	} bits;
};

union dsi_reservd_reg_t {
	u32 dwval;
	struct {
		u32 res0;
	} bits;
};

struct __de_dsi_dev_t {
	/* 0x00 - 0x0c */
	union dsi_ctl_reg_t dsi_gctl;
	union dsi_gint0_reg_t dsi_gint0;
	union dsi_gint1_reg_t dsi_gint1;
	union dsi_basic_ctl_reg_t dsi_basic_ctl;
	/* 0x10 - 0x1c */
	union dsi_basic_ctl0_reg_t dsi_basic_ctl0;
	union dsi_basic_ctl1_reg_t dsi_basic_ctl1;
	union dsi_basic_size0_reg_t dsi_basic_size0;
	union dsi_basic_size1_reg_t dsi_basic_size1;
	/* 0x20 - 0x3c */
	union dsi_basic_inst0_reg_t dsi_inst_func[8];
	/* 0x40 - 0x5c */
	union dsi_basic_inst1_reg_t dsi_inst_loop_sel;
	union dsi_basic_inst2_reg_t dsi_inst_loop_num;
	union dsi_basic_inst3_reg_t dsi_inst_jump_sel;
	union dsi_basic_inst4_reg_t dsi_inst_jump_cfg[2];
	union dsi_basic_inst2_reg_t dsi_inst_loop_num2;
	union dsi_reservd_reg_t dsi_reg058[2];
	/* 0x60 - 0x6c */
	union dsi_basic_tran0_reg_t dsi_trans_start;
	union dsi_reservd_reg_t dsi_reg064[3];
	/* 0x70 - 0x7c */
	union dsi_reservd_reg_t dsi_reg070[2];
	union dsi_basic_tran4_reg_t dsi_trans_zero;
	union dsi_basic_tran5_reg_t dsi_tcon_drq;
	/* 0x80 - 0x8c */
	union dsi_pixel_ctl0_reg_t dsi_pixel_ctl0;
	union dsi_pixel_ctl1_reg_t dsi_pixel_ctl1;
	union dsi_reservd_reg_t dsi_reg088[2];
	/* 0x90 - 0x9c */
	union dsi_pixel_ph_reg_t dsi_pixel_ph;
	union dsi_pixel_pd_reg_t dsi_pixel_pd;
	union dsi_pixel_pf0_reg_t dsi_pixel_pf0;
	union dsi_pixel_pf1_reg_t dsi_pixel_pf1;
	/* 0xa0 - 0xac */
	union dsi_reservd_reg_t dsi_reg0a0[4];
	/* 0xb0 - 0xbc */
	union dsi_short_pkg_reg_t dsi_sync_hss;
	union dsi_short_pkg_reg_t dsi_sync_hse;
	union dsi_short_pkg_reg_t dsi_sync_vss;
	union dsi_short_pkg_reg_t dsi_sync_vse;
	/* 0xc0 - 0xcc */
	union dsi_blk_pkg0_reg_t dsi_blk_hsa0;
	union dsi_blk_pkg1_reg_t dsi_blk_hsa1;
	union dsi_blk_pkg0_reg_t dsi_blk_hbp0;
	union dsi_blk_pkg1_reg_t dsi_blk_hbp1;
	/* 0xd0 - 0xdc */
	union dsi_blk_pkg0_reg_t dsi_blk_hfp0;
	union dsi_blk_pkg1_reg_t dsi_blk_hfp1;
	union dsi_reservd_reg_t dsi_reg0d8[2];
	/* 0xe0 - 0xec */
	union dsi_blk_pkg0_reg_t dsi_blk_hblk0;
	union dsi_blk_pkg1_reg_t dsi_blk_hblk1;
	union dsi_blk_pkg0_reg_t dsi_blk_vblk0;
	union dsi_blk_pkg1_reg_t dsi_blk_vblk1;
	/* 0xf0 - 0x1fc */
	union dsi_burst_line_reg_t dsi_burst_line;
	union dsi_burst_drq_reg_t dsi_burst_drq;
	union dsi_reservd_reg_t dsi_reg0f0[66];
	/* 0x200 - 0x23c */
	union dsi_cmd_ctl_reg_t dsi_cmd_ctl;
	union dsi_reservd_reg_t dsi_reg204[15];
	/* 0x240 - 0x2dc */
	union dsi_cmd_data_reg_t dsi_cmd_rx[8];
	union dsi_reservd_reg_t dsi_reg260[32];
	/* 0x2e0 - 0x2ec */
	union dsi_debug0_reg_t dsi_debug_video0;
	union dsi_debug1_reg_t dsi_debug_video1;
	union dsi_reservd_reg_t dsi_reg2e8[2];
	/* 0x2f0 - 0x2fc */
	union dsi_debug2_reg_t dsi_debug_inst;
	union dsi_debug3_reg_t dsi_debug_fifo;
	union dsi_debug4_reg_t dsi_debug_data;
	union dsi_reservd_reg_t dsi_reg2fc;
	/* 0x300 - 0x3fc */
	union dsi_cmd_data_reg_t dsi_cmd_tx[64];
};

union dphy_ctl_reg_t {
	u32 dwval;
	struct {
		u32 module_en:1;
		u32 res0:3;
		u32 lane_num:2;
		u32 res1:26;
	} bits;
};

union dphy_tx_ctl_reg_t {
	u32 dwval;
	struct {
		u32 tx_d0_force:1;
		u32 tx_d1_force:1;
		u32 tx_d2_force:1;
		u32 tx_d3_force:1;
		u32 tx_clk_force:1;
		u32 res0:3;
		u32 lptx_endian:1;
		u32 hstx_endian:1;
		u32 lptx_8b9b_en:1;
		u32 hstx_8b9b_en:1;
		u32 force_lp11:1;
		u32 res1:3;
		u32 ulpstx_data0_exit:1;
		u32 ulpstx_data1_exit:1;
		u32 ulpstx_data2_exit:1;
		u32 ulpstx_data3_exit:1;
		u32 ulpstx_clk_exit:1;
		u32 res2:3;
		u32 hstx_data_exit:1;
		u32 hstx_clk_exit:1;
		u32 res3:2;
		u32 hstx_clk_cont:1;
		u32 ulpstx_enter:1;
		u32 res4:2;
	} bits;
};

union dphy_rx_ctl_reg_t {
	u32 dwval;
	struct {
		u32 res0:8;
		u32 lprx_endian:1;
		u32 hsrx_endian:1;
		u32 lprx_8b9b_en:1;
		u32 hsrx_8b9b_en:1;
		u32 hsrx_sync:1;
		u32 res1:3;
		u32 lprx_trnd_mask:4;
		u32 rx_d0_force:1;
		u32 rx_d1_force:1;
		u32 rx_d2_force:1;
		u32 rx_d3_force:1;
		u32 rx_clk_force:1;
		u32 res2:6;
		u32 dbc_en:1;
	} bits;
};

union dphy_tx_time0_reg_t {
	u32 dwval;
	struct {
		u32 lpx_tm_set:8;
		u32 dterm_set:8;
		u32 hs_pre_set:8;
		u32 hs_trail_set:8;
	} bits;
};

union dphy_tx_time1_reg_t {
	u32 dwval;
	struct {
		u32 ck_prep_set:8;
		u32 ck_zero_set:8;
		u32 ck_pre_set:8;
		u32 ck_post_set:8;
	} bits;
};

union dphy_tx_time2_reg_t {
	u32 dwval;
	struct {
		u32 ck_trail_set:8;
		u32 hs_dly_set:16;
		u32 res0:4;
		u32 hs_dly_mode:1;
		u32 res1:3;
	} bits;
};

union dphy_tx_time3_reg_t {
	u32 dwval;
	struct {
		u32 lptx_ulps_exit_set:20;
		u32 res0:12;
	} bits;
};

union dphy_tx_time4_reg_t {
	u32 dwval;
	struct {
		u32 hstx_ana0_set:8;
		u32 hstx_ana1_set:8;
		u32 res0:16;
	} bits;
};

union dphy_rx_time0_reg_t {
	u32 dwval;
	struct {
		u32 lprx_to_en:1;
		u32 freq_cnt_en:1;
		u32 res0:2;
		u32 hsrx_clk_miss_en:1;
		u32 hsrx_sync_err_to_en:1;
		u32 res1:2;
		u32 lprx_to:8;
		u32 hsrx_clk_miss:8;
		u32 hsrx_sync_err_to:8;
	} bits;
};

union dphy_rx_time1_reg_t {
	u32 dwval;
	struct {
		u32 lprx_ulps_wp:20;
		u32 rx_dly:12;
	} bits;
};

union dphy_rx_time2_reg_t {
	u32 dwval;
	struct {
		u32 hsrx_ana0_set:8;
		u32 hsrx_ana1_set:8;
		u32 res0:16;
	} bits;
};

union dphy_rx_time3_reg_t {
	u32 dwval;
	struct {
		u32 freq_cnt:16;
		u32 res0:8;
		u32 lprst_dly:8;
	} bits;
};

union dphy_ana0_reg_t {
	u32 dwval;
	struct {
		u32 reg_selsck:1;
		u32 reg_rsd:1;
		u32 reg_sfb:2;
		u32 reg_plr:4;
		u32 reg_den:4;
		u32 reg_slv:3;
		u32 reg_sdiv2:1;
		u32 reg_srxck:4;
		u32 reg_srxdt:4;
		u32 reg_dmpd:4;
		u32 reg_dmpc:1;
		u32 reg_pwenc:1;
		u32 reg_pwend:1;
		u32 reg_pws:1;
	} bits;
};

union dphy_ana1_reg_t {
	u32 dwval;
	struct {
		u32 reg_stxck:1;
		u32 res0:3;
		u32 reg_svdl0:4;
		u32 reg_svdl1:4;
		u32 reg_svdl2:4;
		u32 reg_svdl3:4;
		u32 reg_svdlc:4;
		u32 reg_svtt:4;
		u32 reg_csmps:2;
		u32 res1:1;
		u32 reg_vttmode:1;
	} bits;
};

union dphy_ana2_reg_t {
	u32 dwval;
	struct {
		u32 ana_cpu_en:1;
		u32 enib:1;
		u32 enrvs:1;
		u32 res0:1;
		u32 enck_cpu:1;
		u32 entxc_cpu:1;
		u32 enckq_cpu:1;
		u32 res1:1;
		u32 entx_cpu:4;
		u32 res2:1;
		u32 entermc_cpu:1;
		u32 enrxc_cpu:1;
		u32 res3:1;
		u32 enterm_cpu:4;
		u32 enrx_cpu:4;
		u32 enp2s_cpu:4;
		u32 res4:4;
	} bits;
};

union dphy_ana3_reg_t {
	u32 dwval;
	struct {
		u32 enlptx_cpu:4;
		u32 enlprx_cpu:4;
		u32 enlpcd_cpu:4;
		u32 enlprxc_cpu:1;
		u32 enlptxc_cpu:1;
		u32 enlpcdc_cpu:1;
		u32 res0:1;
		u32 entest:1;
		u32 enckdbg:1;
		u32 enldor:1;
		u32 res1:5;
		u32 enldod:1;
		u32 enldoc:1;
		u32 endiv:1;
		u32 envttc:1;
		u32 envttd:4;
	} bits;
};

union dphy_ana4_reg_t {
	u32 dwval;
	struct {
		u32 reg_txpusd:2;
		u32 reg_txpusc:2;
		u32 reg_txdnsd:2;
		u32 reg_txdnsc:2;
		u32 reg_tmsd:2;
		u32 reg_tmsc:2;
		u32 reg_ckdv:5;
		u32 reg_vtt_set:3;
		u32 reg_dmplvd:4;
		u32 reg_dmplvc:1;
		u32 reg_ib:2;
		u32 res4:1;
		u32 reg_comtest:2;
		u32 en_comtest:1;
		u32 en_mipi:1;

	} bits;
};

union dphy_int_en0_reg_t {
	u32 dwval;
	struct {
		u32 sot_d0_int:1;
		u32 sot_d1_int:1;
		u32 sot_d2_int:1;
		u32 sot_d3_int:1;
		u32 sot_err_d0_int:1;
		u32 sot_err_d1_int:1;
		u32 sot_err_d2_int:1;
		u32 sot_err_d3_int:1;
		u32 sot_sync_err_d0_int:1;
		u32 sot_sync_err_d1_int:1;
		u32 sot_sync_err_d2_int:1;
		u32 sot_sync_err_d3_int:1;
		u32 rx_alg_err_d0_int:1;
		u32 rx_alg_err_d1_int:1;
		u32 rx_alg_err_d2_int:1;
		u32 rx_alg_err_d3_int:1;
		u32 res0:6;
		u32 cd_lp0_err_clk_int:1;
		u32 cd_lp1_err_clk_int:1;
		u32 cd_lp0_err_d0_int:1;
		u32 cd_lp1_err_d0_int:1;
		u32 cd_lp0_err_d1_int:1;
		u32 cd_lp1_err_d1_int:1;
		u32 cd_lp0_err_d2_int:1;
		u32 cd_lp1_err_d2_int:1;
		u32 cd_lp0_err_d3_int:1;
		u32 cd_lp1_err_d3_int:1;
	} bits;
};

union dphy_int_en1_reg_t {
	u32 dwval;
	struct {
		u32 ulps_d0_int:1;
		u32 ulps_d1_int:1;
		u32 ulps_d2_int:1;
		u32 ulps_d3_int:1;
		u32 ulps_wp_d0_int:1;
		u32 ulps_wp_d1_int:1;
		u32 ulps_wp_d2_int:1;
		u32 ulps_wp_d3_int:1;
		u32 ulps_clk_int:1;
		u32 ulps_wp_clk_int:1;
		u32 res0:2;
		u32 lpdt_d0_int:1;
		u32 rx_trnd_d0_int:1;
		u32 tx_trnd_err_d0_int:1;
		u32 undef1_d0_int:1;
		u32 undef2_d0_int:1;
		u32 undef3_d0_int:1;
		u32 undef4_d0_int:1;
		u32 undef5_d0_int:1;
		u32 rst_d0_int:1;
		u32 rst_d1_int:1;
		u32 rst_d2_int:1;
		u32 rst_d3_int:1;
		u32 esc_cmd_err_d0_int:1;
		u32 esc_cmd_err_d1_int:1;
		u32 esc_cmd_err_d2_int:1;
		u32 esc_cmd_err_d3_int:1;
		u32 false_ctl_d0_int:1;
		u32 false_ctl_d1_int:1;
		u32 false_ctl_d2_int:1;
		u32 false_ctl_d3_int:1;
	} bits;
};

union dphy_int_en2_reg_t {
	u32 dwval;
	struct {
		u32 res0;
	} bits;
};

union dphy_int_pd0_reg_t {
	u32 dwval;
	struct {
		u32 sot_d0_pd:1;
		u32 sot_d1_pd:1;
		u32 sot_d2_pd:1;
		u32 sot_d3_pd:1;
		u32 sot_err_d0_pd:1;
		u32 sot_err_d1_pd:1;
		u32 sot_err_d2_pd:1;
		u32 sot_err_d3_pd:1;
		u32 sot_sync_err_d0_pd:1;
		u32 sot_sync_err_d1_pd:1;
		u32 sot_sync_err_d2_pd:1;
		u32 sot_sync_err_d3_pd:1;
		u32 rx_alg_err_d0_pd:1;
		u32 rx_alg_err_d1_pd:1;
		u32 rx_alg_err_d2_pd:1;
		u32 rx_alg_err_d3_pd:1;
		u32 res0:6;
		u32 cd_lp0_err_clk_pd:1;
		u32 cd_lp1_err_clk_pd:1;
		u32 cd_lp0_err_d1_pd:1;
		u32 cd_lp1_err_d1_pd:1;
		u32 cd_lp0_err_d0_pd:1;
		u32 cd_lp1_err_d0_pd:1;
		u32 cd_lp0_err_d2_pd:1;
		u32 cd_lp1_err_d2_pd:1;
		u32 cd_lp0_err_d3_pd:1;
		u32 cd_lp1_err_d3_pd:1;
	} bits;
};

union dphy_int_pd1_reg_t {
	u32 dwval;
	struct {
		u32 ulps_d0_pd:1;
		u32 ulps_d1_pd:1;
		u32 ulps_d2_pd:1;
		u32 ulps_d3_pd:1;
		u32 ulps_wp_d0_pd:1;
		u32 ulps_wp_d1_pd:1;
		u32 ulps_wp_d2_pd:1;
		u32 ulps_wp_d3_pd:1;
		u32 ulps_clk_pd:1;
		u32 ulps_wp_clk_pd:1;
		u32 res0:2;
		u32 lpdt_d0_pd:1;
		u32 rx_trnd_d0_pd:1;
		u32 tx_trnd_err_d0_pd:1;
		u32 undef1_d0_pd:1;
		u32 undef2_d0_pd:1;
		u32 undef3_d0_pd:1;
		u32 undef4_d0_pd:1;
		u32 undef5_d0_pd:1;
		u32 rst_d0_pd:1;
		u32 rst_d1_pd:1;
		u32 rst_d2_pd:1;
		u32 rst_d3_pd:1;
		u32 esc_cmd_err_d0_pd:1;
		u32 esc_cmd_err_d1_pd:1;
		u32 esc_cmd_err_d2_pd:1;
		u32 esc_cmd_err_d3_pd:1;
		u32 false_ctl_d0_pd:1;
		u32 false_ctl_d1_pd:1;
		u32 false_ctl_d2_pd:1;
		u32 false_ctl_d3_pd:1;
	} bits;
};

union dphy_int_pd2_reg_t {
	u32 dwval;
	struct {
		u32 res0;
	} bits;
};

union dphy_dbg0_reg_t {
	u32 dwval;
	struct {
		u32 lptx_sta_d0:3;
		u32 res0:1;
		u32 lptx_sta_d1:3;
		u32 res1:1;
		u32 lptx_sta_d2:3;
		u32 res2:1;
		u32 lptx_sta_d3:3;
		u32 res3:1;
		u32 lptx_sta_clk:3;
		u32 res4:9;
		u32 direction:1;
		u32 res5:3;
	} bits;
};

union dphy_dbg1_reg_t {
	u32 dwval;
	struct {
		u32 lptx_dbg_en:1;
		u32 hstx_dbg_en:1;
		u32 res0:2;
		u32 lptx_set_d0:2;
		u32 lptx_set_d1:2;
		u32 lptx_set_d2:2;
		u32 lptx_set_d3:2;
		u32 lptx_set_ck:2;
		u32 res1:18;
	} bits;
};

union dphy_dbg2_reg_t {
	u32 dwval;
	struct {
		u32 hstx_data;
	} bits;
};

union dphy_dbg3_reg_t {
	u32 dwval;
	struct {
		u32 lprx_sta_d0:4;
		u32 lprx_sta_d1:4;
		u32 lprx_sta_d2:4;
		u32 lprx_sta_d3:4;
		u32 lprx_sta_clk:4;
		u32 res0:12;
	} bits;
};

union dphy_dbg4_reg_t {
	u32 dwval;
	struct {
		u32 lprx_phy_d0:2;
		u32 lprx_phy_d1:2;
		u32 lprx_phy_d2:2;
		u32 lprx_phy_d3:2;
		u32 lprx_phy_clk:2;
		u32 res0:6;
		u32 lpcd_phy_d0:2;
		u32 lpcd_phy_d1:2;
		u32 lpcd_phy_d2:2;
		u32 lpcd_phy_d3:2;
		u32 lpcd_phy_clk:2;
		u32 res1:6;
	} bits;
};

union dphy_dbg5_reg_t {
	u32 dwval;
	struct {
		u32 hsrx_data;
	} bits;
};

union dphy_reservd_reg_t {
	u32 dwval;
	struct {
		u32 res0;
	} bits;
};


union dphy_tx_skew_reg0_t {
	__u32 dwavl;
	struct {
		__u32 reg_skewcal_sync     :  8 ;    // default: 0;
		__u32 reg_skewcal          :  8 ;    // default: 0;
		__u32 skewcal_trail_set    :  8 ;    // default: 0;
		__u32 skewcal_zero_set     :  8 ;    // default: 0;
	} bits;
};

union dphy_tx_skew_reg1_t {
	__u32 dwval;
	struct {
		__u32 skewcal_init_set      : 16 ;    // default: 0;
		__u32 skewcal_pedic_set     :  8 ;    // default: 0;
		__u32 skewcal_sync_set      :  8 ;    // default: 0;
	} bits;
};

union dphy_tx_skew_reg2_t {
	__u32 dwval;
	struct {
		__u32 skewcal_prepare_lp00   :  8 ;    //default: 0;
		__u32 skewcal_trail_inv      :  1 ;    //default: 0;
		__u32 en_skewcal_perdic      :  1 ;    //default: 0;
		__u32 en_skewcal_init        :  1 ;    //default: 0;
		__u32 res0                   : 21 ;    //default: 0;
	} bits;
};

union dphy_pll_reg0_t {
	__u32 dwval;
	struct {
		__u32 m1                      :  4 ;    //default: 0x3;
		__u32 m0                      :  2 ;    //default: 0;
		__u32 tdiv                    :  1 ;    //default: 0;
		__u32 ndet                    :  1 ;    //default: 0x1;
		__u32 n                       :  8 ;    //default: 0x32;
		__u32 p                       :  4 ;    //default: 0;
		__u32 pll_en                  :  1 ;    //default: 0x1;
		__u32 en_lvs                  :  1 ;    //default: 0x1;
		__u32 ldo_en                  :  1 ;    //default: 0x1;
		__u32 cp36_en                 :  1 ;    //default: 0x1;
		__u32 res0                    :  8 ;    //default: 0;
	} bits;
};

union dphy_pll_reg1_t {
	__u32 dwval;
	struct {
		__u32 test_en                  :  1 ;    //default: 0x1;
		__u32 atest_sel                :  2 ;    //default: 0;
		__u32 icp_sel                  :  2 ;    //default: 0;
		__u32 lpf_sw                   :  1 ;    //default: 0;
		__u32 vsetd                    :  3 ;    //default: 0x2;
		__u32 vseta                    :  3 ;    //default: 0x2;
		__u32 lockdet_en               :  1 ;    //default: 0;
		__u32 lockmdsel                :  1 ;    //default: 0;
		__u32 unlock_mdsel             :  2 ;    //default: 0;
		__u32 res0                     : 16 ;    //default: 0;
	} bits;
};

union dphy_pll_reg2_t {
	__u32 dwval;
	struct {
		__u32 frac                      : 12 ;    //default: 0x800;
		__u32 ss_int                    :  8 ;    //default: 0x32;
		__u32 ss_frac                   :  9 ;    //default: 0;
		__u32 ss_en                     :  1 ;    //default: 0;
		__u32 ff_en                     :  1 ;    //default: 0;
		__u32 sdm_en                    :  1 ;    //default: 0x1;
	} bits;
};

union combo_phy_reg0_t {
	__u32 dwval;
	struct {
		__u32 en_cp               :  1 ;    //default: 0;
		__u32 en_comboldo         :  1 ;    //default: 0;
		__u32 en_lvds             :  1 ;    //default: 0;
		__u32 en_mipi             :  1 ;    //default: 0;
		__u32 en_test_0p8         :  1 ;    //default: 0;
		__u32 en_test_comboldo    :  1 ;    //default: 0;
		__u32 res0                :  26;    //default: 0;
	} bits;
};

union combo_phy_reg1_t {
	__u32 dwval;
	struct {
		__u32 reg_vref0p8         :  3 ;    //default: 0;
		__u32 res0                :  1 ;    //default: 0;
		__u32 reg_vref1p6         :  3 ;    //default: 0;
		__u32 res1                :  25;    //default: 0;
	} bits;
};

union combo_phy_reg2_t {
	__u32 dwval;
	struct {
		__u32 hs_stop_dly         :  8 ;    //default: 0;
		__u32 res0                :  24;    //default: 0;
	} bits;
};

/* dphy register define */
struct __de_dsi_dphy_dev_t {
	/* 0x00 - 0x0c */
	union dphy_ctl_reg_t dphy_gctl;
	union dphy_tx_ctl_reg_t dphy_tx_ctl;
	union dphy_rx_ctl_reg_t dphy_rx_ctl;
	union dphy_reservd_reg_t dphy_reg00c;
	/* 0x10 - 0x1c */
	union dphy_tx_time0_reg_t dphy_tx_time0;
	union dphy_tx_time1_reg_t dphy_tx_time1;
	union dphy_tx_time2_reg_t dphy_tx_time2;
	union dphy_tx_time3_reg_t dphy_tx_time3;
	/* 0x20 - 0x2c */
	union dphy_tx_time4_reg_t dphy_tx_time4;
	union dphy_reservd_reg_t dphy_reg024[3];
	/* 0x30 - 0x3c */
	union dphy_rx_time0_reg_t dphy_rx_time0;
	union dphy_rx_time1_reg_t dphy_rx_time1;
	union dphy_rx_time2_reg_t dphy_rx_time2;
	union dphy_reservd_reg_t dphy_reg03c;
	/* 0x40 - 0x4c */
	union dphy_rx_time3_reg_t dphy_rx_time3;
	union dphy_reservd_reg_t dphy_reg044[2];
	union dphy_ana0_reg_t dphy_ana0;
	/* 0x50 - 0x5c */
	union dphy_ana1_reg_t dphy_ana1;
	union dphy_ana2_reg_t dphy_ana2;
	union dphy_ana3_reg_t dphy_ana3;
	union dphy_ana4_reg_t dphy_ana4;
	/* 0x60 - 0x6c */
	union dphy_int_en0_reg_t dphy_int_en0;
	union dphy_int_en1_reg_t dphy_int_en1;
	union dphy_int_en2_reg_t dphy_int_en2;
	union dphy_reservd_reg_t dphy_reg06c;
	/* 0x70 - 0x7c */
	union dphy_int_pd0_reg_t dphy_int_pd0;
	union dphy_int_pd1_reg_t dphy_int_pd1;
	union dphy_int_pd2_reg_t dphy_int_pd2;
	union dphy_reservd_reg_t dphy_reg07c;
	/* 0x80 - 0xdc */
	union dphy_reservd_reg_t dphy_reg080[24];
	/* 0xe0 - 0xec */
	union dphy_dbg0_reg_t dphy_dbg0;
	union dphy_dbg1_reg_t dphy_dbg1;
	union dphy_dbg2_reg_t dphy_dbg2;
	union dphy_dbg3_reg_t dphy_dbg3;
	/* 0xf0 - 0xfc */
	union dphy_dbg4_reg_t dphy_dbg4;
	union dphy_dbg5_reg_t dphy_dbg5;
	union dphy_tx_skew_reg0_t       dphy_tx_skew_reg0;  /*0xf8 */
	union dphy_tx_skew_reg1_t       dphy_tx_skew_reg1;  /*0xfc */
	union dphy_tx_skew_reg2_t       dphy_tx_skew_reg2;  /*0x100 */
	union dphy_pll_reg0_t           dphy_pll_reg0;      /*0x104 */
	union dphy_pll_reg1_t           dphy_pll_reg1;      /*0x108 */
	union dphy_pll_reg2_t           dphy_pll_reg2;      /*0x10c */
	union combo_phy_reg0_t          combo_phy_reg0;     /*0x110 */
	union combo_phy_reg1_t          combo_phy_reg1;     /*0x114 */
	union combo_phy_reg2_t          combo_phy_reg2;     /*0x118 */
};

union dsi_ph_t {
	struct {
		u32 byte012:24;
		u32 byte3:8;
	} bytes;
	struct {
		u32 bit00:1;
		u32 bit01:1;
		u32 bit02:1;
		u32 bit03:1;
		u32 bit04:1;
		u32 bit05:1;
		u32 bit06:1;
		u32 bit07:1;
		u32 bit08:1;
		u32 bit09:1;
		u32 bit10:1;
		u32 bit11:1;
		u32 bit12:1;
		u32 bit13:1;
		u32 bit14:1;
		u32 bit15:1;
		u32 bit16:1;
		u32 bit17:1;
		u32 bit18:1;
		u32 bit19:1;
		u32 bit20:1;
		u32 bit21:1;
		u32 bit22:1;
		u32 bit23:1;
		u32 bit24:1;
		u32 bit25:1;
		u32 bit26:1;
		u32 bit27:1;
		u32 bit28:1;
		u32 bit29:1;
		u32 bit30:1;
		u32 bit31:1;
	} bits;
};

来源：RT-Thread 官方仓库：https://github.com/RT-Thread/rt-thread/blob/master/bsp/allwinner/libraries/sunxi-hal/hal/source/disp2/disp/de/lowlevel_v2x/de_dsi_type.h

awwwwa

@towel_roll D1-H哪吒MIPI屏幕测试固件（TFT08006）.img 是使用 NAND 的，不能刷进NOR存储器里

awwwwa

请安装python3

awwwwa

环境没有安装

Ubuntu 22.04 / 20.04

更新软件源，更新系统软件包

sudo apt-get update
sudo apt-get upgrade -y

安装开发依赖

sudo apt-get install build-essential subversion git libncurses5-dev zlib1g-dev gawk flex bison quilt libssl-dev xsltproc libxml-parser-perl mercurial bzr ecj cvs unzip lsof

安装相关工具

sudo apt-get install kconfig-frontends android-tools-mkbootimg python2 libpython3-dev

增加架构支持

sudo dpkg --add-architecture i386
sudo apt-get update

安装支持包

sudo apt install gcc-multilib 
sudo apt install libc6:i386 libstdc++6:i386 lib32z1

Ubuntu 18.04

更新软件源，更新系统软件包

sudo apt-get update
sudo apt-get upgrade -y

安装开发依赖

sudo apt-get install build-essential subversion git libncurses5-dev zlib1g-dev gawk flex bison quilt libssl-dev xsltproc libxml-parser-perl mercurial bzr ecj cvs unzip lsof

安装相关工具

sudo apt-get install android-tools-mkbootimg libpython3-dev

增加架构支持

sudo dpkg --add-architecture i386
sudo apt-get update

安装支持包

sudo apt install gcc-multilib 
sudo apt install libc6:i386 libstdc++6:i386 lib32z1

Arch Linux / Manjaro

更新软件源，更新系统软件包

pacman -Syyuu

安装开发依赖

pacman -S --needed base-devel autoconf automake bash binutils bison bzip2 fakeroot file findutils flex gawk gcc gettext git grep groff gzip time unzip util-linux wget which zlib asciidoc help2man intltool perl-extutils-makemaker swig

安装相关工具

pacman -S --needed libelf libtool libxslt m4 make ncurses openssl patch pkgconf python rsync sed texinfo

增加架构支持

pacman -S --needed multilib-devel

CentOS / Fedora / openEuler

sudo dnf --setopt install_weak_deps=False --skip-broken install bash-completion bzip2 gcc gcc-c++ git make ncurses-devel patch rsync tar unzip wget which diffutils python2 python3 perl-base perl-Data-Dumper perl-File-Compare perl-File-Copy perl-FindBin perl-Thread-Queue glibc.i686

openSUSE

sudo zypper install --no-recommends asciidoc bash bc binutils bzip2 fastjar flex gawk gcc

awwwwa

R128-S2 驱动 1024x600 RGB 显示屏并运行 LVGL
https://bbs.aw-ol.com/topic/4316/share/1

awwwwa

@tsy2001 选中之后会勾选依赖，但是取消的时候不会取消依赖的勾选，得去对应配置取消

awwwwa

@xsyr1024 tina其实就是openwrt，在openwrt中的KERNEL_开头的选项就是会影响到内核配置

awwwwa

@xsyr1024 在kernel里关闭VIN驱动

awwwwa

@lansecd 在 T113开机LOGO闪烁问题中说：

@awwwwa 2.1的SDK可以分享一下么

新 SDK 平台下载 D1-H/D1s SDK
https://bbs.aw-ol.com/topic/3947/share/1

下载这个即可

awwwwa

正常情况 ref_fps≈fps

异常情况：ref_fps>>fps

需要检查屏幕时序配置是否正确

awwwwa

https://r128.docs.aw-ol.com/r128/prepare_dev_env/#windows_1

awwwwa

@dort91011 这个是UDISK分区，是烧录软件在烧录的时候自动划分的空间。如果需要手动配置，请在sys_partition.fex里手动配置这个分区的size

awwwwa

@polarcode 按住FEL按键重新烧录

awwwwa

RT内核没研究过，不过可以先试试普通内核能不能启动手动打入rt补丁看看

awwwwa

卡7%是不是烧录成nand固件了，nor固件文件名会写nor

awwwwa

@vctorspace 图1是DDR2接线，图2是DDR3接线

awwwwa

@xsyr1024 在请教如何排查 linux kernel 启动卡主的问题中说：

[ 0.969253] 000: printk: console [ttyS0] enabled
[ 0.973945] 000: printk: bootconsole [earlycon0] disabled

看着是earlycon0作为串口输出驱动正常，但是切换到ttyS0作为串口输出的时候ttyS0没有输出，先检查uart部分

另外这个是LinuxRT内核吗

awwwwa

@koupoo 2.1的SDK已经修复了，不需要这个补丁

awwwwa

在这里卡死说明Kernel没有跑起来，或者Kernel没有配置正确串口输出

awwwwa

@missdangerous 固件损坏，GUID 分区表损坏

awwwwa

uhttpd 需要加载luci，需要勾选luci的相关配置feed。具体可以参考openwrt官方文档

awwwwa

适配于 A133 Android 13 方案，Linux 5.15

ctp {
	gt9xx {
		compatible = "goodix,gt9xx";
		reg = <0x5d>;
		status = "okay";
		irq-gpios = <&pio PD 20 GPIO_ACTIVE_LOW>;
		irq-flags = <2>;
		reset-gpios = <&pio PD 21 GPIO_ACTIVE_LOW>;
		vdd_ana-supply = <&reg_cldo2>;

		touchscreen-max-id = <11>;
		touchscreen-size-x = <1280>;
		touchscreen-size-y = <800>;
		touchscreen-max-w = <512>;
		touchscreen-max-p = <512>;
		//touchscreen-key-map = <172>, <158>; /*KEY_HOMEPAGE=172, KEY_BACK=158，KEY_MENU=139*/
		goodix,slide-wakeup = <0>;
		goodix,type-a-report = <1>;
		goodix,driver-send-cfg = <0>;
		goodix,send-cfg-id = <0>;
		goodix,resume-in-workqueue = <0>;
		goodix,int-sync = <1>;
		goodix,revert_x = <0>;
		goodix,revert_y = <0>;
		goodix,swap-x2y = <0>;
		goodix,tp_idle_support = <1>;
		goodix,esd-protect = <1>;
		goodix,auto-update-cfg = <0>;
		goodix,power-off-sleep = <1>;
		goodix,pen-suppress-finger = <0>;
		/* GT9271_Config_20221222_v67.cfg*/
		goodix,cfg-group0 = [
			B4 00 05 20 03 0A 3D 00 01 0A
			28 0F 50 32 03 05 00 00 00 00
			00 00 06 17 19 1F 14 8E 2E 99
			2D 2F 35 11 00 00 00 1A 03 10
			00 00 00 00 00 00 00 00 00 00
			00 32 50 94 D5 02 07 00 00 04
			8E 48 00 8A 4D 00 86 53 00 83
			59 00 80 60 00 80 00 00 00 00
			00 00 00 00 00 00 00 00 00 00
			00 00 00 00 00 00 00 00 00 00
			00 00 00 00 00 00 00 00 00 00
			00 00 00 01 04 05 06 07 08 09
			0C 0D 0E 0F 10 11 14 15 16 17
			FF FF FF FF FF FF FF FF FF FF
			FF FF 28 27 26 25 24 23 22 21
			20 1F 1E 1C 1B 19 13 12 11 10
			0F 0D 0C 0A 08 07 06 04 02 00
			FF FF FF FF FF FF FF FF FF FF
			FF FF FF FF AB 01
		];
	};

awwwwa

SPI2 不是启动使用的SPI，可以挂副存储器但是不能作为启动存储器

awwwwa

@iincity NOR固件需要线刷

awwwwa

NOR固件不能烧卡

awwwwa

@email10000 这个是软件配置问题了，接收spi信息超时

awwwwa

Tina 4.0:
tina_v851se-tinyvision_uart0.zip

Tina 4.0 摄像头测试：
e8ce3a5d-7cbf-40a3-b16a-1989ce206407-tina_v851se-tinyvision_uart0.zip

Tina 5.0:
v851se_linux_tinyvision_uart0_SDNand.zip

Patch:
e4350d20-eda5-4ff5-b708-5901f5469aa9-tinyvision_patch.tar.gz

tinyvision_syterboot.zip

tinyvision_e907_boot.zip

71d8a58c-6fe2-4a93-96ee-b12bb883b2e1-摄像头测试固件.img

d0ef81d9-3893-4c2c-8903-711cf397a3bb-tinyvision.tgz

CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN8IW21=y
CONFIG_SUNXI_GPIO_V2=y
#CONFIG_AXP_GPIO=y
CONFIG_SYS_CONFIG_NAME="sun8iw21p1"
CONFIG_DEFAULT_DEVICE_TREE="sun8iw21p1-soc-system"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_CONSOLE_MUX=y
CONFIG_SUNXI_NECESSARY_REPLACE_FDT=y
CONFIG_RESERVE_FDT_SIZE=0x20000
CONFIG_PRE_CONSOLE_BUFFER=n
# CONFIG_OF_BOARD=y
CONFIG_OF_SEPARATE=y
CONFIG_SYS_TEXT_BASE=0x42000000
CONFIG_SUNXI_FDT_ADDR=0x41800000
CONFIG_SUNXI_MALLOC_LEN=0x1400000
# Environment
# CONFIG_ENV_IS_IN_SUNXI_FLASH=y
# CONFIG_SYS_MAXARGS=64
# CONFIG_SUNXI_REDUNDAND_ENVIRONMENT=y
# CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
# CONFIG_SUNXI_ENV_PARTITION="env"
CONFIG_SUNXI_ENV_BACKUP=y
# CONFIG_SUNXI_ENV_REDUNDAND_PARTITION="env-redund"
# CONFIG_ENV_SIZE=0x20000

#system
CONFIG_ARM_SMCCC=y
CONFIG_SUNXI_DMA=y
CONFIG_CLK_SUNXI=y
#SPI
CONFIG_SPI=y
CONFIG_SUNXI_SPI=y
CONFIG_SPI_USE_DMA=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_SST=y
CONFIG_SPI_FLASH_PUYA=y
CONFIG_SPI_FLASH_FM=y
CONFIG_SPI_FLASH_XT=y
CONFIG_SPI_FLASH_ADESTO=y
CONFIG_SPI_FLASH_XMC=y
CONFIG_SPI_SAMP_DL_EN=y

CONFIG_SF_DEFAULT_SPEED=50000000
# BIT(12) BIT(13) (SPI_RX_DUAL|SPI_RX_QUAD)
CONFIG_SF_DEFAULT_MODE=0x3000
CONFIG_SPINOR_UBOOT_OFFSET=128
CONFIG_SPINOR_LOGICAL_OFFSET=2016
CONFIG_SPINOR_UBOOT_SECURE_OFFSET=128
CONFIG_SPINOR_LOGICAL_SECURE_OFFSET=2200


#axp
CONFIG_SYS_I2C_SUNXI=y
CONFIG_I2C4_ENABLE=y
CONFIG_SYS_SUNXI_I2C4_SLAVE=0x34
CONFIG_SYS_SUNXI_I2C4_SPEED=400000
CONFIG_SUNXI_POWER=y
CONFIG_SUNXI_PMU=y
CONFIG_SUNXI_BMU=y
CONFIG_AXP2101_POWER=y
CONFIG_AXP2101_SUNXI_I2C_SLAVE=0x34


#key
#CONFIG_SUNXI_PHY_KEY=y
#CONFIG_SUNXI_LRADC_KEY=y


#crypto driver
CONFIG_SUNXI_CE_DRIVER=y
CONFIG_SUNXI_CE_23=y

#CONFIG_SF_DEFAULT_SPEED=50000000
# BIT(12) BIT(13) (SPI_RX_DUAL|SPI_RX_QUAD)
#CONFIG_SF_DEFAULT_MODE=0x3000

#
# PWM_SUNXI
#
CONFIG_PWM_SUNXI=y
# CONFIG_PWM_SUNXI_NEW is not set

#CONFIG_SPINOR_UBOOT_OFFSET=128
#CONFIG_SPINOR_LOGICAL_OFFSET=2016

# flash
CONFIG_SUNXI_SDMMC=y
CONFIG_MMC=y
CONFIG_SUNXI_FLASH=y
CONFIG_SUNXI_NAND=y
CONFIG_SUNXI_UBIFS=y
CONFIG_SUNXI_COMM_NAND_V1=y
CONFIG_SUNXI_SPINOR=y

#usb otg config
CONFIG_SUNXI_USB=y
CONFIG_SUNXI_EFEX=y
CONFIG_SUNXI_BURN=y
CONFIG_SUNXI_FASTBOOT=y
#partition
CONFIG_EFI_PARTITION=y

#image
CONFIG_ANDROID_BOOT_IMAGE=y

#sprite
CONFIG_SUNXI_SPRITE=y
CONFIG_SUNXI_SECURE_STORAGE=y
CONFIG_SUNXI_SPRITE_CARTOON=y

#secure feature
CONFIG_SUNXI_SECURE_BOOT=y
CONFIG_SUNXI_IMAGE_VERIFIER=y
CONFIG_SUNXI_KEYBOX=y
CONFIG_SUNXI_DRM_SUPPORT=y
CONFIG_SUNXI_EXTERN_SECURE_MM_LAYOUT=y


CONFIG_SUNXI_HOMLET=y
CONFIG_SUNXI_HDCP_HASH=y
CONFIG_SUNXI_HDCP_IN_SECURESTORAGE=y

#cmd
CONFIG_CMD_SUNXI_TIMER=y
CONFIG_CMD_SUNXI_SPRITE=y
CONFIG_CMD_SUNXI_EFEX=y
CONFIG_CMD_SUNXI_BURN=y
CONFIG_CMD_GPT=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FASTBOOT=y
CONFIG_CMD_SUNXI_DMA=y
CONFIG_CMD_SUNXI_CLK=y
CONFIG_CMD_SUNXI_MEMTEST=y
CONFIG_CMD_PART=y
CONFIG_CMD_SUNXI_AUTO_FEL=n
CONFIG_CMD_SUNXI_BOOTR=y
#arisc
#CONFIG_SUNXI_ARISC_EXIST=y

# CONFIG_SUNXI_INITRD_ROUTINE is not set
#dsp
#CONFIG_XTENSA_DSP=y
#riscv
#CONFIG_RISCV_E907=y

CONFIG_SUNXI_ARM_SOFT_FP=y
CONFIG_USE_PRIVATE_LIBGCC=y
#
# BOOT GUI
#
CONFIG_BOOT_GUI=y
# CONFIG_UPDATE_DISPLAY_MODE is not set
# CONFIG_CONFIG_LCD_CHECK_SKIP_OPEN is not set
# CONFIG_BOOT_GUI_DOUBLE_BUF is not set
# CONFIG_BOOT_GUI_TEST is not set

#
# SUNXI LOGO DISPLAY
#
CONFIG_CMD_SUNXI_BMP=y
# CONFIG_SUNXI_SPINOR_BMP is not set
# CONFIG_ENABLE_ADVERT_PICTURE is not set
# CONFIG_SUNXI_SPINOR_JPEG is not set
# CONFIG_CMD_SUNXI_JPEG is not set
CONFIG_DISP2_SUNXI=y
# CONFIG_HDMI_DISP2_SUNXI is not set
# CONFIG_HDMI2_DISP2_SUNXI is not set
# CONFIG_VDPO_DISP2_SUNXI is not set
# CONFIG_TV_DISP2_SUNXI is not set
# CONFIG_EDP_DISP2_SUNXI is not set
# CONFIG_EINK200_SUNXI is not set

#
# LCD panels select
#
# CONFIG_LCD_SUPPORT_GG1P4062UTSW is not set
# CONFIG_LCD_SUPPORT_DX0960BE40A1 is not set
# CONFIG_LCD_SUPPORT_TFT720X1280 is not set
# CONFIG_LCD_SUPPORT_FD055HD003S is not set
# CONFIG_LCD_SUPPORT_HE0801A068 is not set
# CONFIG_LCD_SUPPORT_ILI9341 is not set
# CONFIG_LCD_SUPPORT_LH219WQ1 is not set
# CONFIG_LCD_SUPPORT_LS029B3SX02 is not set
# CONFIG_LCD_SUPPORT_LT070ME05000 is not set
# CONFIG_LCD_SUPPORT_S6D7AA0X01 is not set
# CONFIG_LCD_SUPPORT_T27P06 is not set
# CONFIG_LCD_SUPPORT_TFT720x1280 is not set
# CONFIG_LCD_SUPPORT_WTQ05027D01 is not set
# CONFIG_LCD_SUPPORT_H245QBN02 is not set
# CONFIG_LCD_SUPPORT_ST7789V is not set
# CONFIG_LCD_SUPPORT_ST7796S is not set
# CONFIG_LCD_SUPPORT_ST7701S is not set
# CONFIG_LCD_SUPPORT_T30P106 is not set
# CONFIG_LCD_SUPPORT_TO20T20000 is not set
# CONFIG_LCD_SUPPORT_FRD450H40014 is not set
# CONFIG_LCD_SUPPORT_S2003T46G is not set
# CONFIG_LCD_SUPPORT_WILLIAMLCD is not set
# CONFIG_LCD_SUPPORT_LQ101R1SX03 is not set
# CONFIG_LCD_SUPPORT_INET_DSI_PANEL is not set
# CONFIG_LCD_SUPPORT_WTL096601G03 is not set
# CONFIG_LCD_SUPPORT_BP101WX1 is not set
# CONFIG_LCD_SUPPORT_M133X56 is not set
# CONFIG_LCD_SUPPORT_K101IM2QA04 is not set
# CONFIG_LCD_SUPPORT_K101IM2BYL02L is not set
# CONFIG_LCD_SUPPORT_FX070 is not set
# CONFIG_LCD_SUPPORT_M101B31 is not set
# CONFIG_LCD_SUPPORT_CC08021801_310_800X1280 is not set
# CONFIG_LCD_SUPPORT_KD101NA5 is not set
# CONFIG_LCD_SUPPORT_KD070D57 is not set
# CONFIG_LCD_SUPPORT_ZS080NI4003E7H3H_A is not set
# CONFIG_LCD_SUPPORT_K080_IM2HYL802R_800X1280 is not set
# CONFIG_LCD_SUPPORT_K101_IM2BYL02_L_800X1280 is not set
# CONFIG_LCD_SUPPORT_JD9366AB_3 is not set
# CONFIG_LCD_SUPPORT_TFT08006 is not set
CONFIG_LCD_SUPPORT_ST7701S_G5=y
CONFIG_LCD_SUPPORT_T050K589=y
CONFIG_LCD_SUPPORT_JD9161Z_MIPI=y
CONFIG_LCD_SUPPORT_ICN6202=y

#
# Display engine feature select
#
# CONFIG_DISP2_SUNXI_SUPPORT_SMBL is not set
# CONFIG_DISP2_SUNXI_SUPPORT_ENAHNCE is not set
# CONFIG_SUNXI_TV_FASTLOGO is not set
# CONFIG_SUNXI_FASTLOGO_JPEG is not set

awwwwa

@liangzhicheng 可以用glmark2测试

awwwwa

@xjy_5 一般2M摄像头都是1920*1088的，可能就按这个来处理了

awwwwa

进入 menuconfig 勾选 drm 驱动

./build.sh menuconfig

先勾选 DRM

再勾选 DRM 驱动

选择驱动的phy

选择屏幕

选择 general 屏幕面板驱动

关闭原来的 disp2 fbdev 驱动

配置设备树

	edp_panel_backlight: edp_backlight {
		compatible = "pwm-backlight";
		status = "okay";
		brightness-levels = <
			  0   1   2   3   4   5   6   7
			  8   9  10  11  12  13  14  15
			 16  17  18  19  20  21  22  23
			 24  25  26  27  28  29  30  31
			 32  33  34  35  36  37  38  39
			 40  41  42  43  44  45  46  47
			 48  49  50  51  52  53  54  55
			 56  57  58  59  60  61  62  63
			 64  65  66  67  68  69  70  71
			 72  73  74  75  76  77  78  79
			 80  81  82  83  84  85  86  87
			 88  89  90  91  92  93  94  95
			 96  97  98  99 100 101 102 103
			104 105 106 107 108 109 110 111
			112 113 114 115 116 117 118 119
			120 121 122 123 124 125 126 127
			128 129 130 131 132 133 134 135
			136 137 138 139 140 141 142 143
			144 145 146 147 148 149 150 151
			152 153 154 155 156 157 158 159
			160 161 162 163 164 165 166 167
			168 169 170 171 172 173 174 175
			176 177 178 179 180 181 182 183
			184 185 186 187 188 189 190 191
			192 193 194 195 196 197 198 199
			200 201 202 203 204 205 206 207
			208 209 210 211 212 213 214 215
			216 217 218 219 220 221 222 223
			224 225 226 227 228 229 230 231
			232 233 234 235 236 237 238 239
			240 241 242 243 244 245 246 247
			248 249 250 251 252 253 254 255>;
		default-brightness-level = <200>;
		enable-gpios = <&pio PI 5 GPIO_ACTIVE_HIGH>;
		/* power-supply = <&reg_backlight_12v>; */
		pwms = <&a_pwm 5 5000000 0>;
	};

	edp_panel: edp_panel {
		compatible = "edp-general-panel";
		status = "okay";
		power0-supply = <&reg_dcdc4>;

		backlight = <&edp_panel_backlight>;

		panel-timing {
			clock-frequency = <348577920>; /* pixel clock */
			hactive = <2560>;
			hback-porch = <120>;
			hfront-porch = <88>;
			hsync-len = <32>;
			vactive = <1600>;
			vback-porch = <71>;
			vfront-porch = <28>;
			vsync-len = <5>;
			/* hor_sync_polarity */
			hsync-active = <1>;
			/* ver_sync_polarity */
			vsync-active = <1>;

			// unused now
			/*
			de-active = <1>;
			pixelclk-active = <1>;
			syncclk-active = <0>;
			interlaced;
			doublescan;
			doubleclk;
			*/
		};
		ports {
			#address-cells = <1>;
			#size-cells = <0>;
			panel_in: port@0 {
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0>;
				edp_panel_in: endpoint@0 {
					reg = <0>;
					remote-endpoint = <&edp_panel_out>;
				};
			};
		};
	};

和 drm_edp 的配置

&drm_edp {
	status = "okay";

	edp_ssc_en = <0>;
	edp_ssc_mode = <0>;
	edp_psr_support = <0>;
	edp_colordepth = <8>; /* 6/8/10/12/16 */
	edp_color_fmt = <0>; /* 0:RGB  1: YUV444  2: YUV422 */

	lane1_sw = <0>;
	lane1_pre = <0>;
	lane2_sw = <0>;
	lane2_pre = <0>;
	lane3_sw = <0>;
	lane3_pre = <0>;
	efficient_training = <0>;

	sink_capacity_prefer = <1>;
	edid_timings_prefer = <1>;
	timings_fixed = <1>;

	vcc-edp-supply = <&reg_bldo3>;
	vdd-edp-supply = <&reg_dcdc2>;
	panel = <&edp_panel>;
	ports {
		edp_out: port@1 {
			edp_panel_out: endpoint@0 {
				reg = <0>;
				remote-endpoint = <&edp_panel_in>;
			};
		};
	};
};

awwwwa

@zm12138 在 T113-S3TF卡启动稳定中说：

[00.593]sunxi flash init ok

MMC已经正常启动了，内核没有输出可以先检查uart配置是否正确

awwwwa

@xjy_5 这个不太清楚了，没有调试过这款芯片。我这边是T507+TC358743实现的

awwwwa

https://www.aw-ol.com/downloads?cat=5

awwwwa

打入以下补丁即可

cd package
git apply *.patch

lvgl8-update-version-from-8.1.0-to-8.3.2.zip

awwwwa

@xjy_5 一般来说配置sensor0_isp_used = <0>; 就不会调用ISP，虽然会配置但是不会处理。需要再跟踪一下调用

awwwwa

@awwwwa

sensor0:sensor@0 {                                      
      device_type = "sensor0";                        
      sensor0_mname = "gc2053_mipi";      /* 必须要和驱动的 SENSOR_NAME 一致 */   
      sensor0_twi_cci_id = <1>;           /* 所使用的twi id号，本例中使用的是twi1，故填写为1 */               
      sensor0_twi_addr = <0x6e>;          /* sensor 设备ID地址，必须与驱动中的I2C_ADDR一致 */                           
      sensor0_mclk_id = <0>;              /* 所使用的mclk id号，本例中使用的是MCLK0，故填写为0 */                        
      sensor0_pos = "rear";                           
      sensor0_isp_used = <1>;             /* 所使用的sensor为raw sensor，需要过ISP处理，故填写为1 */                      
      sensor0_fmt = <1>;                  /* sensor输出的图像格式，YUV：0，RAW：1 */            
      sensor0_stby_mode = <0>;                        
      sensor0_vflip = <0>;                /* VIPP 图像垂直翻转 */                
      sensor0_hflip = <0>;                /* VIPP 图像水平翻转 */                  
      sensor0_iovdd-supply = <&reg_aldo2>;/* sensor iovdd 连接的 ldo，根据硬件原理图的连接来决定（在硬件原理图中搜索aldo，然后找到CSI-iovdd对应的										   是哪一个aldo即可） */
      sensor0_iovdd_vol = <1800000>;	  /* iovdd的电压 */
      sensor0_avdd-supply = <&reg_bldo2>; /* sensor avdd连接的 ldo，根据硬件原理图的连接来决定 */
      sensor0_avdd_vol = <2800000>;		  /* 同上 */
      sensor0_dvdd-supply = <&reg_dldo2>;  /* 同上 */
      sensor0_dvdd_vol = <1200000>;        /* 同上 */                
      sensor0_power_en = <>;          										
      sensor0_reset = <&pio PA 11 1 0 1 0>; /* GPIO 信息配置：pio 端口 组内序号 功能分配 内部电阻状态 驱动能力 输出电平状态,本例中使用的是PA11*/   
      sensor0_pwdn = <&pio PA 9 1 0 1 0>;   /* GPIO 信息配置：pio 端口 组内序号 功能分配 内部电阻状态 驱动能力 输出电平状态,本例中使用的是PA9*/   
      flash_handle = <&flash0>;                       
      act_handle = <&actuator0>;                      
      status  = "okay";                               
};

填写`Sensor`输出图像格式

sensor输出图像格式定义在sensor_format_struct结构体中，vin v4l2驱动框架通过获取sensor_format_struct结构体成员信息来获取当前sensor输出图像格式，sensor_formats结构体中需要填写的成员是.desc和 .mbus_code。

.desc是描述sensor输出的图像格式，本例中gc2053是RGB Raw sensor，故.desc成员填写为"Raw RGB Bayer" 。.mbus_code 为sensor图像数据输出顺序，sensor RAW图像是以Bayer格式传输的（每个像素只表示RGB其中一个分量），常见的Bayer格式为：RGGB、BGGR、GRBG、GBRG，这个可以询问一下sensor原厂或者翻阅sensor datasheet进行查找。.mbus_code 若填错, 会导致色彩偏紫红和出现网格状纹理。

本例中gc2053图像输出格式为RGGB，且当前的配置是10bit mipi接口，故.mbus_code填写为
MEDIA_BUS_FMT_SRGGB10_1X10，若当前调试的sensor配置是8bit输出，
则.mbus_code填写为MEDIA_BUS_FMT_SRGGB8_1X8，按照这种规则进行填写。

static struct sensor_format_struct sensor_formats[] = {
    {
        .desc      = "Raw RGB Bayer", 
        /* 填写 Sensor 初始化时默认的 Bayer 格式，目的是告知主控端ISP当前图像的 Bayer 格式，ISP需要以同样的格式来接收和处理图像数据 */
        .mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10,
        .regs      = sensor_fmt_raw,		
        .regs_size = ARRAY_SIZE(sensor_fmt_raw),		
        .bpp       = 1
    },
};

如果sensor输出图像格式是YUV的话，则需要根据sensor图像数据输出顺序选择YUYV/VYUY/UYVY/YVYU 其中一种，如下：

static struct sensor_format_struct sensor_formats[] = {
	{
		.desc = "YUYV 4:2:2",
		.mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
		.regs = sensor_fmt_raw,
		.regs_size = ARRAY_SIZE(sensor_fmt_raw),
		.bpp = 2,
	},
};

同时，sensor_get_fmt_mbus_core函数也要将当前sensor的图像输出格式赋值给函数参数*code，有些sensor在翻转后RGB顺序不会自动进行调整，需要主控端ISP需要按照当前sensor翻转后的图像格式更新RGB顺序，避免翻转后出现图像色彩异常的问题，如下，gc2053支持翻转后sensor内部自动调整RGB顺序，所以函数参数*code仍赋值为MEDIA_BUS_FMT_SRGGB10_1X10。

static int sensor_get_fmt_mbus_core(struct v4l2_subdev *sd, int *code)
{
	*code = MEDIA_BUS_FMT_SRGGB10_1X10; // gc2053 support change the rgb format by itself
}

static long sensor_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
{
    int ret = 0;
    struct sensor_info *info = to_state(sd);
	switch (cmd) { 
        case VIDIOC_VIN_GET_SENSOR_CODE:    /* vin v4l2框架层在sensor翻转接口被调用后，
        								    通过VIDIOC_VIN_GET_SENSOR_CODE获取当前sensor的RGB顺序 */
            sensor_get_fmt_mbus_core(sd, (int *)arg);  
            break;
        default:
            return -EINVAL;
	}
	return ret;
}

awwwwa

@xjy_5 驱动都不用ISP，ISP是上层用户程序定义的，可以用camerademo抓图测试绕过ISP

awwwwa

对照手册：

SPI2 地址 0x04027000，没问题
SPI2 中断号 49，配置时需要减掉SIG和PPI的数量32，也就是17

中断号配置错误，应该为17不是18

		spi2: spi@04027000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sun8i-spi";
			device_type = "spi2";
			reg = <0x0 0x04027000 0x0 0x1000>;
			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_pll_periph0300m>, <&clk_spi2>;
			status = "disabled";
		};

awwwwa

重新确认了一下，MIPI 接受的数据格式与MIPI无关，也就是MIPI也可以接收YUV这类数据。

是否是因为后端配置的问题。参考T507的TC358743驱动配置的是MEDIA_BUS_FMT_UYVY8_2X8

awwwwa

@xjy_5 RGB888_1X24 我感觉是直出RGB信号的吧

这个DTSI是在T507上配置的，可以参考一下

		vind0:vind@0 {
			compatible = "allwinner,sunxi-vin-media", "simple-bus";
			#address-cells = <2>;
			#size-cells = <2>;
			ranges;
			device_id = <0>;
			vind0_clk = <384000000>;
			reg = <0x0 0x06600800 0x0 0x200>,
				<0x0 0x06600000 0x0 0x800>;
			clocks = <&clk_csi_top>, <&clk_pll_csi>,
				 <&clk_csi_master0>, <&clk_hosc>, <&clk_pll_csi>,
				 <&clk_csi_master1>, <&clk_hosc>, <&clk_pll_csi>;
			pinctrl-names = "mclk0-default","mclk0-sleep","mclk1-default","mclk1-sleep";
			pinctrl-0 = <&csi_mclk0_pins_a>;
			pinctrl-1 = <&csi_mclk0_pins_b>;
			pinctrl-2 = <&csi_mclk1_pins_a>;
			pinctrl-3 = <&csi_mclk1_pins_b>;
			status = "okay";


			csi_cci0:cci@0 {
				compatible = "allwinner,sunxi-csi_cci";
				reg = <0x0 0x06614000 0x0 0x400>;
				interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
				pinctrl-names = "default","sleep";
				pinctrl-0 = <&csi_cci0_pins_a>;
				pinctrl-1 = <&csi_cci0_pins_b>;
				device_id = <0>;
				status = "okay";
			};
			csi_cci1:cci@1 {
				compatible = "allwinner,sunxi-csi_cci";
				reg = <0x0 0x06614400 0x0 0x400>;
				interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
				pinctrl-names = "default","sleep";
				pinctrl-0 = <&csi_cci1_pins_a>;
				pinctrl-1 = <&csi_cci1_pins_b>;
				device_id = <1>;
				status = "okay";
			};
			csi0:csi@0 {
				device_type = "csi0";
				compatible = "allwinner,sunxi-csi";
				reg = <0x0 0x06601000 0x0 0x1000>;
				interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
				device_id = <0>;
				iommus = <&mmu_aw 4 1>;
				status = "okay";
			};
			csi1:csi@1 {
				device_type = "csi1";
				compatible = "allwinner,sunxi-csi";
				reg = <0x0 0x06602000 0x0 0x1000>;
				interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
				pinctrl-names = "default","sleep";
				pinctrl-0 = <&csi1_pins_a>;
				pinctrl-1 = <&csi1_pins_b>;
				device_id = <1>;
				iommus = <&mmu_aw 4 1>;
				status = "okay";
			};
			mipi0:mipi@0 {
				compatible = "allwinner,sunxi-mipi";
				reg = <0x0 0x0660C000 0x0 0x1000>;
				interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
				device_id = <0>;
				status = "okay";
			};
			isp0:isp@0 {
				compatible = "allwinner,sunxi-isp";
				device_id = <0>;
				status = "okay";
			};
			isp1:isp@1 {
				compatible = "allwinner,sunxi-isp";
				device_id = <1>;
				status = "okay";
			};
			scaler0:scaler@0 {
				compatible = "allwinner,sunxi-scaler";
				device_id = <0>;
				iommus = <&mmu_aw 4 1>;
				status = "okay";
			};
			scaler1:scaler@1 {
				compatible = "allwinner,sunxi-scaler";
				device_id = <1>;
				iommus = <&mmu_aw 4 1>;
				status = "okay";
			};
			scaler2:scaler@2 {
				compatible = "allwinner,sunxi-scaler";
				device_id = <2>;
				iommus = <&mmu_aw 4 1>;
				status = "okay";
			};
			scaler3:scaler@3 {
				compatible = "allwinner,sunxi-scaler";
				device_id = <3>;
				iommus = <&mmu_aw 4 1>;
				status = "okay";
			};
			scaler4:scaler@4 {
				compatible = "allwinner,sunxi-scaler";
				device_id = <4>;
				iommus = <&mmu_aw 4 1>;
				status = "okay";
			};
			scaler5:scaler@5 {
				compatible = "allwinner,sunxi-scaler";
				device_id = <5>;
				iommus = <&mmu_aw 4 1>;
				status = "okay";
			};
			actuator0:actuator@0 {
				device_type = "actuator0";
				compatible = "allwinner,sunxi-actuator";
				actuator0_name = "ad5820_act";
				actuator0_slave = <0x18>;
				actuator0_af_pwdn = <>;
				actuator0_afvdd = "afvcc-csi";
				actuator0_afvdd_vol = <2800000>;
				status = "disabled";
			};
			flash0:flash@0 {
				device_type = "flash0";
				compatible = "allwinner,sunxi-flash";
				flash0_type = <2>;
				flash0_en = <>;
				flash0_mode = <>;
				flash0_flvdd = "";
				flash0_flvdd_vol = <>;
				device_id = <0>;
				status = "disabled";
			};
			sensor0:sensor@0 {
				device_type = "sensor0";
				compatible = "allwinner,sunxi-sensor";
				sensor0_mname = "tc358743_mipi";
				sensor0_twi_cci_id = <2>;
				sensor0_twi_addr = <0x1f>;
				sensor0_mclk_id = <0>;
				sensor0_pos = "rear";
				sensor0_isp_used = <0>;
				sensor0_fmt = <0>;
				sensor0_stby_mode = <0>;
				sensor0_vflip = <0>;
				sensor0_hflip = <0>;
				sensor0_cameravdd-supply = <>;
				sensor0_cameravdd_vol = <2800000>;
				sensor0_iovdd-supply = <&reg_cldo4>;
				sensor0_iovdd_vol = <1800000>;
				sensor0_avdd-supply = <>;
				sensor0_avdd_vol = <>;
				sensor0_dvdd-supply = <>;
				sensor0_dvdd_vol = <>;
				sensor0_power_en = <>;
				sensor0_reset = <&pio PI 8 1 0 1 0>;
				sensor0_pwdn = <>;
				sensor0_sm_vs = <>;
				flash_handle = <&flash0>;
				act_handle = <&actuator0>;
				device_id = <0>;
				status	= "okay";
			};
			sensor1:sensor@1 {
				device_type = "sensor1";
				compatible = "allwinner,sunxi-sensor";
				sensor1_mname = "ov5647";
				sensor1_twi_cci_id = <1>;
				sensor1_twi_addr = <0x6c>;
				sensor1_mclk_id = <1>;
				sensor1_pos = "front";
				sensor1_isp_used = <0>;
				sensor1_fmt = <0>;
				sensor1_stby_mode = <0>;
				sensor1_vflip = <0>;
				sensor1_hflip = <0>;
				sensor1_cameravdd-supply = <>;
				sensor1_cameravdd_vol = <2800000>;
				sensor1_iovdd-supply = <>;
				sensor1_iovdd_vol = <2800000>;
				sensor1_avdd-supply = <>;
				sensor1_avdd_vol = <2800000>;
				sensor1_dvdd-supply = <>;
				sensor1_dvdd_vol = <1500000>;
				sensor1_power_en = <>;
				sensor1_reset = <&pio PE 14 1 0 1 0>;
				sensor1_pwdn = <&pio PE 15 1 0 1 0>;
				sensor1_sm_vs = <>;
				flash_handle = <>;
				act_handle = <>;
				device_id = <1>;
				status	= "disable";
			};
			vinc0:vinc@0 {
				device_type = "vinc0";
				compatible = "allwinner,sunxi-vin-core";
				reg = <0x0 0x06609000 0x0 0x200>;
				interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
				vinc0_csi_sel = <0>;
				vinc0_mipi_sel = <0>;
				vinc0_isp_sel = <0>;
				vinc0_isp_tx_ch = <0>;
				vinc0_rear_sensor_sel = <0>;
				vinc0_front_sensor_sel = <0>;
				vinc0_sensor_list = <0>;
				device_id = <0>;
				iommus = <&mmu_aw 4 1>;
				status = "okay";
			};
			vinc1:vinc@1 {
				device_type = "vinc1";
				compatible = "allwinner,sunxi-vin-core";
				reg = <0x0 0x06609200 0x0 0x200>;
				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
				vinc1_csi_sel = <0>;
				vinc1_mipi_sel = <0>;
				vinc1_isp_sel = <0>;
				vinc1_isp_tx_ch = <0>;
				vinc1_rear_sensor_sel = <0>;
				vinc1_front_sensor_sel = <0>;
				vinc1_sensor_list = <0>;
				device_id = <1>;
				iommus = <&mmu_aw 4 1>;
				status = "okay";
			};
			vinc2:vinc@2 {
				device_type = "vinc2";
				compatible = "allwinner,sunxi-vin-core";
				reg = <0x0 0x06609400 0x0 0x200>;
				interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
				vinc2_csi_sel = <0>;
				vinc2_mipi_sel = <0>;
				vinc2_isp_sel = <0>;
				vinc2_isp_tx_ch = <0>;
				vinc2_rear_sensor_sel = <0>;
				vinc2_front_sensor_sel = <0>;
				vinc2_sensor_list = <0>;
				device_id = <2>;
				iommus = <&mmu_aw 4 1>;
				status = "disabled";
			};
			vinc3:vinc@3 {
				device_type = "vinc3";
				compatible = "allwinner,sunxi-vin-core";
				reg = <0x0 0x06609600 0x0 0x200>;
				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
				vinc3_csi_sel = <0>;
				vinc3_mipi_sel = <0>;
				vinc3_isp_sel = <0>;
				vinc3_isp_tx_ch = <0>;
				vinc3_rear_sensor_sel = <0>;
				vinc3_front_sensor_sel = <0>;
				vinc3_sensor_list = <0>;
				device_id = <3>;
				iommus = <&mmu_aw 4 1>;
				status = "disabled";
			};
			vinc4:vinc@4 {
				device_type = "vinc4";
				compatible = "allwinner,sunxi-vin-core";
				reg = <0x0 0x06609800 0x0 0x200>;
				interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
				vinc4_csi_sel = <1>;
				vinc4_mipi_sel = <0xff>;
				vinc4_isp_sel = <1>;
				vinc4_isp_tx_ch = <0>;
				vinc4_rear_sensor_sel = <1>;
				vinc4_front_sensor_sel = <1>;
				vinc4_sensor_list = <0>;
				device_id = <4>;
				iommus = <&mmu_aw 5 1>;
				status = "disabled";
			};
			vinc5:vinc@5 {
				device_type = "vinc5";
				compatible = "allwinner,sunxi-vin-core";
				reg = <0x0 0x06609A00 0x0 0x200>;
				interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
				vinc5_csi_sel = <1>;
				vinc5_mipi_sel = <0xff>;
				vinc5_isp_sel = <1>;
				vinc5_isp_tx_ch = <0>;
				vinc5_rear_sensor_sel = <1>;
				vinc5_front_sensor_sel = <1>;
				vinc5_sensor_list = <0>;
				device_id = <5>;
				iommus = <&mmu_aw 5 1>;
				status = "disabled";
			};
		};

awwwwa

【资料汇总】V853资料汇总
https://bbs.aw-ol.com/topic/1560/share/1

awwwwa

在线文档：https://v853.docs.aw-ol.com/

awwwwa

@xjy_5 MIPI CSI接收的是RAW数据，不支持YUV这样的

awwwwa

kernel有修改，或者kernel配置文件错误

awwwwa

@hy123456 移动位置后需要删除out文件夹，因为SDK生成的设备的认证信息变化了但是由于SDK移动没有重新生成新的认证

awwwwa

AW平台的DRAM控制器支持地址线REMAP，可以通过REMAP简化外部不同种类的DRAM的连接。

这个REAMP是固定在芯片里的不能自己修改，在电路原理图可以看到REMAP的引脚。

如图，如果需要挂DDR3内存，需要接DDR3的REAMP，如果需要接DDR2，可以接默认的REMAP

举个其他平台的例子：
这里接的是 LPDDR4，使用LPDDR4的REMAP

这里接的是DDR4，使用DDR4的REMAP

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@abc16883
下载工具：
AllwinnertechPhoeniSuitRelease20230905.zip

下载驱动：
全志USB烧录驱动20201229

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测试固件
rtos_freertos_r128s2_evt_uart0_16Mnor.img

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jlt35031c.h
jlt35031c.c

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@yxfzz mmc引导到了mmcblk0boot0，rootfs挂载不上

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@lynnl4

Out of memory 没有内存了，camerademo走的拍摄路径是v4l2不是mpp的vipp路径，需要的内存较大，可以尝试拍摄小分辨率的图片测试

@lynnl4 在摄像头无法获取图像中说：

[CAMERA] Resolution size : 1920 * 1088

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出现重复定义，请问是不是同时勾选了 lv_examples 和 lv_g2d_test
分区表配置的空间过小，FAQ有解决方法：https://r128.docs.aw-ol.com/others/faq/

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请按照文档操作：

https://r128.docs.aw-ol.com/r128/prepare_dev_env/

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@huerli 在 T113输出日志，是不是片子坏了啊中说：

BUG: Bad page map in process S10mdev pte:40cdf59f pmd:41bb1835

主线驱动缺陷导致mdev申请出现NULL pointer。可以尝试使用新内核

awwwwa

烧写安全固件和rotpk.bin之后就再也无法烧录非安全固件了，似乎是KeystoreService未能正常启动

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@xjy_5 检查下twi的配置

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SanDisk HIGH ENDURABCE 32G SDHC Pass

SanDisk Ultra 128G SDXC Pass

aa836015-5015-433a-8fcf-b110d8aad425-lQDPJxwUfonqhSzNC9DND8Cw3YpYNr7PIvMFGf2NzIsWAA_4032_3024.jpg

NOKIA 2.0G Fail

e9978cf7-11d3-4d72-b080-4b485a4f1fee-lQDPJw0WbTybFQzNC9DND8Cw_sjdrS3On-0FGf3S3bqCAA_4032_3024.jpg

Unknow SD 120M SDHC Pass

99d79225-90fc-4963-a4e8-c53836447681-lQDPJwkbyvUvqgzNC9DND8CwTxXeh2GBmKoFGf4htgwzAA_4032_3024.jpg

Kingston 4G SDHC Pass

25db9121-3b65-4523-baca-fb299910d539-lQDPJx5swtaqoEzNC9DND8Cwbnudxv-Wiy8FGf5w0ZbSAA_4032_3024.jpg

Micro SD 512M SDHC Pass

4ed933d1-0c6d-4ad3-ab43-f85ffbf93c81-lQDPJwp-fvN_I4zNC9DND8CwRPg_yovkkykFGf7TGPjhAA_4032_3024.jpg

ADATA Micro SD 2G SDHC Pass

0dcd4a3d-9815-4922-8698-68bdb6f881f9-lQDPJxXl-VCwb0zNC9DND8CweJX-mL5KIgQFGf8rVdIHAA_4032_3024.jpg

Kioxia exceria 32G SDHC Pass

13dc558f-b4f1-4fb6-8d6a-e937d83edca9-lQDPJyDgT8wOfwzNC9DND8CwlWZLh8H4PJUFGf-NqUscAA_4032_3024.jpg

SanDisk Ultra 16GB SDHC Pass

d5eafdb8-71d4-4d62-863a-c49cb41498c2-lQDPJwGl2naexszNC9DND8CwHiiibxpT2ssFGgCz44-bAA_4032_3024.jpg

awwwwa

@biubiu 闪迪128G SDXC 和无标山寨卡 SDHC 都测试通过

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@biubiu 试试换一张卡看看，可能是不支持这个卡的型号

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[sdc0]
card_ctrl       = 0
card_high_speed = 0
card_line       = 4
sdc_d1          = port:PA27<2><1><3><default>
sdc_d0          = port:PA26<2><1><3><default>
sdc_clk         = port:PA29<2><1><3><default>
sdc_cmd         = port:PA25<2><1><3><default>
sdc_d3          = port:PA24<2><1><3><default>
sdc_d2          = port:PA28<2><1><3><default>

[sdc0det_para]
sdc0_det        = port:PA23<0><1><3><1>

适配 EVT 的测试镜像：
be810818-4bc0-447f-8705-d5d70abd8813-rtos_freertos_r128s2_evt_uart0_16Mnor.img

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@zhoudaxia3000 目前最新的是1.2.2

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@abcdef menuconfig勾选驱动编译了吗

awwwwa

jlt35031c是比较少见的小端屏，但是大部分的SPI屏都是大端屏，所以用jlt35031c时，需要修改sys_config.fex里面的配置项lcd_rgb_order为9.

unsigned char color[4] = {0xff,0x0,0xff,0x0};

这个数组决定颜色，颜色顺序是R（红） G（绿） B（蓝） A（亮度）。

所以红色 + 蓝色，应该是紫色

但是这里由于使用的是SPI接口驱动这个屏幕，并不支持lcd_rgb_order的参数配置。所以在屏幕初始化的时候通过写寄存器配置为对应的接口以支持LVGL的正确显示输出。但是测试命令可能会出现反色的情况。

awwwwa

固件适配板子吗？1.2V电压是DDR4的电压是不是烧录到LPDDR4的板子上了

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屏参改一下

lcd_driver_name     = "default_lcd"
lcd_backlight       = 150
lcd_if              = 0
lcd_x               = 1024
lcd_y               = 600
lcd_width           = 150
lcd_height          = 94
lcd_rb_swap         = 0
lcd_dclk_freq       = 48
lcd_pwm_used        = 1
lcd_pwm_ch          = 7
lcd_pwm_freq        = 500000
lcd_pwm_pol         = 1
lcd_hbp             = 160
lcd_ht              = 1344
lcd_hspw            = 20
lcd_vbp             = 20
lcd_vt              = 635
lcd_vspw            = 3
lcd_lvds_if         = 0
lcd_lvds_colordepth = 1
lcd_lvds_mode       = 0
lcd_frm             = 0
lcd_io_phase        = 0x0000
lcd_gamma_en        = 0
lcd_bright_curve_en = 0
lcd_cmap_en         = 0

awwwwa

@masterlu 64G内存，本地磁盘500G

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@masterlu
测试复现过程：
出现错误

6fe9beb8-bfec-4049-a140-c2a7570554b0-lQLPJwPZvYRS0EzM9c0GRrC4cenRP12kzwUGwWzH_DgA_1606_245.png

重开终端清除编译环境和之前编译输出后重新编译正常

awwwwa

感觉是环境配置有问题
试试：

重开一个终端
重新 source build/envsetup.sh
重新 ./longan/build.sh config
./longan/build.sh distclean
make installclean
lunch

awwwwa

@huangyuhan 没有配置默认保存用户名密码，需要多次输入

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@zhouyuan369 删除文件夹内的.repo隐藏文件夹重新拉取

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@sunxi source后 mkmpp，你的环境变量没有导入，不能直接make mk文件

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@zhouyuan369 网盘要怎么接收后续更新呢，重新下载25G的压缩包吗？

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可以看《Linux_Display_开发指南.pdf》不过这个也没有设备树的配置描述，更多是源码描述

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由于屏幕较大首先精简系统内存，关闭DSP核心，并将 RV 核心移到 HSPSRAM 上提高带宽。配置 LV_COLOR_DEPTH 16 提高帧率降低内存占用

patch 如下，增加了新方案r128-devkit-rgb：161ca91b-f759-4108-8bfc-85114394da0c-r128-devkit-rgb.tar.gz

编译打包即可

700ms启动 LVGL：

awwwwa

@casdfxx 这个代码是u-boot提供的，具体问题可以访问 https://lists.denx.de/listinfo/u-boot 寻求帮助。

裸机工程：https://github.com/xboot/xboot/tree/master/src/arch/arm32/mach-v3s

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