看一下 device/config/chips/d1-h/configs/nezha/sys_config.fex 的内容
A
awwwwa 发布的帖子
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回复: D1-H烧录固件后无法进入tina linux发布在 MR Series
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回复: v853 vin通路配置发布在 V Series
（1）在线模式：四个vipp和dma实体，最大缩小比例为16*16，每路最多可支持16个orl
（2）离线模式：每个vipp和dma可分时复用为4个vipp和dma虚拟体，四个vipp和dma实体相互独立，在线模式和离线模式开关也是相互独立的；
（3）VIPP和DAM的分时复用（离线模式）与isp和tdm的分时复用（离线模式）是绑定关系，即tdm和isp开启了离线模式，vipp和dma的输入端如果是isp，那么vipp和dma也需要开启离线模式；
（4）只有VIPP0和dma0实体支持VE在线编码，而vipp0在线，如果vipp00的输入端为isp，那么tdm和isp也只能配置在线模式，而isp在线，那么四个vipp和dma实体都只能配置在线模式；online 和 offline 配 置 方 式 在 board.dts ， 所 以 需 要 在 对 应 版 型 的 board.dts 中 找 到 vind0 节 点 配 置 列 表 ， 对 应 关 系 为 tdm 对 应 节 点 ， isp 对 应 isp00 节 点 ， vipp 对 应 scaler00 、 scaler10 、 scaler20 和 scaler30 节 点 ， dma 对 ， 应 vinc00 、 vinc10 、 vinc20 和 vinc30 节 点 。
- 在线模式，单路3输出
- 离线模式，2路8输出
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回复: T113 nand flash 启动失败发布在 MR Series
@cwj1986521 内核没有配置UBIFS
CONFIG_UBIFS_FS=y CONFIG_UBIFS_FS_ADVANCED_COMPR=y # CONFIG_UBIFS_FS_LZO is not set # CONFIG_UBIFS_FS_ZLIB is not set # CONFIG_UBIFS_FS_ZSTD is not set # CONFIG_UBIFS_ATIME_SUPPORT is not set CONFIG_UBIFS_FS_XATTR=y CONFIG_UBIFS_FS_SECURITY=y -
回复: 全志D1如何获取芯片运行的频率呢？发布在 MR Series
cd /sys/kernel/debug/ cat clk/clk_summary | grep pll-cpux
切换到 /sys/kernel/debug/ 目录，并尝试使用 cat 命令读取 clk/clk_summary 文件的内容，并通过 grep 过滤显示包含 "pll-cpux" 的行，便是CPU的运行时钟。
如果运行命令时没有出现错误，并且输出了包含 "pll-cpux" 的行，则说明成功执行了命令并找到了匹配的行。
如果命令未能正常执行，请确保目录和文件存在，以及你是否拥有适当的权限。另外，也请确保你的系统支持 debugfs 文件系统，并且已经正确挂载。
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回复: 测试编译不过发布在 V Series
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helloworld_fel 使用了 VFP 寄存器参数，但是某个库文件(libgcc.a(_udivmoddi4.o))却不支持。
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缺少 .note.GNU-stack 段，暗示可执行栈缺失。
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对于具有 RWX 权限的 LOAD 段，给出了警告。
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在链接时，出现了对 raise 函数的未定义引用。
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回复: T113-S3 Tina_linux编译后启动失败发布在 MR Series
@cwj1986521
启用MTD子系统：UBIFS是建立在MTD（Memory Technology Devices）子系统之上的，因此首先需要启用MTD子系统。在内核配置中，你可以找到 CONFIG_MTD 配置项并将其启用。启用UBI：UBIFS需要使用UBI（Unsorted Block Images）层来管理闪存设备，因此你需要启用UBI支持。在内核配置中，查找 CONFIG_UBI 配置项并将其启用。
启用UBIFS文件系统支持：在内核配置中，查找 CONFIG_UBIFS_FS 配置项并将其启用。这将启用UBIFS文件系统的核心支持。
配置MTD设备：UBIFS需要与特定的MTD设备进行交互。你需要在内核配置中启用相应的MTD设备驱动，以及指定UBI和UBIFS所需的MTD设备参数。这些配置选项可能因硬件平台和具体的MTD设备而有所不同。
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回复: T113-S3 Tina_linux编译后启动失败发布在 MR Series
ubi设备没有挂载，挂载为裸mtd设备
正常挂载会出现大量UBI开头的log
[ 1.952826] sunxi-mmc 4021000.sdmmc: smc 0 p1 err, cmd 5, RTO !! [ 1.960398] sunxi-mmc 4021000.sdmmc: smc 0 p1 err, cmd 5, RTO !! [ 1.967886] sunxi-codec-machine 2030340.sound: 2030000.codec <-> 203034c.dummy_cpudai mapping ok [ 1.977685] sunxi-mmc 4021000.sdmmc: smc 0 p1 err, cmd 5, RTO !! [ 1.984522] sunxi-mmc 4021000.sdmmc: sdc set ios:clk 0Hz bm PP pm OFF vdd 0 width 1 timing LEGACY(SDR12) dt B [ 1.997425] input: audiocodec sunxi Audio Jack as /devices/platform/soc@3000000/2030340.sound/sound/card0/input0 [ 2.010714] [SNDCODEC][sunxi_card_dev_probe][836]:register card finished [ 2.020708] NET: Registered protocol family 10 [ 2.027327] Segment Routing with IPv6 [ 2.031537] [SNDCODEC][sunxi_hs_init_work][259]:resume-->report switch [ 2.039133] NET: Registered protocol family 17 [ 2.044411] Bluetooth: RFCOMM TTY layer initialized [ 2.049865] Bluetooth: RFCOMM socket layer initialized [ 2.055819] Bluetooth: RFCOMM ver 1.11 [ 2.096457] ubi0: attaching mtd3 [ 2.473414] ubi0: scanning is finished [ 2.490836] ubi0: attached mtd3 (name "sys", size 123 MiB) [ 2.497186] ubi0: PEB size: 262144 bytes (256 KiB), LEB size: 258048 bytes [ 2.504905] ubi0: min./max. I/O unit sizes: 4096/4096, sub-page size 2048 [ 2.512552] ubi0: VID header offset: 2048 (aligned 2048), data offset: 4096 [ 2.520340] ubi0: good PEBs: 492, bad PEBs: 0, corrupted PEBs: 0 [ 2.527055] ubi0: user volume: 9, internal volumes: 1, max. volumes count: 128 [ 2.535131] ubi0: max/mean erase counter: 2/1, WL threshold: 4096, image sequence number: 0 [ 2.544501] ubi0: available PEBs: 10, total reserved PEBs: 482, PEBs reserved for bad PEB handling: 10 [ 2.555351] ubi0: background thread "ubi_bgt0d" started, PID 64 [ 2.564391] block ubiblock0_5: created from ubi0:5(rootfs) [ 2.571959] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2 [ 2.581694] clk: Not disabling unused clocks [ 2.586458] ALSA device list: [ 2.589758] #0: audiocodec [ 2.593045] cfg80211: failed to load regulatory.db [ 2.598481] alloc_fd: slot 0 not NULL! [ 2.606842] VFS: Mounted root (squashfs filesystem) readonly on device 254:0. [ 2.618509] devtmpfs: mounted [ 2.622621] Freeing unused kernel memory: 176K [ 2.627755] This architecture does not have kernel memory protection. [ 2.635026] Run /pseudo_init as init process mount: mounting none on /dev failed: Device or resource busy [ 3.197350] UBIFS (ubi0:7): Mounting in unauthenticated mode [ 3.204248] UBIFS (ubi0:7): background thread "ubifs_bgt0_7" started, PID 90 [ 3.306905] UBIFS (ubi0:7): recovery needed [ 3.437736] random: crng init done [ 3.484394] UBIFS (ubi0:7): recovery completed [ 3.489563] UBIFS (ubi0:7): UBIFS: mounted UBI device 0, volume 7, name "rootfs_data" [ 3.498354] UBIFS (ubi0:7): LEB size: 258048 bytes (252 KiB), min./max. I/O unit sizes: 4096 bytes/4096 bytes [ 3.509494] UBIFS (ubi0:7): FS size: 3096576 bytes (2 MiB, 12 LEBs), journal size 1806337 bytes (1 MiB, 5 LEBs) [ 3.520808] UBIFS (ubi0:7): reserved for root: 146258 bytes (142 KiB) [ 3.528009] UBIFS (ubi0:7): media format: w5/r0 (latest is w5/r0), UUID F3C42DF5-C431-46B6-9FB0-44D877A77B61, small LPT model can't run '/etc/preinit': No such file or directory mount: mounting devpts on /dev/pts failed: No such device [ 3.914941] UBIFS (ubi0:8): Mounting in unauthenticated mode [ 3.923295] UBIFS (ubi0:8): background thread "ubifs_bgt0_8" started, PID 118 [ 4.074613] UBIFS (ubi0:8): recovery needed [ 4.176774] UBIFS (ubi0:8): recovery completed [ 4.190587] UBIFS (ubi0:8): UBIFS: mounted UBI device 0, volume 8, name "UDISK" [ 4.198772] UBIFS (ubi0:8): LEB size: 258048 bytes (252 KiB), min./max. I/O unit sizes: 4096 bytes/4096 bytes [ 4.211023] UBIFS (ubi0:8): FS size: 47738880 bytes (45 MiB, 185 LEBs), journal size 2322432 bytes (2 MiB, 9 LEBs) [ 4.223836] UBIFS (ubi0:8): reserved for root: 2254825 bytes (2201 KiB) [ 4.231568] UBIFS (ubi0:8): media format: w5/r0 (latest is w5/r0), UUID 36942453-7E73-45BA-9E89-913155DABE62, small LPT model -
回复: V853 SDK : PMU TWI发布在 V Series
@alb702 在 V853 SDK : PMU TWI 中说：
[267]ic cant match axp, please check...
V853 和 V853s 的芯片安全系统验证不一样，SDK不能通用，这行输出表示芯片型号验证失败，跳过初始化DRAM
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回复: R128 打包失败 merge_full_rtos_img_failed发布在 MR Series
@cai_yp 分区参数错误，只打包了UDISK分区，但是UDISK是自动生成的分区
32356+0 records in 32356+0 records out 8283136 bytes (8.3 MB) copied, 0.0394041 s, 210 MB/s this is not a partition key update mbr file ok ----------------mbr convert to gpt start--------------------- out: sunxi_gpt_nor.fex source: sunxi_mbr_nor.fex input_logic_offset: 256 input_flash_size: 16M gpt partition entry crc32 = 0x618ebc8 gpt header crc32 = 0x4fdf09e2 GPT----part num 10--- gpt_entry: 128 gpt_header: 92 GPT:env : 120 127 GPT:env-redund : 128 12f GPT:arm-lpsram : 130 a8f GPT:rv-lpsram : a90 1a2f GPT:dsp-hpsram : 1a30 206f GPT:rtos-xip : 2070 33f7 GPT:arm-b : 33f8 3d57 GPT:config : 3d58 3d77 GPT:settings : 3d78 3db7 GPT:UDISK : 3db8 7fff update gpt file ok ----------------mbr convert to gpt end--------------------- boot0: boot0_spinor.fex redund boot0: boot0_spinor.fex mbr: sunxi_gpt_nor.fex partition: sys_partition_nor.bin UDISK_partition_size: 16968 sector outfile: rtos_16Mnor.bin logic_start: 128K total_image_size: 16M load file: boot0_spinor.fex ok load file: sunxi_gpt_nor.fex ok load file: boot0_spinor.fex ok support redund boot0 at 0x10000 load file: sys_partition_nor.bin ok part name=env file name:env.fex part size:8 sector load file: env.fex ok part name=env-redund file name:env.fex part size:8 sector load file: env.fex ok part name=arm-lpsram file name:rtos_arm.fex part size:2400 sector load file: rtos_arm.fex ok part name=rv-lpsram file name:rtos_riscv.fex part size:4000 sector load file: rtos_riscv.fex ok part name=dsp-hpsram file name:rtos_dsp.fex part size:1600 sector load file: rtos_dsp.fex ok part name=rtos-xip file name:rtos_xip_rv.fex part size:5000 sector load file: rtos_xip_rv.fex ok part name=arm-b file name:etf.fex part size:2400 sector load file: etf.fex ok part name=config file name:config.fex part size:32 sector load file: config.fex ok part name=settings part size:64 sector part name=UDISK file name:data_udisk.fex load file: data_udisk.fex ok partname: UDISK this is not a partition key merge_package ok -
回复: t113使用sd卡启动卡住了发布在 Linux
@xingxing8 在 t113使用sd卡启动卡住了 中说：
先看这行
VFS: Cannot open root device "mmcblk0p5" or unknown-block(0,0): error -6
这行表示没有挂载上mmc设备
再往上找
[ 4.002919] sunxi-mmc 4020000.sdmmc: Got CD GPIO
[ 4.008458] sunxi-mmc 4020000.sdmmc: set cd-gpios as 24M fail
[ 4.018859] sunxi-mmc 4020000.sdmmc: sdc set ios:clk 0Hz bm PP pm UP vdd 21 width 1 timing LEGACY(SDR12) dt BCD卡检测GPIO检测不到卡，关闭MMC驱动
Linux中的驱动为了省电会根据CD引脚检测卡是否存在，不存在则关闭MMC驱动，U-boot驱动没有这个逻辑
解决方法：
- 正向解决法
- 根据实物硬件查看CD引脚配置，上下拉状态是否正常，是否反转CD
- 软件规避法
- 直接关闭CD检测功能，取消注释
broken-cd;
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回复: V853 SDK : PMU TWI发布在 V Series
@alb702 在device\config\chips\v853\configs\vision\sys_config.fex 中，out目录是从这里拷贝过去的
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回复: V851S tina linux ov5647 驱动程序没有 dmesg发布在 V Series
ov5647 这个型号的摄像头并没有适配，SDK也没有支持。
请参考V85x的摄像头支持手册选择适配的摄像头。这里推荐已经量产的产品使用的GC2063，GC2083，GC4663这三款摄像头，已经经过严格的测试与调试，可以达到最佳画质和分辨率
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回复: 提高香橙派GPIO最高速率发布在 H/F/TV Series
SoC一般不推荐GPIO翻转，如果需要提高需要提高APB的时钟，但是修改APB的时钟会对ＡＰＢ上的全部设备造成影响，例如ＵＡＲＴ，ＴＷＩ，ＰＷＭ，Ｔｉｍｅｒ全部需要重新计算频率配置
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回复: V3s nor flash 烧录之后必须断电才能引导？发布在 编译和烧写问题专区
@march1993 在 V3s nor flash 烧录之后必须断电才能引导？ 中说：
u-boot-sunxi-with-spl.bin
考虑u-boot-sunxi-with-spl.bin代码给rtc的fel标识位置位了
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回复: T113-S3 MIPI + LVDS 可以实现吗发布在 MR Series
@lansecd lcd_gpio_0 = <&pio PD 20 GPIO_ACTIVE_HIGH>; //reset 在Uboot里怎么配置的
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回复: 2.4 spi lcd点不亮发布在 A Series
配置成DBI了，老版本SDK需要手动注释DBI功能
lichee\rtos-hal\hal\source\spilcd\lcd_fb\lcd_fb_feature.h
新版SDK已修复
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T113 busybox init 配置 overlayfs 为 UDISK 分区而不是 rootfs_data发布在 Linux
- 先确定挂载overlayfs
查看 pseudo_init 中 MOUNT_OVERLAY 是不是 1，如果不是配置为 1
package/busybox-init-base-files/files/pseudo_init
- 修改挂载分区
找到文件末尾，吧 rootfs_data 改成UDISK
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busybox init 简介发布在 Linux
一、简介
tina 使用busybox init方式启动，首先调用执行pseudo_init（挂载文件系统，如/proc、/tmp、/sys /etc、/usr），接着会调用/sbin/init进程，而init进程调用的第一个启动脚本为/etc/init.d/rcS。
二、平台的自定义
不同的平台文件系统具有其共性与特殊性。tina/packge/busybox-init-base-files/files下提供了所有平台的基础文件。而在tina/target/allwinner/XXX/busybox-init-base-files下存放的是平台特性文件，其优先级高于前者,即当前者目录和后者存在有相同文件时，以后者为准。如有以下两个文件:A：tina/target/allwinner/r11-R11_pref1/busybox-init-base-files/etc/banner
B：tina/package/busybox-init-base-files/files/etc/banner最终拷贝到文件系统中的为A。
三、pseudo_init与rcS
pseudo_init与rcS文件中存在很多平台共性的代码，避免系统充斥大量冗余代码,以及方便基础文件的维护和开发。所以不允许在特定平台下自定义pseudo_init、rcS文件（必须使用tina/packge/busybox-init-base-files/files下的pseudo_init、rcS）。
如果需要添加平台特定配置（pseudo_init，rcS没有配置），可将其写到rc.preboot,rc.final中，参考第四节。
四、rcS脚本
1.功能描述
（1）执行/etc/init.d/rc.preboot。
为了满足开机快速启动的需求，提供了用户可自定义rc.preboot文件，即在tina/target/allwinner/XXX/busybox-init-base-files/etc/init.d/目录下创建rc.preboot脚本文件，将会被rcS最先调用执行。
（2）配置打印级别，主机名称。
（3）执行/etc/init.d/rc.log，配置系统log信息。
系统默认使用的是tina/package/busybox-init-base-files/files/etc/init.d/rc.log脚本进行配置系统log信息。用户可在tina/target/allwinner/XXX/busybox-init-base-files/etc/init.d/下创建rc.log，自定义rc.log。
如果需要使用默认rc.log，需要在make menuconfig配置。Base system ---> busybox-init-base-files......................... Busybox init base system ---> [*] Use the rc.log（4）挂载UDISK。
（5）执行/etc/init.d/rc.modules，加载内核模块。
系统默认使用的是tina/package/busybox-init-base-files/files/etc/init.d/rc.modules脚本进行内核模块自加载，用户可在tina/target/allwinner/XXX/busybox-init-base-files/etc/init.d/下创建rc.modules，自定义rc.modules。
如果需要使用默认rc.modules，需要在make menuconfig配置如下。Base system ---> busybox-init-base-files......................... Busybox init base system ---> [*] Use the rc.modules（6）启动/etc/rc.d下的脚本。
关于执行rc.d下的启动脚本，目的为兼容procd式的应用脚本。/etc/rc.d下的脚本是链接到/etc/init.d/下，默认情况下只执行adbd,如果需要执行其他脚本，需要在tina/target/allwinner/XXX/busybox-init-base-files/etc/init.d/下，自定义load_script.conf文件，文件内容中写上要启动的应用，如adbd（注意，每一个应用占一行）。可参考：tina/packge/busybox-init-base-files/files/etc/init.d/load_script.conf。如果需要执行rc.d下的启动脚本，需要在make menuconfig做如下配置。 Base system ---> busybox-init-base-files......................... Busybox init base system ---> [*] Auto load the script in /etc/rc.d（7）ota初始化。
（8）执行/etc/init.d/rc.final,用户自定义启动脚本。
用户可在tina/packge/busybox-init-base-files/files/etc/init.d/下创建一个rc.final脚本，自定义启动应用程序,该脚本将会被rcS最后调用执行。2.rc.preboot与rc.final的区别？
rc.preboot比rc.final先运行，在执行rc.preboot脚本的时候，系统的一些初始化操作还没完成，如挂载UDISK、内核模块自加载、ota等等操作。而rc.final执行的时候，以上的初始化操作已经完成。五.如何写应用的启动脚本
example：开机自启动smartlinkd（tina/package/allwinner/smartlinkd/files/smartlinkd.init）
1.方法一（特定格式要求）详细的格式参考：
https://wiki.openwrt.org/inbox/procd-init-scripts
https://wiki.openwrt.org/doc/techref/initscripts（1）procd式
#!/bin/sh /etc/rc.common #本质为script脚本,以#!开头, 之后执行/etc/rc.common START=98 #开机启动优先级(序列) [数值越小, 越先启动] STOP=98 #关机停止优先级(序列) [数值越小, 越先关闭] USE_PROCD=1 PROG=smartlinkd start_service() { #启动函数 procd_open_instance procd_set_param command $PROG -d procd_close_instance } shutdown() { echo shutdown }（2）Sys式
#!/bin/sh /etc/rc.common START=98 STOP=98 PROG=smartlinkd start() { smartlinkd -d & }使用上述procd式和sys式脚本，既能兼容procd init启动和busybox init的启动方式。
另外如果使用的是busybox init的启动方式，还需要在load_script.conf文件中换行添加内容：smartlinkd2.方法二（无特定格式要求）
创建rc.preboot或者rc.final脚本，添加启动smartlinkd的内容。 -
回复: T113-S3平台，使用can通信，TX发送数据出现大量错误码发布在 其它全志芯片讨论区
@duanzhh 请问SDK是哪里获取的？据我所知CAN目前在T113-I的平台上有压测过，T113-S3的SDK里的驱动可能是很早期的版本
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回复: V851s buildroot openwrt 编译GCC失败发布在 编译和烧写问题专区
@kanken6174 不建议编译gcc进入固件，首先这个gcc没有适配平台，其次v851s的64M内存也无法支持gcc的使用
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回复: T113基于Longan在LVGL中如何播放视屏，通过tplayer发布在 GUI
static lv_style_t style_scr_act; if (style_scr_act.prop_cnt == 0) { lv_style_init(&style_scr_act); lv_style_set_bg_opa(&style_scr_act, LV_OPA_COVER); lv_obj_add_style(lv_scr_act(), &style_scr_act, 0); } lv_disp_get_default()->driver->screen_transp = 1; lv_disp_set_bg_opa(lv_disp_get_default(), LV_OPA_TRANSP); /* Empty the buffer, not emptying will cause the UI to be opaque */ lv_memset_00(lv_disp_get_default()->driver->draw_buf->buf_act, lv_disp_get_default()->driver->draw_buf->size * sizeof(lv_color32_t)); lv_style_set_bg_opa(&style_scr_act, LV_OPA_TRANSP); lv_obj_report_style_change(&style_scr_act);设置透明层
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回复: R128S2 Ubuntu20.04 编译系统错误发布在 A Series
@oneofzero 这个是，直接从其他sdk复制过来的吗？、
rm -rf out rm -rf lichee/rtos/build/ -
回复: R128S2 Ubuntu20.04 编译系统错误发布在 A Series
先删除预解压的工具链，再重新解压。这是因为之前解压工具链解压未完成导致丢失文件。
rm -rf lichee/rtos/tools/riscv64-elf-x86_64-20201104 -
回复: 全志T113-i 或者V85X MIPI DSI 寻求控制器寄存器资料发布在 V Series
@chrisvista 在 全志T113-i 或者V85X MIPI DSI 寻求控制器寄存器资料 中说：
统定义里面不停更新，比如第一个就已经改变了：
A64的MIPI DSI是使用的 synopsys 的，T113的不是这个IP，所以有差异
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回复: 全志T113-i 或者V85X MIPI DSI 寻求控制器寄存器资料发布在 V Series
芯片寄存器开放有很多因素制约，大部分外购的IP都不允许详细描述寄存器，需要提交申请审核后才能公开，法务流程很长索性不开放，开放了还会有潜在的法律风险和抄袭风险，再加上IP迭代和升级，勘误和修改。所以一般是需要定制化的客户有专门的对接。国外芯片自己自研的IP或者购买的IP走了审核流程的开放，也有很多芯片不开放，需要NDA后专门对接。
其实国外做的好的也就TI，NXP，ST那几家的芯片，博通高通一样没啥资料。
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回复: 全志T113-i 或者V85X MIPI DSI 寻求控制器寄存器资料发布在 V Series
/* * Detail information of registers */ union dsi_ctl_reg_t { u32 dwval; struct { u32 dsi_en:1; u32 res0:31; } bits; }; union dsi_gint0_reg_t { u32 dwval; struct { u32 dsi_irq_en:16; u32 dsi_irq_flag:16; } bits; }; union dsi_gint1_reg_t { u32 dwval; struct { u32 video_line_int_num:13; u32 res0:19; } bits; }; union dsi_basic_ctl_reg_t { u32 dwval; struct { u32 video_mode_burst:1; u32 hsa_hse_dis:1; u32 hbp_dis:1; u32 trail_fill:1; u32 trail_inv:4; u32 res0:8; u32 brdy_set:8; u32 brdy_l_sel:3; u32 res1:5; } bits; }; union dsi_basic_ctl0_reg_t { u32 dwval; struct { u32 inst_st:1; u32 res0:3; u32 src_sel:2; u32 res1:4; u32 fifo_manual_reset:1; u32 res2:1; u32 fifo_gating:1; u32 res3:3; u32 ecc_en:1; u32 crc_en:1; u32 hs_eotp_en:1; u32 res4:13; } bits; }; union dsi_basic_ctl1_reg_t { u32 dwval; struct { u32 dsi_mode:1; u32 video_frame_start:1; u32 video_precision_mode_align:1; u32 res0:1; u32 video_start_delay:13; u32 res1:15; } bits; }; union dsi_basic_size0_reg_t { u32 dwval; struct { u32 vsa:12; u32 res0:4; u32 vbp:12; u32 res1:4; } bits; }; union dsi_basic_size1_reg_t { u32 dwval; struct { u32 vact:12; u32 res0:4; u32 vt:13; u32 res1:3; } bits; }; union dsi_basic_inst0_reg_t { u32 dwval; struct { u32 lane_den:4; u32 lane_cen:1; u32 res0:11; u32 trans_start_condition:4; u32 trans_packet:4; u32 escape_enrty:4; u32 instru_mode:4; } bits; }; union dsi_basic_inst1_reg_t { u32 dwval; struct { u32 inst0_sel:4; u32 inst1_sel:4; u32 inst2_sel:4; u32 inst3_sel:4; u32 inst4_sel:4; u32 inst5_sel:4; u32 inst6_sel:4; u32 inst7_sel:4; } bits; }; union dsi_basic_inst2_reg_t { u32 dwval; struct { u32 loop_n0:12; u32 res0:4; u32 loop_n1:12; u32 res1:4; } bits; }; union dsi_basic_inst3_reg_t { u32 dwval; struct { u32 inst0_jump:4; u32 inst1_jump:4; u32 inst2_jump:4; u32 inst3_jump:4; u32 inst4_jump:4; u32 inst5_jump:4; u32 inst6_jump:4; u32 inst7_jump:4; } bits; }; union dsi_basic_inst4_reg_t { u32 dwval; struct { u32 jump_cfg_num:16; u32 jump_cfg_point:4; u32 jump_cfg_to:4; u32 res0:4; u32 jump_cfg_en:1; u32 res1:3; } bits; }; union dsi_basic_tran0_reg_t { u32 dwval; struct { u32 trans_start_set:13; u32 res0:19; } bits; }; union dsi_basic_tran1_reg_t { u32 dwval; struct { u32 trans_size:16; u32 res0:12; u32 trans_end_condition:1; u32 res1:3; } bits; }; union dsi_basic_tran2_reg_t { u32 dwval; struct { u32 trans_cycle_set:16; u32 res0:16; } bits; }; union dsi_basic_tran3_reg_t { u32 dwval; struct { u32 trans_blank_set:16; u32 res0:16; } bits; }; union dsi_basic_tran4_reg_t { u32 dwval; struct { u32 hs_zero_reduce_set:16; u32 res0:16; } bits; }; union dsi_basic_tran5_reg_t { u32 dwval; struct { u32 drq_set:10; u32 res0:18; u32 drq_mode:1; u32 res1:3; } bits; }; union dsi_pixel_ctl0_reg_t { u32 dwval; struct { u32 pixel_format:4; u32 pixel_endian:1; u32 res0:11; u32 pd_plug_dis:1; u32 res1:15; } bits; }; union dsi_pixel_ctl1_reg_t { u32 dwval; struct { u32 res0; } bits; }; union dsi_pixel_ph_reg_t { u32 dwval; struct { u32 dt:6; u32 vc:2; u32 wc:16; u32 ecc:8; } bits; }; union dsi_pixel_pd_reg_t { u32 dwval; struct { u32 pd_tran0:8; u32 res0:8; u32 pd_trann:8; u32 res1:8; } bits; }; union dsi_pixel_pf0_reg_t { u32 dwval; struct { u32 crc_force:16; u32 res0:16; } bits; }; union dsi_pixel_pf1_reg_t { u32 dwval; struct { u32 crc_init_line0:16; u32 crc_init_linen:16; } bits; }; union dsi_short_pkg_reg_t { u32 dwval; struct { u32 dt:6; u32 vc:2; u32 d0:8; u32 d1:8; u32 ecc:8; } bits; }; union dsi_blk_pkg0_reg_t { u32 dwval; struct { u32 dt:6; u32 vc:2; u32 wc:16; u32 ecc:8; } bits; }; union dsi_blk_pkg1_reg_t { u32 dwval; struct { u32 pd:8; u32 res0:8; u32 pf:16; } bits; }; union dsi_burst_line_reg_t { u32 dwval; struct { u32 line_num:16; u32 line_syncpoint:16; } bits; }; union dsi_burst_drq_reg_t { u32 dwval; struct { u32 drq_edge0:16; u32 drq_edge1:16; } bits; }; union dsi_cmd_ctl_reg_t { u32 dwval; struct { u32 tx_size:8; u32 tx_status:1; u32 tx_flag:1; u32 res0:6; u32 rx_size:5; u32 res1:3; u32 rx_status:1; u32 rx_flag:1; u32 rx_overflow:1; u32 res2:5; } bits; }; union dsi_cmd_data_reg_t { u32 dwval; struct { u32 byte0:8; u32 byte1:8; u32 byte2:8; u32 byte3:8; } bits; }; union dsi_debug0_reg_t { u32 dwval; struct { u32 video_curr_line:13; u32 res0:19; } bits; }; union dsi_debug1_reg_t { u32 dwval; struct { u32 video_curr_lp2hs:16; u32 res0:16; } bits; }; union dsi_debug2_reg_t { u32 dwval; struct { u32 trans_low_flag:1; u32 trans_fast_flag:1; u32 res0:2; u32 curr_loop_num:16; u32 curr_instru_num:3; u32 res1:1; u32 instru_unknown_flag:8; } bits; }; union dsi_debug3_reg_t { u32 dwval; struct { u32 res0:16; u32 curr_fifo_num:16; } bits; }; union dsi_debug4_reg_t { u32 dwval; struct { u32 test_data:24; u32 res0:4; u32 dsi_fifo_bist_en:1; u32 res1:3; } bits; }; union dsi_reservd_reg_t { u32 dwval; struct { u32 res0; } bits; }; struct __de_dsi_dev_t { /* 0x00 - 0x0c */ union dsi_ctl_reg_t dsi_gctl; union dsi_gint0_reg_t dsi_gint0; union dsi_gint1_reg_t dsi_gint1; union dsi_basic_ctl_reg_t dsi_basic_ctl; /* 0x10 - 0x1c */ union dsi_basic_ctl0_reg_t dsi_basic_ctl0; union dsi_basic_ctl1_reg_t dsi_basic_ctl1; union dsi_basic_size0_reg_t dsi_basic_size0; union dsi_basic_size1_reg_t dsi_basic_size1; /* 0x20 - 0x3c */ union dsi_basic_inst0_reg_t dsi_inst_func[8]; /* 0x40 - 0x5c */ union dsi_basic_inst1_reg_t dsi_inst_loop_sel; union dsi_basic_inst2_reg_t dsi_inst_loop_num; union dsi_basic_inst3_reg_t dsi_inst_jump_sel; union dsi_basic_inst4_reg_t dsi_inst_jump_cfg[2]; union dsi_basic_inst2_reg_t dsi_inst_loop_num2; union dsi_reservd_reg_t dsi_reg058[2]; /* 0x60 - 0x6c */ union dsi_basic_tran0_reg_t dsi_trans_start; union dsi_reservd_reg_t dsi_reg064[3]; /* 0x70 - 0x7c */ union dsi_reservd_reg_t dsi_reg070[2]; union dsi_basic_tran4_reg_t dsi_trans_zero; union dsi_basic_tran5_reg_t dsi_tcon_drq; /* 0x80 - 0x8c */ union dsi_pixel_ctl0_reg_t dsi_pixel_ctl0; union dsi_pixel_ctl1_reg_t dsi_pixel_ctl1; union dsi_reservd_reg_t dsi_reg088[2]; /* 0x90 - 0x9c */ union dsi_pixel_ph_reg_t dsi_pixel_ph; union dsi_pixel_pd_reg_t dsi_pixel_pd; union dsi_pixel_pf0_reg_t dsi_pixel_pf0; union dsi_pixel_pf1_reg_t dsi_pixel_pf1; /* 0xa0 - 0xac */ union dsi_reservd_reg_t dsi_reg0a0[4]; /* 0xb0 - 0xbc */ union dsi_short_pkg_reg_t dsi_sync_hss; union dsi_short_pkg_reg_t dsi_sync_hse; union dsi_short_pkg_reg_t dsi_sync_vss; union dsi_short_pkg_reg_t dsi_sync_vse; /* 0xc0 - 0xcc */ union dsi_blk_pkg0_reg_t dsi_blk_hsa0; union dsi_blk_pkg1_reg_t dsi_blk_hsa1; union dsi_blk_pkg0_reg_t dsi_blk_hbp0; union dsi_blk_pkg1_reg_t dsi_blk_hbp1; /* 0xd0 - 0xdc */ union dsi_blk_pkg0_reg_t dsi_blk_hfp0; union dsi_blk_pkg1_reg_t dsi_blk_hfp1; union dsi_reservd_reg_t dsi_reg0d8[2]; /* 0xe0 - 0xec */ union dsi_blk_pkg0_reg_t dsi_blk_hblk0; union dsi_blk_pkg1_reg_t dsi_blk_hblk1; union dsi_blk_pkg0_reg_t dsi_blk_vblk0; union dsi_blk_pkg1_reg_t dsi_blk_vblk1; /* 0xf0 - 0x1fc */ union dsi_burst_line_reg_t dsi_burst_line; union dsi_burst_drq_reg_t dsi_burst_drq; union dsi_reservd_reg_t dsi_reg0f0[66]; /* 0x200 - 0x23c */ union dsi_cmd_ctl_reg_t dsi_cmd_ctl; union dsi_reservd_reg_t dsi_reg204[15]; /* 0x240 - 0x2dc */ union dsi_cmd_data_reg_t dsi_cmd_rx[8]; union dsi_reservd_reg_t dsi_reg260[32]; /* 0x2e0 - 0x2ec */ union dsi_debug0_reg_t dsi_debug_video0; union dsi_debug1_reg_t dsi_debug_video1; union dsi_reservd_reg_t dsi_reg2e8[2]; /* 0x2f0 - 0x2fc */ union dsi_debug2_reg_t dsi_debug_inst; union dsi_debug3_reg_t dsi_debug_fifo; union dsi_debug4_reg_t dsi_debug_data; union dsi_reservd_reg_t dsi_reg2fc; /* 0x300 - 0x3fc */ union dsi_cmd_data_reg_t dsi_cmd_tx[64]; }; union dphy_ctl_reg_t { u32 dwval; struct { u32 module_en:1; u32 res0:3; u32 lane_num:2; u32 res1:26; } bits; }; union dphy_tx_ctl_reg_t { u32 dwval; struct { u32 tx_d0_force:1; u32 tx_d1_force:1; u32 tx_d2_force:1; u32 tx_d3_force:1; u32 tx_clk_force:1; u32 res0:3; u32 lptx_endian:1; u32 hstx_endian:1; u32 lptx_8b9b_en:1; u32 hstx_8b9b_en:1; u32 force_lp11:1; u32 res1:3; u32 ulpstx_data0_exit:1; u32 ulpstx_data1_exit:1; u32 ulpstx_data2_exit:1; u32 ulpstx_data3_exit:1; u32 ulpstx_clk_exit:1; u32 res2:3; u32 hstx_data_exit:1; u32 hstx_clk_exit:1; u32 res3:2; u32 hstx_clk_cont:1; u32 ulpstx_enter:1; u32 res4:2; } bits; }; union dphy_rx_ctl_reg_t { u32 dwval; struct { u32 res0:8; u32 lprx_endian:1; u32 hsrx_endian:1; u32 lprx_8b9b_en:1; u32 hsrx_8b9b_en:1; u32 hsrx_sync:1; u32 res1:3; u32 lprx_trnd_mask:4; u32 rx_d0_force:1; u32 rx_d1_force:1; u32 rx_d2_force:1; u32 rx_d3_force:1; u32 rx_clk_force:1; u32 res2:6; u32 dbc_en:1; } bits; }; union dphy_tx_time0_reg_t { u32 dwval; struct { u32 lpx_tm_set:8; u32 dterm_set:8; u32 hs_pre_set:8; u32 hs_trail_set:8; } bits; }; union dphy_tx_time1_reg_t { u32 dwval; struct { u32 ck_prep_set:8; u32 ck_zero_set:8; u32 ck_pre_set:8; u32 ck_post_set:8; } bits; }; union dphy_tx_time2_reg_t { u32 dwval; struct { u32 ck_trail_set:8; u32 hs_dly_set:16; u32 res0:4; u32 hs_dly_mode:1; u32 res1:3; } bits; }; union dphy_tx_time3_reg_t { u32 dwval; struct { u32 lptx_ulps_exit_set:20; u32 res0:12; } bits; }; union dphy_tx_time4_reg_t { u32 dwval; struct { u32 hstx_ana0_set:8; u32 hstx_ana1_set:8; u32 res0:16; } bits; }; union dphy_rx_time0_reg_t { u32 dwval; struct { u32 lprx_to_en:1; u32 freq_cnt_en:1; u32 res0:2; u32 hsrx_clk_miss_en:1; u32 hsrx_sync_err_to_en:1; u32 res1:2; u32 lprx_to:8; u32 hsrx_clk_miss:8; u32 hsrx_sync_err_to:8; } bits; }; union dphy_rx_time1_reg_t { u32 dwval; struct { u32 lprx_ulps_wp:20; u32 rx_dly:12; } bits; }; union dphy_rx_time2_reg_t { u32 dwval; struct { u32 hsrx_ana0_set:8; u32 hsrx_ana1_set:8; u32 res0:16; } bits; }; union dphy_rx_time3_reg_t { u32 dwval; struct { u32 freq_cnt:16; u32 res0:8; u32 lprst_dly:8; } bits; }; union dphy_ana0_reg_t { u32 dwval; struct { u32 reg_selsck:1; u32 reg_rsd:1; u32 reg_sfb:2; u32 reg_plr:4; u32 reg_den:4; u32 reg_slv:3; u32 reg_sdiv2:1; u32 reg_srxck:4; u32 reg_srxdt:4; u32 reg_dmpd:4; u32 reg_dmpc:1; u32 reg_pwenc:1; u32 reg_pwend:1; u32 reg_pws:1; } bits; }; union dphy_ana1_reg_t { u32 dwval; struct { u32 reg_stxck:1; u32 res0:3; u32 reg_svdl0:4; u32 reg_svdl1:4; u32 reg_svdl2:4; u32 reg_svdl3:4; u32 reg_svdlc:4; u32 reg_svtt:4; u32 reg_csmps:2; u32 res1:1; u32 reg_vttmode:1; } bits; }; union dphy_ana2_reg_t { u32 dwval; struct { u32 ana_cpu_en:1; u32 enib:1; u32 enrvs:1; u32 res0:1; u32 enck_cpu:1; u32 entxc_cpu:1; u32 enckq_cpu:1; u32 res1:1; u32 entx_cpu:4; u32 res2:1; u32 entermc_cpu:1; u32 enrxc_cpu:1; u32 res3:1; u32 enterm_cpu:4; u32 enrx_cpu:4; u32 enp2s_cpu:4; u32 res4:4; } bits; }; union dphy_ana3_reg_t { u32 dwval; struct { u32 enlptx_cpu:4; u32 enlprx_cpu:4; u32 enlpcd_cpu:4; u32 enlprxc_cpu:1; u32 enlptxc_cpu:1; u32 enlpcdc_cpu:1; u32 res0:1; u32 entest:1; u32 enckdbg:1; u32 enldor:1; u32 res1:5; u32 enldod:1; u32 enldoc:1; u32 endiv:1; u32 envttc:1; u32 envttd:4; } bits; }; union dphy_ana4_reg_t { u32 dwval; struct { u32 reg_txpusd:2; u32 reg_txpusc:2; u32 reg_txdnsd:2; u32 reg_txdnsc:2; u32 reg_tmsd:2; u32 reg_tmsc:2; u32 reg_ckdv:5; u32 reg_vtt_set:3; u32 reg_dmplvd:4; u32 reg_dmplvc:1; u32 reg_ib:2; u32 res4:1; u32 reg_comtest:2; u32 en_comtest:1; u32 en_mipi:1; } bits; }; union dphy_int_en0_reg_t { u32 dwval; struct { u32 sot_d0_int:1; u32 sot_d1_int:1; u32 sot_d2_int:1; u32 sot_d3_int:1; u32 sot_err_d0_int:1; u32 sot_err_d1_int:1; u32 sot_err_d2_int:1; u32 sot_err_d3_int:1; u32 sot_sync_err_d0_int:1; u32 sot_sync_err_d1_int:1; u32 sot_sync_err_d2_int:1; u32 sot_sync_err_d3_int:1; u32 rx_alg_err_d0_int:1; u32 rx_alg_err_d1_int:1; u32 rx_alg_err_d2_int:1; u32 rx_alg_err_d3_int:1; u32 res0:6; u32 cd_lp0_err_clk_int:1; u32 cd_lp1_err_clk_int:1; u32 cd_lp0_err_d0_int:1; u32 cd_lp1_err_d0_int:1; u32 cd_lp0_err_d1_int:1; u32 cd_lp1_err_d1_int:1; u32 cd_lp0_err_d2_int:1; u32 cd_lp1_err_d2_int:1; u32 cd_lp0_err_d3_int:1; u32 cd_lp1_err_d3_int:1; } bits; }; union dphy_int_en1_reg_t { u32 dwval; struct { u32 ulps_d0_int:1; u32 ulps_d1_int:1; u32 ulps_d2_int:1; u32 ulps_d3_int:1; u32 ulps_wp_d0_int:1; u32 ulps_wp_d1_int:1; u32 ulps_wp_d2_int:1; u32 ulps_wp_d3_int:1; u32 ulps_clk_int:1; u32 ulps_wp_clk_int:1; u32 res0:2; u32 lpdt_d0_int:1; u32 rx_trnd_d0_int:1; u32 tx_trnd_err_d0_int:1; u32 undef1_d0_int:1; u32 undef2_d0_int:1; u32 undef3_d0_int:1; u32 undef4_d0_int:1; u32 undef5_d0_int:1; u32 rst_d0_int:1; u32 rst_d1_int:1; u32 rst_d2_int:1; u32 rst_d3_int:1; u32 esc_cmd_err_d0_int:1; u32 esc_cmd_err_d1_int:1; u32 esc_cmd_err_d2_int:1; u32 esc_cmd_err_d3_int:1; u32 false_ctl_d0_int:1; u32 false_ctl_d1_int:1; u32 false_ctl_d2_int:1; u32 false_ctl_d3_int:1; } bits; }; union dphy_int_en2_reg_t { u32 dwval; struct { u32 res0; } bits; }; union dphy_int_pd0_reg_t { u32 dwval; struct { u32 sot_d0_pd:1; u32 sot_d1_pd:1; u32 sot_d2_pd:1; u32 sot_d3_pd:1; u32 sot_err_d0_pd:1; u32 sot_err_d1_pd:1; u32 sot_err_d2_pd:1; u32 sot_err_d3_pd:1; u32 sot_sync_err_d0_pd:1; u32 sot_sync_err_d1_pd:1; u32 sot_sync_err_d2_pd:1; u32 sot_sync_err_d3_pd:1; u32 rx_alg_err_d0_pd:1; u32 rx_alg_err_d1_pd:1; u32 rx_alg_err_d2_pd:1; u32 rx_alg_err_d3_pd:1; u32 res0:6; u32 cd_lp0_err_clk_pd:1; u32 cd_lp1_err_clk_pd:1; u32 cd_lp0_err_d1_pd:1; u32 cd_lp1_err_d1_pd:1; u32 cd_lp0_err_d0_pd:1; u32 cd_lp1_err_d0_pd:1; u32 cd_lp0_err_d2_pd:1; u32 cd_lp1_err_d2_pd:1; u32 cd_lp0_err_d3_pd:1; u32 cd_lp1_err_d3_pd:1; } bits; }; union dphy_int_pd1_reg_t { u32 dwval; struct { u32 ulps_d0_pd:1; u32 ulps_d1_pd:1; u32 ulps_d2_pd:1; u32 ulps_d3_pd:1; u32 ulps_wp_d0_pd:1; u32 ulps_wp_d1_pd:1; u32 ulps_wp_d2_pd:1; u32 ulps_wp_d3_pd:1; u32 ulps_clk_pd:1; u32 ulps_wp_clk_pd:1; u32 res0:2; u32 lpdt_d0_pd:1; u32 rx_trnd_d0_pd:1; u32 tx_trnd_err_d0_pd:1; u32 undef1_d0_pd:1; u32 undef2_d0_pd:1; u32 undef3_d0_pd:1; u32 undef4_d0_pd:1; u32 undef5_d0_pd:1; u32 rst_d0_pd:1; u32 rst_d1_pd:1; u32 rst_d2_pd:1; u32 rst_d3_pd:1; u32 esc_cmd_err_d0_pd:1; u32 esc_cmd_err_d1_pd:1; u32 esc_cmd_err_d2_pd:1; u32 esc_cmd_err_d3_pd:1; u32 false_ctl_d0_pd:1; u32 false_ctl_d1_pd:1; u32 false_ctl_d2_pd:1; u32 false_ctl_d3_pd:1; } bits; }; union dphy_int_pd2_reg_t { u32 dwval; struct { u32 res0; } bits; }; union dphy_dbg0_reg_t { u32 dwval; struct { u32 lptx_sta_d0:3; u32 res0:1; u32 lptx_sta_d1:3; u32 res1:1; u32 lptx_sta_d2:3; u32 res2:1; u32 lptx_sta_d3:3; u32 res3:1; u32 lptx_sta_clk:3; u32 res4:9; u32 direction:1; u32 res5:3; } bits; }; union dphy_dbg1_reg_t { u32 dwval; struct { u32 lptx_dbg_en:1; u32 hstx_dbg_en:1; u32 res0:2; u32 lptx_set_d0:2; u32 lptx_set_d1:2; u32 lptx_set_d2:2; u32 lptx_set_d3:2; u32 lptx_set_ck:2; u32 res1:18; } bits; }; union dphy_dbg2_reg_t { u32 dwval; struct { u32 hstx_data; } bits; }; union dphy_dbg3_reg_t { u32 dwval; struct { u32 lprx_sta_d0:4; u32 lprx_sta_d1:4; u32 lprx_sta_d2:4; u32 lprx_sta_d3:4; u32 lprx_sta_clk:4; u32 res0:12; } bits; }; union dphy_dbg4_reg_t { u32 dwval; struct { u32 lprx_phy_d0:2; u32 lprx_phy_d1:2; u32 lprx_phy_d2:2; u32 lprx_phy_d3:2; u32 lprx_phy_clk:2; u32 res0:6; u32 lpcd_phy_d0:2; u32 lpcd_phy_d1:2; u32 lpcd_phy_d2:2; u32 lpcd_phy_d3:2; u32 lpcd_phy_clk:2; u32 res1:6; } bits; }; union dphy_dbg5_reg_t { u32 dwval; struct { u32 hsrx_data; } bits; }; union dphy_reservd_reg_t { u32 dwval; struct { u32 res0; } bits; }; union dphy_tx_skew_reg0_t { __u32 dwavl; struct { __u32 reg_skewcal_sync : 8 ; // default: 0; __u32 reg_skewcal : 8 ; // default: 0; __u32 skewcal_trail_set : 8 ; // default: 0; __u32 skewcal_zero_set : 8 ; // default: 0; } bits; }; union dphy_tx_skew_reg1_t { __u32 dwval; struct { __u32 skewcal_init_set : 16 ; // default: 0; __u32 skewcal_pedic_set : 8 ; // default: 0; __u32 skewcal_sync_set : 8 ; // default: 0; } bits; }; union dphy_tx_skew_reg2_t { __u32 dwval; struct { __u32 skewcal_prepare_lp00 : 8 ; //default: 0; __u32 skewcal_trail_inv : 1 ; //default: 0; __u32 en_skewcal_perdic : 1 ; //default: 0; __u32 en_skewcal_init : 1 ; //default: 0; __u32 res0 : 21 ; //default: 0; } bits; }; union dphy_pll_reg0_t { __u32 dwval; struct { __u32 m1 : 4 ; //default: 0x3; __u32 m0 : 2 ; //default: 0; __u32 tdiv : 1 ; //default: 0; __u32 ndet : 1 ; //default: 0x1; __u32 n : 8 ; //default: 0x32; __u32 p : 4 ; //default: 0; __u32 pll_en : 1 ; //default: 0x1; __u32 en_lvs : 1 ; //default: 0x1; __u32 ldo_en : 1 ; //default: 0x1; __u32 cp36_en : 1 ; //default: 0x1; __u32 res0 : 8 ; //default: 0; } bits; }; union dphy_pll_reg1_t { __u32 dwval; struct { __u32 test_en : 1 ; //default: 0x1; __u32 atest_sel : 2 ; //default: 0; __u32 icp_sel : 2 ; //default: 0; __u32 lpf_sw : 1 ; //default: 0; __u32 vsetd : 3 ; //default: 0x2; __u32 vseta : 3 ; //default: 0x2; __u32 lockdet_en : 1 ; //default: 0; __u32 lockmdsel : 1 ; //default: 0; __u32 unlock_mdsel : 2 ; //default: 0; __u32 res0 : 16 ; //default: 0; } bits; }; union dphy_pll_reg2_t { __u32 dwval; struct { __u32 frac : 12 ; //default: 0x800; __u32 ss_int : 8 ; //default: 0x32; __u32 ss_frac : 9 ; //default: 0; __u32 ss_en : 1 ; //default: 0; __u32 ff_en : 1 ; //default: 0; __u32 sdm_en : 1 ; //default: 0x1; } bits; }; union combo_phy_reg0_t { __u32 dwval; struct { __u32 en_cp : 1 ; //default: 0; __u32 en_comboldo : 1 ; //default: 0; __u32 en_lvds : 1 ; //default: 0; __u32 en_mipi : 1 ; //default: 0; __u32 en_test_0p8 : 1 ; //default: 0; __u32 en_test_comboldo : 1 ; //default: 0; __u32 res0 : 26; //default: 0; } bits; }; union combo_phy_reg1_t { __u32 dwval; struct { __u32 reg_vref0p8 : 3 ; //default: 0; __u32 res0 : 1 ; //default: 0; __u32 reg_vref1p6 : 3 ; //default: 0; __u32 res1 : 25; //default: 0; } bits; }; union combo_phy_reg2_t { __u32 dwval; struct { __u32 hs_stop_dly : 8 ; //default: 0; __u32 res0 : 24; //default: 0; } bits; }; /* dphy register define */ struct __de_dsi_dphy_dev_t { /* 0x00 - 0x0c */ union dphy_ctl_reg_t dphy_gctl; union dphy_tx_ctl_reg_t dphy_tx_ctl; union dphy_rx_ctl_reg_t dphy_rx_ctl; union dphy_reservd_reg_t dphy_reg00c; /* 0x10 - 0x1c */ union dphy_tx_time0_reg_t dphy_tx_time0; union dphy_tx_time1_reg_t dphy_tx_time1; union dphy_tx_time2_reg_t dphy_tx_time2; union dphy_tx_time3_reg_t dphy_tx_time3; /* 0x20 - 0x2c */ union dphy_tx_time4_reg_t dphy_tx_time4; union dphy_reservd_reg_t dphy_reg024[3]; /* 0x30 - 0x3c */ union dphy_rx_time0_reg_t dphy_rx_time0; union dphy_rx_time1_reg_t dphy_rx_time1; union dphy_rx_time2_reg_t dphy_rx_time2; union dphy_reservd_reg_t dphy_reg03c; /* 0x40 - 0x4c */ union dphy_rx_time3_reg_t dphy_rx_time3; union dphy_reservd_reg_t dphy_reg044[2]; union dphy_ana0_reg_t dphy_ana0; /* 0x50 - 0x5c */ union dphy_ana1_reg_t dphy_ana1; union dphy_ana2_reg_t dphy_ana2; union dphy_ana3_reg_t dphy_ana3; union dphy_ana4_reg_t dphy_ana4; /* 0x60 - 0x6c */ union dphy_int_en0_reg_t dphy_int_en0; union dphy_int_en1_reg_t dphy_int_en1; union dphy_int_en2_reg_t dphy_int_en2; union dphy_reservd_reg_t dphy_reg06c; /* 0x70 - 0x7c */ union dphy_int_pd0_reg_t dphy_int_pd0; union dphy_int_pd1_reg_t dphy_int_pd1; union dphy_int_pd2_reg_t dphy_int_pd2; union dphy_reservd_reg_t dphy_reg07c; /* 0x80 - 0xdc */ union dphy_reservd_reg_t dphy_reg080[24]; /* 0xe0 - 0xec */ union dphy_dbg0_reg_t dphy_dbg0; union dphy_dbg1_reg_t dphy_dbg1; union dphy_dbg2_reg_t dphy_dbg2; union dphy_dbg3_reg_t dphy_dbg3; /* 0xf0 - 0xfc */ union dphy_dbg4_reg_t dphy_dbg4; union dphy_dbg5_reg_t dphy_dbg5; union dphy_tx_skew_reg0_t dphy_tx_skew_reg0; /*0xf8 */ union dphy_tx_skew_reg1_t dphy_tx_skew_reg1; /*0xfc */ union dphy_tx_skew_reg2_t dphy_tx_skew_reg2; /*0x100 */ union dphy_pll_reg0_t dphy_pll_reg0; /*0x104 */ union dphy_pll_reg1_t dphy_pll_reg1; /*0x108 */ union dphy_pll_reg2_t dphy_pll_reg2; /*0x10c */ union combo_phy_reg0_t combo_phy_reg0; /*0x110 */ union combo_phy_reg1_t combo_phy_reg1; /*0x114 */ union combo_phy_reg2_t combo_phy_reg2; /*0x118 */ }; union dsi_ph_t { struct { u32 byte012:24; u32 byte3:8; } bytes; struct { u32 bit00:1; u32 bit01:1; u32 bit02:1; u32 bit03:1; u32 bit04:1; u32 bit05:1; u32 bit06:1; u32 bit07:1; u32 bit08:1; u32 bit09:1; u32 bit10:1; u32 bit11:1; u32 bit12:1; u32 bit13:1; u32 bit14:1; u32 bit15:1; u32 bit16:1; u32 bit17:1; u32 bit18:1; u32 bit19:1; u32 bit20:1; u32 bit21:1; u32 bit22:1; u32 bit23:1; u32 bit24:1; u32 bit25:1; u32 bit26:1; u32 bit27:1; u32 bit28:1; u32 bit29:1; u32 bit30:1; u32 bit31:1; } bits; };来源：RT-Thread 官方仓库：https://github.com/RT-Thread/rt-thread/blob/master/bsp/allwinner/libraries/sunxi-hal/hal/source/disp2/disp/de/lowlevel_v2x/de_dsi_type.h
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回复: D1S 如何通过nor flash启动发布在 MR Series
@towel_roll D1-H哪吒MIPI屏幕测试固件（TFT08006）.img 是使用 NAND 的，不能刷进NOR存储器里
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回复: A133編譯kernel 遇到error trying to exec cc1: execvp : No such file or directory发布在 其它全志芯片讨论区
环境没有安装
Ubuntu 22.04 / 20.04
- 更新软件源，更新系统软件包
sudo apt-get update sudo apt-get upgrade -y- 安装开发依赖
sudo apt-get install build-essential subversion git libncurses5-dev zlib1g-dev gawk flex bison quilt libssl-dev xsltproc libxml-parser-perl mercurial bzr ecj cvs unzip lsof- 安装相关工具
sudo apt-get install kconfig-frontends android-tools-mkbootimg python2 libpython3-dev- 增加架构支持
sudo dpkg --add-architecture i386 sudo apt-get update- 安装支持包
sudo apt install gcc-multilib sudo apt install libc6:i386 libstdc++6:i386 lib32z1Ubuntu 18.04
- 更新软件源，更新系统软件包
sudo apt-get update sudo apt-get upgrade -y- 安装开发依赖
sudo apt-get install build-essential subversion git libncurses5-dev zlib1g-dev gawk flex bison quilt libssl-dev xsltproc libxml-parser-perl mercurial bzr ecj cvs unzip lsof- 安装相关工具
sudo apt-get install android-tools-mkbootimg libpython3-dev- 增加架构支持
sudo dpkg --add-architecture i386 sudo apt-get update- 安装支持包
sudo apt install gcc-multilib sudo apt install libc6:i386 libstdc++6:i386 lib32z1Arch Linux / Manjaro
- 更新软件源，更新系统软件包
pacman -Syyuu- 安装开发依赖
pacman -S --needed base-devel autoconf automake bash binutils bison bzip2 fakeroot file findutils flex gawk gcc gettext git grep groff gzip time unzip util-linux wget which zlib asciidoc help2man intltool perl-extutils-makemaker swig- 安装相关工具
pacman -S --needed libelf libtool libxslt m4 make ncurses openssl patch pkgconf python rsync sed texinfo- 增加架构支持
pacman -S --needed multilib-develCentOS / Fedora / openEuler
sudo dnf --setopt install_weak_deps=False --skip-broken install bash-completion bzip2 gcc gcc-c++ git make ncurses-devel patch rsync tar unzip wget which diffutils python2 python3 perl-base perl-Data-Dumper perl-File-Compare perl-File-Copy perl-FindBin perl-Thread-Queue glibc.i686openSUSE
sudo zypper install --no-recommends asciidoc bash bc binutils bzip2 fastjar flex gawk gcc -
回复: 有R128点亮百问网7寸RGB屏的DEMO吗？发布在 A Series
R128-S2 驱动 1024x600 RGB 显示屏 并运行 LVGL
https://bbs.aw-ol.com/topic/4316/share/1 -
回复: 求助！T113 Tina Linux编译报错，intltool-0.51.0发布在 MR Series
@tsy2001 选中之后会勾选依赖，但是取消的时候不会取消依赖的勾选，得去对应配置取消
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回复: 请教如何排查 linux kernel 启动卡主的问题发布在 Linux
@xsyr1024 tina其实就是openwrt，在openwrt中的KERNEL_开头的选项就是会影响到内核配置
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回复: T113开机LOGO闪烁问题发布在 MR Series
@lansecd 在 T113开机LOGO闪烁问题 中说：
@awwwwa 2.1的SDK可以分享一下么
新 SDK 平台下载 D1-H/D1s SDK
https://bbs.aw-ol.com/topic/3947/share/1下载这个即可
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回复: A40i tf卡固化系统到emmc剩余空间指定发布在 飞凌嵌入式专区
@dort91011 这个是UDISK分区，是烧录软件在烧录的时候自动划分的空间。如果需要手动配置，请在sys_partition.fex里手动配置这个分区的size
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回复: 请教如何排查 linux kernel 启动卡主的问题发布在 Linux
@xsyr1024 在 请教如何排查 linux kernel 启动卡主的问题 中说：
[ 0.969253] 000: printk: console [ttyS0] enabled
[ 0.973945] 000: printk: bootconsole [earlycon0] disabled看着是earlycon0作为串口输出驱动正常，但是切换到ttyS0作为串口输出的时候ttyS0没有输出，先检查uart部分
另外这个是LinuxRT内核吗
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回复: A133怎么把触摸配置数组写入到芯片中啊（GT9271）发布在 其它全志芯片讨论区
适配于 A133 Android 13 方案，Linux 5.15
ctp { gt9xx { compatible = "goodix,gt9xx"; reg = <0x5d>; status = "okay"; irq-gpios = <&pio PD 20 GPIO_ACTIVE_LOW>; irq-flags = <2>; reset-gpios = <&pio PD 21 GPIO_ACTIVE_LOW>; vdd_ana-supply = <®_cldo2>; touchscreen-max-id = <11>; touchscreen-size-x = <1280>; touchscreen-size-y = <800>; touchscreen-max-w = <512>; touchscreen-max-p = <512>; //touchscreen-key-map = <172>, <158>; /*KEY_HOMEPAGE=172, KEY_BACK=158，KEY_MENU=139*/ goodix,slide-wakeup = <0>; goodix,type-a-report = <1>; goodix,driver-send-cfg = <0>; goodix,send-cfg-id = <0>; goodix,resume-in-workqueue = <0>; goodix,int-sync = <1>; goodix,revert_x = <0>; goodix,revert_y = <0>; goodix,swap-x2y = <0>; goodix,tp_idle_support = <1>; goodix,esd-protect = <1>; goodix,auto-update-cfg = <0>; goodix,power-off-sleep = <1>; goodix,pen-suppress-finger = <0>; /* GT9271_Config_20221222_v67.cfg*/ goodix,cfg-group0 = [ B4 00 05 20 03 0A 3D 00 01 0A 28 0F 50 32 03 05 00 00 00 00 00 00 06 17 19 1F 14 8E 2E 99 2D 2F 35 11 00 00 00 1A 03 10 00 00 00 00 00 00 00 00 00 00 00 32 50 94 D5 02 07 00 00 04 8E 48 00 8A 4D 00 86 53 00 83 59 00 80 60 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 04 05 06 07 08 09 0C 0D 0E 0F 10 11 14 15 16 17 FF FF FF FF FF FF FF FF FF FF FF FF 28 27 26 25 24 23 22 21 20 1F 1E 1C 1B 19 13 12 11 10 0F 0D 0C 0A 08 07 06 04 02 00 FF FF FF FF FF FF FF FF FF FF FF FF FF FF AB 01 ]; }; -
回复: V853我们来了！！！发布在 V Series
Tina 4.0:
tina_v851se-tinyvision_uart0.zipTina 4.0 摄像头测试：
e8ce3a5d-7cbf-40a3-b16a-1989ce206407-tina_v851se-tinyvision_uart0.zipTina 5.0:
v851se_linux_tinyvision_uart0_SDNand.zipPatch:
e4350d20-eda5-4ff5-b708-5901f5469aa9-tinyvision_patch.tar.gz71d8a58c-6fe2-4a93-96ee-b12bb883b2e1-摄像头测试固件.img
d0ef81d9-3893-4c2c-8903-711cf397a3bb-tinyvision.tgz
CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN8IW21=y CONFIG_SUNXI_GPIO_V2=y #CONFIG_AXP_GPIO=y CONFIG_SYS_CONFIG_NAME="sun8iw21p1" CONFIG_DEFAULT_DEVICE_TREE="sun8iw21p1-soc-system" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_CONSOLE_MUX=y CONFIG_SUNXI_NECESSARY_REPLACE_FDT=y CONFIG_RESERVE_FDT_SIZE=0x20000 CONFIG_PRE_CONSOLE_BUFFER=n # CONFIG_OF_BOARD=y CONFIG_OF_SEPARATE=y CONFIG_SYS_TEXT_BASE=0x42000000 CONFIG_SUNXI_FDT_ADDR=0x41800000 CONFIG_SUNXI_MALLOC_LEN=0x1400000 # Environment # CONFIG_ENV_IS_IN_SUNXI_FLASH=y # CONFIG_SYS_MAXARGS=64 # CONFIG_SUNXI_REDUNDAND_ENVIRONMENT=y # CONFIG_SYS_REDUNDAND_ENVIRONMENT=y # CONFIG_SUNXI_ENV_PARTITION="env" CONFIG_SUNXI_ENV_BACKUP=y # CONFIG_SUNXI_ENV_REDUNDAND_PARTITION="env-redund" # CONFIG_ENV_SIZE=0x20000 #system CONFIG_ARM_SMCCC=y CONFIG_SUNXI_DMA=y CONFIG_CLK_SUNXI=y #SPI CONFIG_SPI=y CONFIG_SUNXI_SPI=y CONFIG_SPI_USE_DMA=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_EON=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_PUYA=y CONFIG_SPI_FLASH_FM=y CONFIG_SPI_FLASH_XT=y CONFIG_SPI_FLASH_ADESTO=y CONFIG_SPI_FLASH_XMC=y CONFIG_SPI_SAMP_DL_EN=y CONFIG_SF_DEFAULT_SPEED=50000000 # BIT(12) BIT(13) (SPI_RX_DUAL|SPI_RX_QUAD) CONFIG_SF_DEFAULT_MODE=0x3000 CONFIG_SPINOR_UBOOT_OFFSET=128 CONFIG_SPINOR_LOGICAL_OFFSET=2016 CONFIG_SPINOR_UBOOT_SECURE_OFFSET=128 CONFIG_SPINOR_LOGICAL_SECURE_OFFSET=2200 #axp CONFIG_SYS_I2C_SUNXI=y CONFIG_I2C4_ENABLE=y CONFIG_SYS_SUNXI_I2C4_SLAVE=0x34 CONFIG_SYS_SUNXI_I2C4_SPEED=400000 CONFIG_SUNXI_POWER=y CONFIG_SUNXI_PMU=y CONFIG_SUNXI_BMU=y CONFIG_AXP2101_POWER=y CONFIG_AXP2101_SUNXI_I2C_SLAVE=0x34 #key #CONFIG_SUNXI_PHY_KEY=y #CONFIG_SUNXI_LRADC_KEY=y #crypto driver CONFIG_SUNXI_CE_DRIVER=y CONFIG_SUNXI_CE_23=y #CONFIG_SF_DEFAULT_SPEED=50000000 # BIT(12) BIT(13) (SPI_RX_DUAL|SPI_RX_QUAD) #CONFIG_SF_DEFAULT_MODE=0x3000 # # PWM_SUNXI # CONFIG_PWM_SUNXI=y # CONFIG_PWM_SUNXI_NEW is not set #CONFIG_SPINOR_UBOOT_OFFSET=128 #CONFIG_SPINOR_LOGICAL_OFFSET=2016 # flash CONFIG_SUNXI_SDMMC=y CONFIG_MMC=y CONFIG_SUNXI_FLASH=y CONFIG_SUNXI_NAND=y CONFIG_SUNXI_UBIFS=y CONFIG_SUNXI_COMM_NAND_V1=y CONFIG_SUNXI_SPINOR=y #usb otg config CONFIG_SUNXI_USB=y CONFIG_SUNXI_EFEX=y CONFIG_SUNXI_BURN=y CONFIG_SUNXI_FASTBOOT=y #partition CONFIG_EFI_PARTITION=y #image CONFIG_ANDROID_BOOT_IMAGE=y #sprite CONFIG_SUNXI_SPRITE=y CONFIG_SUNXI_SECURE_STORAGE=y CONFIG_SUNXI_SPRITE_CARTOON=y #secure feature CONFIG_SUNXI_SECURE_BOOT=y CONFIG_SUNXI_IMAGE_VERIFIER=y CONFIG_SUNXI_KEYBOX=y CONFIG_SUNXI_DRM_SUPPORT=y CONFIG_SUNXI_EXTERN_SECURE_MM_LAYOUT=y CONFIG_SUNXI_HOMLET=y CONFIG_SUNXI_HDCP_HASH=y CONFIG_SUNXI_HDCP_IN_SECURESTORAGE=y #cmd CONFIG_CMD_SUNXI_TIMER=y CONFIG_CMD_SUNXI_SPRITE=y CONFIG_CMD_SUNXI_EFEX=y CONFIG_CMD_SUNXI_BURN=y CONFIG_CMD_GPT=y CONFIG_CMD_FAT=y CONFIG_CMD_FASTBOOT=y CONFIG_CMD_SUNXI_DMA=y CONFIG_CMD_SUNXI_CLK=y CONFIG_CMD_SUNXI_MEMTEST=y CONFIG_CMD_PART=y CONFIG_CMD_SUNXI_AUTO_FEL=n CONFIG_CMD_SUNXI_BOOTR=y #arisc #CONFIG_SUNXI_ARISC_EXIST=y # CONFIG_SUNXI_INITRD_ROUTINE is not set #dsp #CONFIG_XTENSA_DSP=y #riscv #CONFIG_RISCV_E907=y CONFIG_SUNXI_ARM_SOFT_FP=y CONFIG_USE_PRIVATE_LIBGCC=y # # BOOT GUI # CONFIG_BOOT_GUI=y # CONFIG_UPDATE_DISPLAY_MODE is not set # CONFIG_CONFIG_LCD_CHECK_SKIP_OPEN is not set # CONFIG_BOOT_GUI_DOUBLE_BUF is not set # CONFIG_BOOT_GUI_TEST is not set # # SUNXI LOGO DISPLAY # CONFIG_CMD_SUNXI_BMP=y # CONFIG_SUNXI_SPINOR_BMP is not set # CONFIG_ENABLE_ADVERT_PICTURE is not set # CONFIG_SUNXI_SPINOR_JPEG is not set # CONFIG_CMD_SUNXI_JPEG is not set CONFIG_DISP2_SUNXI=y # CONFIG_HDMI_DISP2_SUNXI is not set # CONFIG_HDMI2_DISP2_SUNXI is not set # CONFIG_VDPO_DISP2_SUNXI is not set # CONFIG_TV_DISP2_SUNXI is not set # CONFIG_EDP_DISP2_SUNXI is not set # CONFIG_EINK200_SUNXI is not set # # LCD panels select # # CONFIG_LCD_SUPPORT_GG1P4062UTSW is not set # CONFIG_LCD_SUPPORT_DX0960BE40A1 is not set # CONFIG_LCD_SUPPORT_TFT720X1280 is not set # CONFIG_LCD_SUPPORT_FD055HD003S is not set # CONFIG_LCD_SUPPORT_HE0801A068 is not set # CONFIG_LCD_SUPPORT_ILI9341 is not set # CONFIG_LCD_SUPPORT_LH219WQ1 is not set # CONFIG_LCD_SUPPORT_LS029B3SX02 is not set # CONFIG_LCD_SUPPORT_LT070ME05000 is not set # CONFIG_LCD_SUPPORT_S6D7AA0X01 is not set # CONFIG_LCD_SUPPORT_T27P06 is not set # CONFIG_LCD_SUPPORT_TFT720x1280 is not set # CONFIG_LCD_SUPPORT_WTQ05027D01 is not set # CONFIG_LCD_SUPPORT_H245QBN02 is not set # CONFIG_LCD_SUPPORT_ST7789V is not set # CONFIG_LCD_SUPPORT_ST7796S is not set # CONFIG_LCD_SUPPORT_ST7701S is not set # CONFIG_LCD_SUPPORT_T30P106 is not set # CONFIG_LCD_SUPPORT_TO20T20000 is not set # CONFIG_LCD_SUPPORT_FRD450H40014 is not set # CONFIG_LCD_SUPPORT_S2003T46G is not set # CONFIG_LCD_SUPPORT_WILLIAMLCD is not set # CONFIG_LCD_SUPPORT_LQ101R1SX03 is not set # CONFIG_LCD_SUPPORT_INET_DSI_PANEL is not set # CONFIG_LCD_SUPPORT_WTL096601G03 is not set # CONFIG_LCD_SUPPORT_BP101WX1 is not set # CONFIG_LCD_SUPPORT_M133X56 is not set # CONFIG_LCD_SUPPORT_K101IM2QA04 is not set # CONFIG_LCD_SUPPORT_K101IM2BYL02L is not set # CONFIG_LCD_SUPPORT_FX070 is not set # CONFIG_LCD_SUPPORT_M101B31 is not set # CONFIG_LCD_SUPPORT_CC08021801_310_800X1280 is not set # CONFIG_LCD_SUPPORT_KD101NA5 is not set # CONFIG_LCD_SUPPORT_KD070D57 is not set # CONFIG_LCD_SUPPORT_ZS080NI4003E7H3H_A is not set # CONFIG_LCD_SUPPORT_K080_IM2HYL802R_800X1280 is not set # CONFIG_LCD_SUPPORT_K101_IM2BYL02_L_800X1280 is not set # CONFIG_LCD_SUPPORT_JD9366AB_3 is not set # CONFIG_LCD_SUPPORT_TFT08006 is not set CONFIG_LCD_SUPPORT_ST7701S_G5=y CONFIG_LCD_SUPPORT_T050K589=y CONFIG_LCD_SUPPORT_JD9161Z_MIPI=y CONFIG_LCD_SUPPORT_ICN6202=y # # Display engine feature select # # CONFIG_DISP2_SUNXI_SUPPORT_SMBL is not set # CONFIG_DISP2_SUNXI_SUPPORT_ENAHNCE is not set # CONFIG_SUNXI_TV_FASTLOGO is not set # CONFIG_SUNXI_FASTLOGO_JPEG is not set -
T527 使用 DRM 驱动 edp 屏幕发布在 T Series
进入 menuconfig 勾选 drm 驱动
./build.sh menuconfig先勾选 DRM
再勾选 DRM 驱动
选择驱动的phy
选择屏幕
选择 general 屏幕面板驱动
关闭原来的 disp2 fbdev 驱动
配置设备树
edp_panel_backlight: edp_backlight { compatible = "pwm-backlight"; status = "okay"; brightness-levels = < 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255>; default-brightness-level = <200>; enable-gpios = <&pio PI 5 GPIO_ACTIVE_HIGH>; /* power-supply = <®_backlight_12v>; */ pwms = <&a_pwm 5 5000000 0>; }; edp_panel: edp_panel { compatible = "edp-general-panel"; status = "okay"; power0-supply = <®_dcdc4>; backlight = <&edp_panel_backlight>; panel-timing { clock-frequency = <348577920>; /* pixel clock */ hactive = <2560>; hback-porch = <120>; hfront-porch = <88>; hsync-len = <32>; vactive = <1600>; vback-porch = <71>; vfront-porch = <28>; vsync-len = <5>; /* hor_sync_polarity */ hsync-active = <1>; /* ver_sync_polarity */ vsync-active = <1>; // unused now /* de-active = <1>; pixelclk-active = <1>; syncclk-active = <0>; interlaced; doublescan; doubleclk; */ }; ports { #address-cells = <1>; #size-cells = <0>; panel_in: port@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; edp_panel_in: endpoint@0 { reg = <0>; remote-endpoint = <&edp_panel_out>; }; }; }; };和 drm_edp 的配置
&drm_edp { status = "okay"; edp_ssc_en = <0>; edp_ssc_mode = <0>; edp_psr_support = <0>; edp_colordepth = <8>; /* 6/8/10/12/16 */ edp_color_fmt = <0>; /* 0:RGB 1: YUV444 2: YUV422 */ lane1_sw = <0>; lane1_pre = <0>; lane2_sw = <0>; lane2_pre = <0>; lane3_sw = <0>; lane3_pre = <0>; efficient_training = <0>; sink_capacity_prefer = <1>; edid_timings_prefer = <1>; timings_fixed = <1>; vcc-edp-supply = <®_bldo3>; vdd-edp-supply = <®_dcdc2>; panel = <&edp_panel>; ports { edp_out: port@1 { edp_panel_out: endpoint@0 { reg = <0>; remote-endpoint = <&edp_panel_in>; }; }; }; };
